arm64: dts: qcom: sm8350: move DPU opp-table to its node

The Qualcomm MDSS bindings expect that DPU opp-table is defined within
DPU node:

  sm8350-hdk.dtb: display-subsystem@ae00000: Unevaluated properties are not allowed ('opp-table' was unexpected)
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20231107103540.27353-3-krzysztof.kozlowski@linaro.orgSigned-off-by: Bjorn Andersson <andersson@kernel.org>

arch/arm64/boot/dts/qcom/sm8350.dtsi

@@ -2452,6 +2452,34 @@ mdss: display-subsystem@ae00000 {
 			#size-cells = <2>;
 			ranges;
 
+			mdss_mdp: display-controller@ae01000 {
+				compatible = "qcom,sm8350-dpu";
+				reg = <0 0x0ae01000 0 0x8f000>,
+				      <0 0x0aeb0000 0 0x2008>;
+				reg-names = "mdp", "vbif";
+
+				clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
+					<&gcc GCC_DISP_SF_AXI_CLK>,
+					<&dispcc DISP_CC_MDSS_AHB_CLK>,
+					<&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
+					<&dispcc DISP_CC_MDSS_MDP_CLK>,
+					<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+				clock-names = "bus",
+					      "nrt_bus",
+					      "iface",
+					      "lut",
+					      "core",
+					      "vsync";
+
+				assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+				assigned-clock-rates = <19200000>;
+
+				operating-points-v2 = <&dpu_opp_table>;
+				power-domains = <&rpmhpd RPMHPD_MMCX>;
+
+				interrupt-parent = <&mdss>;
+				interrupts = <0>;
+
 				dpu_opp_table: opp-table {
 					compatible = "operating-points-v2";
 
@@ -2481,34 +2509,6 @@ opp-460000000 {
 					};
 				};
 
-			mdss_mdp: display-controller@ae01000 {
-				compatible = "qcom,sm8350-dpu";
-				reg = <0 0x0ae01000 0 0x8f000>,
-				      <0 0x0aeb0000 0 0x2008>;
-				reg-names = "mdp", "vbif";
-
-				clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
-					<&gcc GCC_DISP_SF_AXI_CLK>,
-					<&dispcc DISP_CC_MDSS_AHB_CLK>,
-					<&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
-					<&dispcc DISP_CC_MDSS_MDP_CLK>,
-					<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
-				clock-names = "bus",
-					      "nrt_bus",
-					      "iface",
-					      "lut",
-					      "core",
-					      "vsync";
-
-				assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
-				assigned-clock-rates = <19200000>;
-
-				operating-points-v2 = <&dpu_opp_table>;
-				power-domains = <&rpmhpd RPMHPD_MMCX>;
-
-				interrupt-parent = <&mdss>;
-				interrupts = <0>;
-
 				ports {
 					#address-cells = <1>;
 					#size-cells = <0>;