Commit fdd85a05 authored by Hardik T Shah's avatar Hardik T Shah Committed by Mark Brown

ASoC: Intel: Skylake: Fix DMA position reporting for capture stream

As per hardware recommendation, for every capture stream completion
following operations need to be done in order to reflect the actual
data that is received in position buffer.

1. Wait for 20us before reading the DMA position in buffer once the
interrupt is generated for stream completion.
2. Read any of the register to flush the DMA position value. This is
dummy read operation.
Signed-off-by: default avatarDharageswari R <dharageswari.r@intel.com>
Signed-off-by: default avatarHardik T Shah <hardik.t.shah@intel.com>
Signed-off-by: default avatarJeeja KP <jeeja.kp@intel.com>
Acked-by: default avatarVinod Koul <vinod.koul@intel.com>
Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent b26199ea
...@@ -21,6 +21,7 @@ ...@@ -21,6 +21,7 @@
#include <linux/pci.h> #include <linux/pci.h>
#include <linux/pm_runtime.h> #include <linux/pm_runtime.h>
#include <linux/delay.h>
#include <sound/pcm_params.h> #include <sound/pcm_params.h>
#include <sound/soc.h> #include <sound/soc.h>
#include "skl.h" #include "skl.h"
...@@ -1063,13 +1064,31 @@ static snd_pcm_uframes_t skl_platform_pcm_pointer ...@@ -1063,13 +1064,31 @@ static snd_pcm_uframes_t skl_platform_pcm_pointer
* HAD space reflects the actual data that is transferred. * HAD space reflects the actual data that is transferred.
* Use the position buffer for capture, as DPIB write gets * Use the position buffer for capture, as DPIB write gets
* completed earlier than the actual data written to the DDR. * completed earlier than the actual data written to the DDR.
*
* For capture stream following workaround is required to fix the
* incorrect position reporting.
*
* 1. Wait for 20us before reading the DMA position in buffer once
* the interrupt is generated for stream completion as update happens
* on the HDA frame boundary i.e. 20.833uSec.
* 2. Read DPIB register to flush the DMA position value. This dummy
* read is required to flush DMA position value.
* 3. Read the DMA Position-in-Buffer. This value now will be equal to
* or greater than period boundary.
*/ */
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
pos = readl(ebus->bus.remap_addr + AZX_REG_VS_SDXDPIB_XBASE + pos = readl(ebus->bus.remap_addr + AZX_REG_VS_SDXDPIB_XBASE +
(AZX_REG_VS_SDXDPIB_XINTERVAL * (AZX_REG_VS_SDXDPIB_XINTERVAL *
hdac_stream(hstream)->index)); hdac_stream(hstream)->index));
else } else {
udelay(20);
readl(ebus->bus.remap_addr +
AZX_REG_VS_SDXDPIB_XBASE +
(AZX_REG_VS_SDXDPIB_XINTERVAL *
hdac_stream(hstream)->index));
pos = snd_hdac_stream_get_pos_posbuf(hdac_stream(hstream)); pos = snd_hdac_stream_get_pos_posbuf(hdac_stream(hstream));
}
if (pos >= hdac_stream(hstream)->bufsize) if (pos >= hdac_stream(hstream)->bufsize)
pos = 0; pos = 0;
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment