Commit fe38ea56 authored by Ben Dooks's avatar Ben Dooks Committed by Russell King

[ARM] 3246/1: S3C24XX - retab clock list in arch/arm/mach-s3c2410/clock.c

Patch from Ben Dooks

Properly tabulate the clock table in arch/arm/mach-s3c2410/clock.c
and put the requisite commas on the end of the structs.

Fix the comment about clock enable and disable in the setup code
Signed-off-by: default avatarBen Dooks <ben-linux@fluff.org>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent 9d4ae727
...@@ -253,100 +253,101 @@ struct clk s3c24xx_uclk = { ...@@ -253,100 +253,101 @@ struct clk s3c24xx_uclk = {
/* clock definitions */ /* clock definitions */
static struct clk init_clocks[] = { static struct clk init_clocks[] = {
{ .name = "nand", {
.name = "nand",
.id = -1, .id = -1,
.parent = &clk_h, .parent = &clk_h,
.enable = s3c24xx_clkcon_enable, .enable = s3c24xx_clkcon_enable,
.ctrlbit = S3C2410_CLKCON_NAND .ctrlbit = S3C2410_CLKCON_NAND,
}, }, {
{ .name = "lcd", .name = "lcd",
.id = -1, .id = -1,
.parent = &clk_h, .parent = &clk_h,
.enable = s3c24xx_clkcon_enable, .enable = s3c24xx_clkcon_enable,
.ctrlbit = S3C2410_CLKCON_LCDC .ctrlbit = S3C2410_CLKCON_LCDC,
}, }, {
{ .name = "usb-host", .name = "usb-host",
.id = -1, .id = -1,
.parent = &clk_h, .parent = &clk_h,
.enable = s3c24xx_clkcon_enable, .enable = s3c24xx_clkcon_enable,
.ctrlbit = S3C2410_CLKCON_USBH .ctrlbit = S3C2410_CLKCON_USBH,
}, }, {
{ .name = "usb-device", .name = "usb-device",
.id = -1, .id = -1,
.parent = &clk_h, .parent = &clk_h,
.enable = s3c24xx_clkcon_enable, .enable = s3c24xx_clkcon_enable,
.ctrlbit = S3C2410_CLKCON_USBD .ctrlbit = S3C2410_CLKCON_USBD,
}, }, {
{ .name = "timers", .name = "timers",
.id = -1, .id = -1,
.parent = &clk_p, .parent = &clk_p,
.enable = s3c24xx_clkcon_enable, .enable = s3c24xx_clkcon_enable,
.ctrlbit = S3C2410_CLKCON_PWMT .ctrlbit = S3C2410_CLKCON_PWMT,
}, }, {
{ .name = "sdi", .name = "sdi",
.id = -1, .id = -1,
.parent = &clk_p, .parent = &clk_p,
.enable = s3c24xx_clkcon_enable, .enable = s3c24xx_clkcon_enable,
.ctrlbit = S3C2410_CLKCON_SDI .ctrlbit = S3C2410_CLKCON_SDI,
}, }, {
{ .name = "uart", .name = "uart",
.id = 0, .id = 0,
.parent = &clk_p, .parent = &clk_p,
.enable = s3c24xx_clkcon_enable, .enable = s3c24xx_clkcon_enable,
.ctrlbit = S3C2410_CLKCON_UART0 .ctrlbit = S3C2410_CLKCON_UART0,
}, }, {
{ .name = "uart", .name = "uart",
.id = 1, .id = 1,
.parent = &clk_p, .parent = &clk_p,
.enable = s3c24xx_clkcon_enable, .enable = s3c24xx_clkcon_enable,
.ctrlbit = S3C2410_CLKCON_UART1 .ctrlbit = S3C2410_CLKCON_UART1,
}, }, {
{ .name = "uart", .name = "uart",
.id = 2, .id = 2,
.parent = &clk_p, .parent = &clk_p,
.enable = s3c24xx_clkcon_enable, .enable = s3c24xx_clkcon_enable,
.ctrlbit = S3C2410_CLKCON_UART2 .ctrlbit = S3C2410_CLKCON_UART2,
}, }, {
{ .name = "gpio", .name = "gpio",
.id = -1, .id = -1,
.parent = &clk_p, .parent = &clk_p,
.enable = s3c24xx_clkcon_enable, .enable = s3c24xx_clkcon_enable,
.ctrlbit = S3C2410_CLKCON_GPIO .ctrlbit = S3C2410_CLKCON_GPIO,
}, }, {
{ .name = "rtc", .name = "rtc",
.id = -1, .id = -1,
.parent = &clk_p, .parent = &clk_p,
.enable = s3c24xx_clkcon_enable, .enable = s3c24xx_clkcon_enable,
.ctrlbit = S3C2410_CLKCON_RTC .ctrlbit = S3C2410_CLKCON_RTC,
}, }, {
{ .name = "adc", .name = "adc",
.id = -1, .id = -1,
.parent = &clk_p, .parent = &clk_p,
.enable = s3c24xx_clkcon_enable, .enable = s3c24xx_clkcon_enable,
.ctrlbit = S3C2410_CLKCON_ADC .ctrlbit = S3C2410_CLKCON_ADC,
}, }, {
{ .name = "i2c", .name = "i2c",
.id = -1, .id = -1,
.parent = &clk_p, .parent = &clk_p,
.enable = s3c24xx_clkcon_enable, .enable = s3c24xx_clkcon_enable,
.ctrlbit = S3C2410_CLKCON_IIC .ctrlbit = S3C2410_CLKCON_IIC,
}, }, {
{ .name = "iis", .name = "iis",
.id = -1, .id = -1,
.parent = &clk_p, .parent = &clk_p,
.enable = s3c24xx_clkcon_enable, .enable = s3c24xx_clkcon_enable,
.ctrlbit = S3C2410_CLKCON_IIS .ctrlbit = S3C2410_CLKCON_IIS,
}, }, {
{ .name = "spi", .name = "spi",
.id = -1, .id = -1,
.parent = &clk_p, .parent = &clk_p,
.enable = s3c24xx_clkcon_enable, .enable = s3c24xx_clkcon_enable,
.ctrlbit = S3C2410_CLKCON_SPI .ctrlbit = S3C2410_CLKCON_SPI,
}, }, {
{ .name = "watchdog", .name = "watchdog",
.id = -1, .id = -1,
.parent = &clk_p, .parent = &clk_p,
.ctrlbit = 0 .ctrlbit = 0,
} }
}; };
...@@ -390,15 +391,14 @@ int __init s3c24xx_setup_clocks(unsigned long xtal, ...@@ -390,15 +391,14 @@ int __init s3c24xx_setup_clocks(unsigned long xtal,
clk_p.rate = pclk; clk_p.rate = pclk;
clk_f.rate = fclk; clk_f.rate = fclk;
/* it looks like just setting the register here is not good /* We must be careful disabling the clocks we are not intending to
* enough, and causes the odd hang at initial boot time, so * be using at boot time, as subsytems such as the LCD which do
* do all of them indivdually. * their own DMA requests to the bus can cause the system to lockup
* * if they where in the middle of requesting bus access.
* I think disabling the LCD clock if the LCD is active is
* very dangerous, and therefore the bootloader should be
* careful to not enable the LCD clock if it is not needed.
* *
* and of course, this looks neater * Disabling the LCD clock if the LCD is active is very dangerous,
* and therefore the bootloader should be careful to not enable
* the LCD clock if it is not needed.
*/ */
s3c24xx_clk_enable(S3C2410_CLKCON_NAND, 0); s3c24xx_clk_enable(S3C2410_CLKCON_NAND, 0);
......
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