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Commit fec57a8e authored by Ian Rogers's avatar Ian Rogers Committed by Arnaldo Carvalho de Melo
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perf vendor events intel: Refresh broadwell metrics and events 

Update the broadwell metrics and events using the new tooling from:

  https://github.com/intel/perfmon

The metrics are unchanged but the formulas differ due to parentheses,
use of exponents and removal of redundant operations like "* 1".  The
events are unchanged but unused json values are removed, implicit
umasks of 0 are dropped and duplicate short and long descriptions have
the long one dropped. This increases consistency across the json
files.
Signed-off-by: default avatarIan Rogers <irogers@google.com>
Acked-by: default avatarKan Liang <kan.liang@linux.intel.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.g.garry@oracle.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Xing Zhengjun <zhengjun.xing@linux.intel.com>
Link: https://lore.kernel.org/r/20221215064755.1620246-6-irogers@google.comSigned-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent 6fa91f64
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Showing with 84 additions and 2396 deletions
tools/perf/pmu-events/arch/x86/broadwell/bdw-metrics.json
View file @ fec57a8e
...@@ -110,7 +110,7 @@ ...@@ -110,7 +110,7 @@
}, },
{ {
"BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations", "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations",
"MetricExpr": "(UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ((INT_MISC.RECOVERY_CYCLES_ANY / 2) if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / SLOTS", "MetricExpr": "(UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * (INT_MISC.RECOVERY_CYCLES_ANY / 2 if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / SLOTS",
"MetricGroup": "TopdownL1;tma_L1_group", "MetricGroup": "TopdownL1;tma_L1_group",
"MetricName": "tma_bad_speculation", "MetricName": "tma_bad_speculation",
"PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.", "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.",
...@@ -118,7 +118,7 @@ ...@@ -118,7 +118,7 @@
}, },
{ {
"BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction", "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction",
"MetricExpr": "(BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT)) * tma_bad_speculation", "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * tma_bad_speculation",
"MetricGroup": "BadSpec;BrMispredicts;TopdownL2;tma_L2_group;tma_bad_speculation_group", "MetricGroup": "BadSpec;BrMispredicts;TopdownL2;tma_L2_group;tma_bad_speculation_group",
"MetricName": "tma_branch_mispredicts", "MetricName": "tma_branch_mispredicts",
"PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES", "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES",
...@@ -142,7 +142,7 @@ ...@@ -142,7 +142,7 @@
}, },
{ {
"BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck", "BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck",
"MetricExpr": "((CYCLE_ACTIVITY.STALLS_MEM_ANY + RESOURCE_STALLS.SB) / (CYCLE_ACTIVITY.STALLS_TOTAL + UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if (IPC > 1.8) else UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC - RS_EVENTS.EMPTY_CYCLES if (tma_fetch_latency > 0.1) else RESOURCE_STALLS.SB)) * tma_backend_bound", "MetricExpr": "(CYCLE_ACTIVITY.STALLS_MEM_ANY + RESOURCE_STALLS.SB) / (CYCLE_ACTIVITY.STALLS_TOTAL + UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if IPC > 1.8 else (UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC - RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else RESOURCE_STALLS.SB)) * tma_backend_bound",
"MetricGroup": "Backend;TopdownL2;tma_L2_group;tma_backend_bound_group", "MetricGroup": "Backend;TopdownL2;tma_L2_group;tma_backend_bound_group",
"MetricName": "tma_memory_bound", "MetricName": "tma_memory_bound",
"PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).", "PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).",
...@@ -174,7 +174,7 @@ ...@@ -174,7 +174,7 @@
}, },
{ {
"BriefDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations", "BriefDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations",
"MetricExpr": "(MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO) / CLKS", "MetricExpr": "MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO) / CLKS",
"MetricGroup": "Offcore;TopdownL4;tma_l1_bound_group", "MetricGroup": "Offcore;TopdownL4;tma_l1_bound_group",
"MetricName": "tma_lock_latency", "MetricName": "tma_lock_latency",
"PublicDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them. Sample with: MEM_UOPS_RETIRED.LOCK_LOADS_PS", "PublicDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them. Sample with: MEM_UOPS_RETIRED.LOCK_LOADS_PS",
...@@ -214,7 +214,7 @@ ...@@ -214,7 +214,7 @@
}, },
{ {
"BriefDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core", "BriefDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core",
"MetricExpr": "(MEM_LOAD_UOPS_RETIRED.L3_HIT / (MEM_LOAD_UOPS_RETIRED.L3_HIT + 7 * MEM_LOAD_UOPS_RETIRED.L3_MISS)) * CYCLE_ACTIVITY.STALLS_L2_MISS / CLKS", "MetricExpr": "MEM_LOAD_UOPS_RETIRED.L3_HIT / (MEM_LOAD_UOPS_RETIRED.L3_HIT + 7 * MEM_LOAD_UOPS_RETIRED.L3_MISS) * CYCLE_ACTIVITY.STALLS_L2_MISS / CLKS",
"MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group", "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
"MetricName": "tma_l3_bound", "MetricName": "tma_l3_bound",
"PublicDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core. Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L3_HIT_PS", "PublicDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core. Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L3_HIT_PS",
...@@ -222,7 +222,7 @@ ...@@ -222,7 +222,7 @@
}, },
{ {
"BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses", "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses",
"MetricExpr": "(60 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_RETIRED.L3_MISS))) + 43 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_RETIRED.L3_MISS)))) / CLKS", "MetricExpr": "(60 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.L3_MISS))) + 43 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.L3_MISS)))) / CLKS",
"MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_l3_bound_group", "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_l3_bound_group",
"MetricName": "tma_contested_accesses", "MetricName": "tma_contested_accesses",
"PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS_PS", "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS_PS",
...@@ -230,7 +230,7 @@ ...@@ -230,7 +230,7 @@
}, },
{ {
"BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses", "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses",
"MetricExpr": "43 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_RETIRED.L3_MISS))) / CLKS", "MetricExpr": "43 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.L3_MISS))) / CLKS",
"MetricGroup": "Offcore;Snoop;TopdownL4;tma_l3_bound_group", "MetricGroup": "Offcore;Snoop;TopdownL4;tma_l3_bound_group",
"MetricName": "tma_data_sharing", "MetricName": "tma_data_sharing",
"PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT_PS", "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT_PS",
...@@ -238,7 +238,7 @@ ...@@ -238,7 +238,7 @@
}, },
{ {
"BriefDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited)", "BriefDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited)",
"MetricExpr": "29 * (MEM_LOAD_UOPS_RETIRED.L3_HIT * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_RETIRED.L3_MISS))) / CLKS", "MetricExpr": "29 * (MEM_LOAD_UOPS_RETIRED.L3_HIT * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.L3_MISS))) / CLKS",
"MetricGroup": "MemoryLat;TopdownL4;tma_l3_bound_group", "MetricGroup": "MemoryLat;TopdownL4;tma_l3_bound_group",
"MetricName": "tma_l3_hit_latency", "MetricName": "tma_l3_hit_latency",
"PublicDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_UOPS_RETIRED.L3_HIT_PS", "PublicDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_UOPS_RETIRED.L3_HIT_PS",
...@@ -246,7 +246,7 @@ ...@@ -246,7 +246,7 @@
}, },
{ {
"BriefDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors)", "BriefDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors)",
"MetricExpr": "((OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2) if #SMT_on else OFFCORE_REQUESTS_BUFFER.SQ_FULL) / CORE_CLKS", "MetricExpr": "(OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2 if #SMT_on else OFFCORE_REQUESTS_BUFFER.SQ_FULL) / CORE_CLKS",
"MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_l3_bound_group", "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_l3_bound_group",
"MetricName": "tma_sq_full", "MetricName": "tma_sq_full",
"PublicDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors). The Super Queue is used for requests to access the L2 cache or to go out to the Uncore.", "PublicDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors). The Super Queue is used for requests to access the L2 cache or to go out to the Uncore.",
...@@ -254,7 +254,7 @@ ...@@ -254,7 +254,7 @@
}, },
{ {
"BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads", "BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads",
"MetricExpr": "(1 - (MEM_LOAD_UOPS_RETIRED.L3_HIT / (MEM_LOAD_UOPS_RETIRED.L3_HIT + 7 * MEM_LOAD_UOPS_RETIRED.L3_MISS))) * CYCLE_ACTIVITY.STALLS_L2_MISS / CLKS", "MetricExpr": "(1 - MEM_LOAD_UOPS_RETIRED.L3_HIT / (MEM_LOAD_UOPS_RETIRED.L3_HIT + 7 * MEM_LOAD_UOPS_RETIRED.L3_MISS)) * CYCLE_ACTIVITY.STALLS_L2_MISS / CLKS",
"MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group", "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
"MetricName": "tma_dram_bound", "MetricName": "tma_dram_bound",
"PublicDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L3_MISS_PS", "PublicDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L3_MISS_PS",
...@@ -286,7 +286,7 @@ ...@@ -286,7 +286,7 @@
}, },
{ {
"BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses", "BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses",
"MetricExpr": "((L2_RQSTS.RFO_HIT * 9 * (1 - (MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES))) + (1 - (MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES)) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / CLKS", "MetricExpr": "(L2_RQSTS.RFO_HIT * 9 * (1 - MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES) + (1 - MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / CLKS",
"MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_store_bound_group", "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_store_bound_group",
"MetricName": "tma_store_latency", "MetricName": "tma_store_latency",
"PublicDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full)", "PublicDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full)",
...@@ -334,7 +334,7 @@ ...@@ -334,7 +334,7 @@
}, },
{ {
"BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related)", "BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related)",
"MetricExpr": "((CYCLE_ACTIVITY.STALLS_TOTAL + UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if (IPC > 1.8) else UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC - RS_EVENTS.EMPTY_CYCLES if (tma_fetch_latency > 0.1) else RESOURCE_STALLS.SB) - RESOURCE_STALLS.SB - CYCLE_ACTIVITY.STALLS_MEM_ANY) / CLKS", "MetricExpr": "((CYCLE_ACTIVITY.STALLS_TOTAL + UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if IPC > 1.8 else (UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC - RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else RESOURCE_STALLS.SB)) - RESOURCE_STALLS.SB - CYCLE_ACTIVITY.STALLS_MEM_ANY) / CLKS",
"MetricGroup": "PortsUtil;TopdownL3;tma_core_bound_group", "MetricGroup": "PortsUtil;TopdownL3;tma_core_bound_group",
"MetricName": "tma_ports_utilization", "MetricName": "tma_ports_utilization",
"PublicDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.", "PublicDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.",
...@@ -342,7 +342,7 @@ ...@@ -342,7 +342,7 @@
}, },
{ {
"BriefDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise)", "BriefDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
"MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,inv\\,cmask\\=1@) / 2 if #SMT_on else (CYCLE_ACTIVITY.STALLS_TOTAL - RS_EVENTS.EMPTY_CYCLES if (tma_fetch_latency > 0.1) else 0) / CORE_CLKS", "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,inv\\,cmask\\=1@ / 2 if #SMT_on else (CYCLE_ACTIVITY.STALLS_TOTAL - RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0) / CORE_CLKS)",
"MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group", "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
"MetricName": "tma_ports_utilized_0", "MetricName": "tma_ports_utilized_0",
"PublicDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric.", "PublicDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric.",
...@@ -350,7 +350,7 @@ ...@@ -350,7 +350,7 @@
}, },
{ {
"BriefDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)", "BriefDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
"MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@) / 2 if #SMT_on else (UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC) / CORE_CLKS", "MetricExpr": "((cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@) / 2 if #SMT_on else (UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC) / CORE_CLKS)",
"MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group", "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
"MetricName": "tma_ports_utilized_1", "MetricName": "tma_ports_utilized_1",
"PublicDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful.", "PublicDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful.",
...@@ -358,7 +358,7 @@ ...@@ -358,7 +358,7 @@
}, },
{ {
"BriefDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)", "BriefDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
"MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@) / 2 if #SMT_on else (UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC - UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC) / CORE_CLKS", "MetricExpr": "((cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@) / 2 if #SMT_on else (UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC - UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC) / CORE_CLKS)",
"MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group", "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
"MetricName": "tma_ports_utilized_2", "MetricName": "tma_ports_utilized_2",
"PublicDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop.", "PublicDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop.",
...@@ -366,14 +366,14 @@ ...@@ -366,14 +366,14 @@
}, },
{ {
"BriefDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise).", "BriefDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise).",
"MetricExpr": "((cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@ / 2) if #SMT_on else UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC) / CORE_CLKS", "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@ / 2 if #SMT_on else UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC) / CORE_CLKS",
"MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group", "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
"MetricName": "tma_ports_utilized_3m", "MetricName": "tma_ports_utilized_3m",
"ScaleUnit": "100%" "ScaleUnit": "100%"
}, },
{ {
"BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations.", "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations.",
"MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_0 + UOPS_DISPATCHED_PORT.PORT_1 + UOPS_DISPATCHED_PORT.PORT_5 + UOPS_DISPATCHED_PORT.PORT_6) / (4 * CORE_CLKS)", "MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_0 + UOPS_DISPATCHED_PORT.PORT_1 + UOPS_DISPATCHED_PORT.PORT_5 + UOPS_DISPATCHED_PORT.PORT_6) / SLOTS",
"MetricGroup": "TopdownL5;tma_ports_utilized_3m_group", "MetricGroup": "TopdownL5;tma_ports_utilized_3m_group",
"MetricName": "tma_alu_op_utilization", "MetricName": "tma_alu_op_utilization",
"ScaleUnit": "100%" "ScaleUnit": "100%"
...@@ -429,7 +429,7 @@ ...@@ -429,7 +429,7 @@
}, },
{ {
"BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations", "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations",
"MetricExpr": "UOPS_DISPATCHED_PORT.PORT_4 / CORE_CLKS", "MetricExpr": "tma_port_4",
"MetricGroup": "TopdownL5;tma_ports_utilized_3m_group", "MetricGroup": "TopdownL5;tma_ports_utilized_3m_group",
"MetricName": "tma_store_op_utilization", "MetricName": "tma_store_op_utilization",
"ScaleUnit": "100%" "ScaleUnit": "100%"
...@@ -522,7 +522,7 @@ ...@@ -522,7 +522,7 @@
}, },
{ {
"BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit", "BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit",
"MetricExpr": "(UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY) * IDQ.MS_UOPS / SLOTS", "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY * IDQ.MS_UOPS / SLOTS",
"MetricGroup": "MicroSeq;TopdownL3;tma_heavy_operations_group", "MetricGroup": "MicroSeq;TopdownL3;tma_heavy_operations_group",
"MetricName": "tma_microcode_sequencer", "MetricName": "tma_microcode_sequencer",
"PublicDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided. Sample with: IDQ.MS_UOPS", "PublicDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided. Sample with: IDQ.MS_UOPS",
...@@ -595,26 +595,26 @@ ...@@ -595,26 +595,26 @@
}, },
{ {
"BriefDescription": "Floating Point Operations Per Cycle", "BriefDescription": "Floating Point Operations Per Cycle",
"MetricExpr": "(1 * (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / CORE_CLKS", "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / CORE_CLKS",
"MetricGroup": "Flops;Ret", "MetricGroup": "Flops;Ret",
"MetricName": "FLOPc" "MetricName": "FLOPc"
}, },
{ {
"BriefDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width)", "BriefDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width)",
"MetricExpr": "((FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)) / (2 * CORE_CLKS)", "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)) / (2 * CORE_CLKS)",
"MetricGroup": "Cor;Flops;HPC", "MetricGroup": "Cor;Flops;HPC",
"MetricName": "FP_Arith_Utilization", "MetricName": "FP_Arith_Utilization",
"PublicDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). Values > 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less common)." "PublicDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). Values > 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less common)."
}, },
{ {
"BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-core", "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-core",
"MetricExpr": "UOPS_EXECUTED.THREAD / ((cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ / 2) if #SMT_on else UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC)", "MetricExpr": "UOPS_EXECUTED.THREAD / (cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ / 2 if #SMT_on else UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC)",
"MetricGroup": "Backend;Cor;Pipeline;PortsUtil", "MetricGroup": "Backend;Cor;Pipeline;PortsUtil",
"MetricName": "ILP" "MetricName": "ILP"
}, },
{ {
"BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core", "BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core",
"MetricExpr": "((CPU_CLK_UNHALTED.THREAD / 2) * (1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK)) if #core_wide < 1 else (CPU_CLK_UNHALTED.THREAD_ANY / 2) if #SMT_on else CLKS", "MetricExpr": "(CPU_CLK_UNHALTED.THREAD / 2 * (1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK) if #core_wide < 1 else (CPU_CLK_UNHALTED.THREAD_ANY / 2 if #SMT_on else CLKS))",
"MetricGroup": "SMT", "MetricGroup": "SMT",
"MetricName": "CORE_CLKS" "MetricName": "CORE_CLKS"
}, },
...@@ -656,13 +656,13 @@ ...@@ -656,13 +656,13 @@
}, },
{ {
"BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)", "BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)",
"MetricExpr": "INST_RETIRED.ANY / (1 * (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)", "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)",
"MetricGroup": "Flops;InsType", "MetricGroup": "Flops;InsType",
"MetricName": "IpFLOP" "MetricName": "IpFLOP"
}, },
{ {
"BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate)", "BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate)",
"MetricExpr": "INST_RETIRED.ANY / ((FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE))", "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE))",
"MetricGroup": "Flops;InsType", "MetricGroup": "Flops;InsType",
"MetricName": "IpArith", "MetricName": "IpArith",
"PublicDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). May undercount due to FMA double counting. Approximated prior to BDW." "PublicDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). May undercount due to FMA double counting. Approximated prior to BDW."
...@@ -715,7 +715,7 @@ ...@@ -715,7 +715,7 @@
}, },
{ {
"BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)", "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)",
"MetricExpr": "IDQ.DSB_UOPS / ((IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS))", "MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS)",
"MetricGroup": "DSB;Fed;FetchBW", "MetricGroup": "DSB;Fed;FetchBW",
"MetricName": "DSB_Coverage" "MetricName": "DSB_Coverage"
}, },
...@@ -727,13 +727,13 @@ ...@@ -727,13 +727,13 @@
}, },
{ {
"BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)", "BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)",
"MetricExpr": " (tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) * SLOTS / BR_MISP_RETIRED.ALL_BRANCHES", "MetricExpr": "(tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) * SLOTS / BR_MISP_RETIRED.ALL_BRANCHES",
"MetricGroup": "Bad;BrMispredicts", "MetricGroup": "Bad;BrMispredicts",
"MetricName": "Branch_Misprediction_Cost" "MetricName": "Branch_Misprediction_Cost"
}, },
{ {
"BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)", "BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)",
"MetricExpr": "L1D_PEND_MISS.PENDING / (MEM_LOAD_UOPS_RETIRED.L1_MISS + mem_load_uops_retired.hit_lfb)", "MetricExpr": "L1D_PEND_MISS.PENDING / (MEM_LOAD_UOPS_RETIRED.L1_MISS + MEM_LOAD_UOPS_RETIRED.HIT_LFB)",
"MetricGroup": "Mem;MemoryBound;MemoryLat", "MetricGroup": "Mem;MemoryBound;MemoryLat",
"MetricName": "Load_Miss_Real_Latency" "MetricName": "Load_Miss_Real_Latency"
}, },
...@@ -745,43 +745,43 @@ ...@@ -745,43 +745,43 @@
}, },
{ {
"BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads", "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads",
"MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L1_MISS / INST_RETIRED.ANY", "MetricExpr": "1e3 * MEM_LOAD_UOPS_RETIRED.L1_MISS / INST_RETIRED.ANY",
"MetricGroup": "CacheMisses;Mem", "MetricGroup": "CacheMisses;Mem",
"MetricName": "L1MPKI" "MetricName": "L1MPKI"
}, },
{ {
"BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads", "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads",
"MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY", "MetricExpr": "1e3 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY",
"MetricGroup": "Backend;CacheMisses;Mem", "MetricGroup": "Backend;CacheMisses;Mem",
"MetricName": "L2MPKI" "MetricName": "L2MPKI"
}, },
{ {
"BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all request types (including speculative)", "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all request types (including speculative)",
"MetricExpr": "1000 * L2_RQSTS.MISS / INST_RETIRED.ANY", "MetricExpr": "1e3 * L2_RQSTS.MISS / INST_RETIRED.ANY",
"MetricGroup": "CacheMisses;Mem;Offcore", "MetricGroup": "CacheMisses;Mem;Offcore",
"MetricName": "L2MPKI_All" "MetricName": "L2MPKI_All"
}, },
{ {
"BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all demand loads (including speculative)", "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all demand loads (including speculative)",
"MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY", "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY",
"MetricGroup": "CacheMisses;Mem", "MetricGroup": "CacheMisses;Mem",
"MetricName": "L2MPKI_Load" "MetricName": "L2MPKI_Load"
}, },
{ {
"BriefDescription": "L2 cache hits per kilo instruction for all request types (including speculative)", "BriefDescription": "L2 cache hits per kilo instruction for all request types (including speculative)",
"MetricExpr": "1000 * (L2_RQSTS.REFERENCES - L2_RQSTS.MISS) / INST_RETIRED.ANY", "MetricExpr": "1e3 * (L2_RQSTS.REFERENCES - L2_RQSTS.MISS) / INST_RETIRED.ANY",
"MetricGroup": "CacheMisses;Mem", "MetricGroup": "CacheMisses;Mem",
"MetricName": "L2HPKI_All" "MetricName": "L2HPKI_All"
}, },
{ {
"BriefDescription": "L2 cache hits per kilo instruction for all demand loads (including speculative)", "BriefDescription": "L2 cache hits per kilo instruction for all demand loads (including speculative)",
"MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANY", "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANY",
"MetricGroup": "CacheMisses;Mem", "MetricGroup": "CacheMisses;Mem",
"MetricName": "L2HPKI_Load" "MetricName": "L2HPKI_Load"
}, },
{ {
"BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads", "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads",
"MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L3_MISS / INST_RETIRED.ANY", "MetricExpr": "1e3 * MEM_LOAD_UOPS_RETIRED.L3_MISS / INST_RETIRED.ANY",
"MetricGroup": "CacheMisses;Mem", "MetricGroup": "CacheMisses;Mem",
"MetricName": "L3MPKI" "MetricName": "L3MPKI"
}, },
...@@ -794,19 +794,19 @@ ...@@ -794,19 +794,19 @@
}, },
{ {
"BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]", "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",
"MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time", "MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / duration_time",
"MetricGroup": "Mem;MemoryBW", "MetricGroup": "Mem;MemoryBW",
"MetricName": "L1D_Cache_Fill_BW" "MetricName": "L1D_Cache_Fill_BW"
}, },
{ {
"BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]", "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]",
"MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time", "MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / duration_time",
"MetricGroup": "Mem;MemoryBW", "MetricGroup": "Mem;MemoryBW",
"MetricName": "L2_Cache_Fill_BW" "MetricName": "L2_Cache_Fill_BW"
}, },
{ {
"BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]", "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
"MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration_time", "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / duration_time",
"MetricGroup": "Mem;MemoryBW", "MetricGroup": "Mem;MemoryBW",
"MetricName": "L3_Cache_Fill_BW" "MetricName": "L3_Cache_Fill_BW"
}, },
...@@ -836,19 +836,19 @@ ...@@ -836,19 +836,19 @@
}, },
{ {
"BriefDescription": "Average CPU Utilization", "BriefDescription": "Average CPU Utilization",
"MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@", "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC",
"MetricGroup": "HPC;Summary", "MetricGroup": "HPC;Summary",
"MetricName": "CPU_Utilization" "MetricName": "CPU_Utilization"
}, },
{ {
"BriefDescription": "Measured Average Frequency for unhalted processors [GHz]", "BriefDescription": "Measured Average Frequency for unhalted processors [GHz]",
"MetricExpr": "Turbo_Utilization * msr@tsc@ / 1000000000 / duration_time", "MetricExpr": "Turbo_Utilization * TSC / 1e9 / duration_time",
"MetricGroup": "Power;Summary", "MetricGroup": "Power;Summary",
"MetricName": "Average_Frequency" "MetricName": "Average_Frequency"
}, },
{ {
"BriefDescription": "Giga Floating Point Operations Per Second", "BriefDescription": "Giga Floating Point Operations Per Second",
"MetricExpr": "((1 * (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / 1000000000) / duration_time", "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / 1e9 / duration_time",
"MetricGroup": "Cor;Flops;HPC", "MetricGroup": "Cor;Flops;HPC",
"MetricName": "GFLOPs", "MetricName": "GFLOPs",
"PublicDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width and AMX engine." "PublicDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width and AMX engine."
...@@ -861,7 +861,7 @@ ...@@ -861,7 +861,7 @@
}, },
{ {
"BriefDescription": "Fraction of cycles where both hardware Logical Processors were active", "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active",
"MetricExpr": "1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / (CPU_CLK_UNHALTED.REF_XCLK_ANY / 2) if #SMT_on else 0", "MetricExpr": "(1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / (CPU_CLK_UNHALTED.REF_XCLK_ANY / 2) if #SMT_on else 0)",
"MetricGroup": "SMT", "MetricGroup": "SMT",
"MetricName": "SMT_2T_Utilization" "MetricName": "SMT_2T_Utilization"
}, },
...@@ -879,68 +879,87 @@ ...@@ -879,68 +879,87 @@
}, },
{ {
"BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]", "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]",
"MetricExpr": "64 * (arb@event\\=0x81\\,umask\\=0x1@ + arb@event\\=0x84\\,umask\\=0x1@) / 1000000 / duration_time / 1000", "MetricExpr": "64 * (UNC_ARB_TRK_REQUESTS.ALL + UNC_ARB_COH_TRK_REQUESTS.ALL) / 1e6 / duration_time / 1e3",
"MetricGroup": "HPC;Mem;MemoryBW;SoC", "MetricGroup": "HPC;Mem;MemoryBW;SoC",
"MetricName": "DRAM_BW_Use" "MetricName": "DRAM_BW_Use"
}, },
{ {
"BriefDescription": "Average latency of all requests to external memory (in Uncore cycles)", "BriefDescription": "Average latency of all requests to external memory (in Uncore cycles)",
"MetricExpr": "UNC_ARB_TRK_OCCUPANCY.ALL / arb@event\\=0x81\\,umask\\=0x1@", "MetricExpr": "MEM_Parallel_Requests",
"MetricGroup": "Mem;SoC", "MetricGroup": "Mem;SoC",
"MetricName": "MEM_Request_Latency" "MetricName": "MEM_Request_Latency"
}, },
{ {
"BriefDescription": "Average number of parallel requests to external memory. Accounts for all requests", "BriefDescription": "Average number of parallel requests to external memory. Accounts for all requests",
"MetricExpr": "UNC_ARB_TRK_OCCUPANCY.ALL / arb@event\\=0x81\\,umask\\=0x1@", "MetricExpr": "UNC_ARB_TRK_OCCUPANCY.ALL / UNC_ARB_TRK_REQUESTS.ALL",
"MetricGroup": "Mem;SoC", "MetricGroup": "Mem;SoC",
"MetricName": "MEM_Parallel_Requests" "MetricName": "MEM_Parallel_Requests"
}, },
{
"BriefDescription": "Socket actual clocks when any core is active on that socket",
"MetricExpr": "UNC_CLOCK.SOCKET",
"MetricGroup": "SoC",
"MetricName": "Socket_CLKS"
},
{ {
"BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]", "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]",
"MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u", "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u",
"MetricGroup": "Branches;OS", "MetricGroup": "Branches;OS",
"MetricName": "IpFarBranch" "MetricName": "IpFarBranch"
}, },
{
"BriefDescription": "Uncore frequency per die [GHZ]",
"MetricExpr": "Socket_CLKS / #num_dies / duration_time / 1e9",
"MetricGroup": "SoC",
"MetricName": "UNCORE_FREQ"
},
{ {
"BriefDescription": "C3 residency percent per core", "BriefDescription": "C3 residency percent per core",
"MetricExpr": "(cstate_core@c3\\-residency@ / msr@tsc@) * 100", "MetricExpr": "cstate_core@c3\\-residency@ / TSC",
"MetricGroup": "Power", "MetricGroup": "Power",
"MetricName": "C3_Core_Residency" "MetricName": "C3_Core_Residency",
"ScaleUnit": "100%"
}, },
{ {
"BriefDescription": "C6 residency percent per core", "BriefDescription": "C6 residency percent per core",
"MetricExpr": "(cstate_core@c6\\-residency@ / msr@tsc@) * 100", "MetricExpr": "cstate_core@c6\\-residency@ / TSC",
"MetricGroup": "Power", "MetricGroup": "Power",
"MetricName": "C6_Core_Residency" "MetricName": "C6_Core_Residency",
"ScaleUnit": "100%"
}, },
{ {
"BriefDescription": "C7 residency percent per core", "BriefDescription": "C7 residency percent per core",
"MetricExpr": "(cstate_core@c7\\-residency@ / msr@tsc@) * 100", "MetricExpr": "cstate_core@c7\\-residency@ / TSC",
"MetricGroup": "Power", "MetricGroup": "Power",
"MetricName": "C7_Core_Residency" "MetricName": "C7_Core_Residency",
"ScaleUnit": "100%"
}, },
{ {
"BriefDescription": "C2 residency percent per package", "BriefDescription": "C2 residency percent per package",
"MetricExpr": "(cstate_pkg@c2\\-residency@ / msr@tsc@) * 100", "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC",
"MetricGroup": "Power", "MetricGroup": "Power",
"MetricName": "C2_Pkg_Residency" "MetricName": "C2_Pkg_Residency",
"ScaleUnit": "100%"
}, },
{ {
"BriefDescription": "C3 residency percent per package", "BriefDescription": "C3 residency percent per package",
"MetricExpr": "(cstate_pkg@c3\\-residency@ / msr@tsc@) * 100", "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC",
"MetricGroup": "Power", "MetricGroup": "Power",
"MetricName": "C3_Pkg_Residency" "MetricName": "C3_Pkg_Residency",
"ScaleUnit": "100%"
}, },
{ {
"BriefDescription": "C6 residency percent per package", "BriefDescription": "C6 residency percent per package",
"MetricExpr": "(cstate_pkg@c6\\-residency@ / msr@tsc@) * 100", "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC",
"MetricGroup": "Power", "MetricGroup": "Power",
"MetricName": "C6_Pkg_Residency" "MetricName": "C6_Pkg_Residency",
"ScaleUnit": "100%"
}, },
{ {
"BriefDescription": "C7 residency percent per package", "BriefDescription": "C7 residency percent per package",
"MetricExpr": "(cstate_pkg@c7\\-residency@ / msr@tsc@) * 100", "MetricExpr": "cstate_pkg@c7\\-residency@ / TSC",
"MetricGroup": "Power", "MetricGroup": "Power",
"MetricName": "C7_Pkg_Residency" "MetricName": "C7_Pkg_Residency",
"ScaleUnit": "100%"
} }
] ]
tools/perf/pmu-events/arch/x86/broadwell/cache.json
View file @ fec57a8e
This source diff could not be displayed because it is too large. You can view the blob instead.
tools/perf/pmu-events/arch/x86/broadwell/floating-point.json
View file @ fec57a8e
[ [
{ {
"BriefDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", "BriefDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xc7", "EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
...@@ -10,8 +8,6 @@ ...@@ -10,8 +8,6 @@
}, },
{ {
"BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 4 calculations per element.", "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 4 calculations per element.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xc7", "EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
...@@ -19,8 +15,6 @@ ...@@ -19,8 +15,6 @@
}, },
{ {
"BriefDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 4 calculations per element.", "BriefDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 4 calculations per element.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xc7", "EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
...@@ -28,8 +22,6 @@ ...@@ -28,8 +22,6 @@
}, },
{ {
"BriefDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 8 calculations per element.", "BriefDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 8 calculations per element.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xc7", "EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
...@@ -37,8 +29,6 @@ ...@@ -37,8 +29,6 @@
}, },
{ {
"BriefDescription": "Number of SSE/AVX computational double precision floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* scalar and packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", "BriefDescription": "Number of SSE/AVX computational double precision floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* scalar and packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xc7", "EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.DOUBLE", "EventName": "FP_ARITH_INST_RETIRED.DOUBLE",
"SampleAfterValue": "2000006", "SampleAfterValue": "2000006",
...@@ -46,8 +36,6 @@ ...@@ -46,8 +36,6 @@
}, },
{ {
"BriefDescription": "Number of SSE/AVX computational packed floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* packed double and single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", "BriefDescription": "Number of SSE/AVX computational packed floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* packed double and single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xc7", "EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.PACKED", "EventName": "FP_ARITH_INST_RETIRED.PACKED",
"SampleAfterValue": "2000004", "SampleAfterValue": "2000004",
...@@ -55,8 +43,6 @@ ...@@ -55,8 +43,6 @@
}, },
{ {
"BriefDescription": "Number of SSE/AVX computational scalar floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computation operation. Applies to SSE* and AVX* scalar double and single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", "BriefDescription": "Number of SSE/AVX computational scalar floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computation operation. Applies to SSE* and AVX* scalar double and single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xc7", "EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.SCALAR", "EventName": "FP_ARITH_INST_RETIRED.SCALAR",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
...@@ -64,8 +50,6 @@ ...@@ -64,8 +50,6 @@
}, },
{ {
"BriefDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", "BriefDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xc7", "EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
...@@ -73,8 +57,6 @@ ...@@ -73,8 +57,6 @@
}, },
{ {
"BriefDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", "BriefDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xc7", "EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
...@@ -82,8 +64,6 @@ ...@@ -82,8 +64,6 @@
}, },
{ {
"BriefDescription": "Number of SSE/AVX computational single precision floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* scalar and packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", "BriefDescription": "Number of SSE/AVX computational single precision floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* scalar and packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xc7", "EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.SINGLE", "EventName": "FP_ARITH_INST_RETIRED.SINGLE",
"SampleAfterValue": "2000005", "SampleAfterValue": "2000005",
...@@ -91,8 +71,6 @@ ...@@ -91,8 +71,6 @@
}, },
{ {
"BriefDescription": "Cycles with any input/output SSE or FP assist", "BriefDescription": "Cycles with any input/output SSE or FP assist",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"CounterMask": "1", "CounterMask": "1",
"EventCode": "0xCA", "EventCode": "0xCA",
"EventName": "FP_ASSIST.ANY", "EventName": "FP_ASSIST.ANY",
...@@ -102,8 +80,6 @@ ...@@ -102,8 +80,6 @@
}, },
{ {
"BriefDescription": "Number of SIMD FP assists due to input values", "BriefDescription": "Number of SIMD FP assists due to input values",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xCA", "EventCode": "0xCA",
"EventName": "FP_ASSIST.SIMD_INPUT", "EventName": "FP_ASSIST.SIMD_INPUT",
"PublicDescription": "This event counts any input SSE* FP assist - invalid operation, denormal operand, dividing by zero, SNaN operand. Counting includes only cases involving penalties that required micro-code assist intervention.", "PublicDescription": "This event counts any input SSE* FP assist - invalid operation, denormal operand, dividing by zero, SNaN operand. Counting includes only cases involving penalties that required micro-code assist intervention.",
...@@ -112,8 +88,6 @@ ...@@ -112,8 +88,6 @@
}, },
{ {
"BriefDescription": "Number of SIMD FP assists due to Output values", "BriefDescription": "Number of SIMD FP assists due to Output values",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xCA", "EventCode": "0xCA",
"EventName": "FP_ASSIST.SIMD_OUTPUT", "EventName": "FP_ASSIST.SIMD_OUTPUT",
"PublicDescription": "This event counts the number of SSE* floating point (FP) micro-code assist (numeric overflow/underflow) when the output value (destination register) is invalid. Counting covers only cases involving penalties that require micro-code assist intervention.", "PublicDescription": "This event counts the number of SSE* floating point (FP) micro-code assist (numeric overflow/underflow) when the output value (destination register) is invalid. Counting covers only cases involving penalties that require micro-code assist intervention.",
...@@ -122,8 +96,6 @@ ...@@ -122,8 +96,6 @@
}, },
{ {
"BriefDescription": "Number of X87 assists due to input value.", "BriefDescription": "Number of X87 assists due to input value.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xCA", "EventCode": "0xCA",
"EventName": "FP_ASSIST.X87_INPUT", "EventName": "FP_ASSIST.X87_INPUT",
"PublicDescription": "This event counts x87 floating point (FP) micro-code assist (invalid operation, denormal operand, SNaN operand) when the input value (one of the source operands to an FP instruction) is invalid.", "PublicDescription": "This event counts x87 floating point (FP) micro-code assist (invalid operation, denormal operand, SNaN operand) when the input value (one of the source operands to an FP instruction) is invalid.",
...@@ -132,8 +104,6 @@ ...@@ -132,8 +104,6 @@
}, },
{ {
"BriefDescription": "Number of X87 assists due to output value.", "BriefDescription": "Number of X87 assists due to output value.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xCA", "EventCode": "0xCA",
"EventName": "FP_ASSIST.X87_OUTPUT", "EventName": "FP_ASSIST.X87_OUTPUT",
"PublicDescription": "This event counts the number of x87 floating point (FP) micro-code assist (numeric overflow/underflow, inexact result) when the output value (destination register) is invalid.", "PublicDescription": "This event counts the number of x87 floating point (FP) micro-code assist (numeric overflow/underflow, inexact result) when the output value (destination register) is invalid.",
...@@ -142,8 +112,6 @@ ...@@ -142,8 +112,6 @@
}, },
{ {
"BriefDescription": "Number of SIMD Move Elimination candidate uops that were eliminated.", "BriefDescription": "Number of SIMD Move Elimination candidate uops that were eliminated.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x58", "EventCode": "0x58",
"EventName": "MOVE_ELIMINATION.SIMD_ELIMINATED", "EventName": "MOVE_ELIMINATION.SIMD_ELIMINATED",
"SampleAfterValue": "1000003", "SampleAfterValue": "1000003",
...@@ -151,8 +119,6 @@ ...@@ -151,8 +119,6 @@
}, },
{ {
"BriefDescription": "Number of SIMD Move Elimination candidate uops that were not eliminated.", "BriefDescription": "Number of SIMD Move Elimination candidate uops that were not eliminated.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x58", "EventCode": "0x58",
"EventName": "MOVE_ELIMINATION.SIMD_NOT_ELIMINATED", "EventName": "MOVE_ELIMINATION.SIMD_NOT_ELIMINATED",
"SampleAfterValue": "1000003", "SampleAfterValue": "1000003",
...@@ -160,8 +126,6 @@ ...@@ -160,8 +126,6 @@
}, },
{ {
"BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.", "BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM30", "Errata": "BDM30",
"EventCode": "0xC1", "EventCode": "0xC1",
"EventName": "OTHER_ASSISTS.AVX_TO_SSE", "EventName": "OTHER_ASSISTS.AVX_TO_SSE",
...@@ -171,8 +135,6 @@ ...@@ -171,8 +135,6 @@
}, },
{ {
"BriefDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.", "BriefDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM30", "Errata": "BDM30",
"EventCode": "0xC1", "EventCode": "0xC1",
"EventName": "OTHER_ASSISTS.SSE_TO_AVX", "EventName": "OTHER_ASSISTS.SSE_TO_AVX",
...@@ -182,8 +144,6 @@ ...@@ -182,8 +144,6 @@
}, },
{ {
"BriefDescription": "Micro-op dispatches cancelled due to insufficient SIMD physical register file read ports", "BriefDescription": "Micro-op dispatches cancelled due to insufficient SIMD physical register file read ports",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xA0", "EventCode": "0xA0",
"EventName": "UOP_DISPATCHES_CANCELLED.SIMD_PRF", "EventName": "UOP_DISPATCHES_CANCELLED.SIMD_PRF",
"PublicDescription": "This event counts the number of micro-operations cancelled after they were dispatched from the scheduler to the execution units when the total number of physical register read ports across all dispatch ports exceeds the read bandwidth of the physical register file. The SIMD_PRF subevent applies to the following instructions: VDPPS, DPPS, VPCMPESTRI, PCMPESTRI, VPCMPESTRM, PCMPESTRM, VFMADD*, VFMADDSUB*, VFMSUB*, VMSUBADD*, VFNMADD*, VFNMSUB*. See the Broadwell Optimization Guide for more information.", "PublicDescription": "This event counts the number of micro-operations cancelled after they were dispatched from the scheduler to the execution units when the total number of physical register read ports across all dispatch ports exceeds the read bandwidth of the physical register file. The SIMD_PRF subevent applies to the following instructions: VDPPS, DPPS, VPCMPESTRI, PCMPESTRI, VPCMPESTRM, PCMPESTRM, VFMADD*, VFMADDSUB*, VFMSUB*, VMSUBADD*, VFNMADD*, VFNMSUB*. See the Broadwell Optimization Guide for more information.",
......
tools/perf/pmu-events/arch/x86/broadwell/frontend.json
View file @ fec57a8e
[ [
{ {
"BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.", "BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xe6", "EventCode": "0xe6",
"EventName": "BACLEARS.ANY", "EventName": "BACLEARS.ANY",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
...@@ -10,8 +8,6 @@ ...@@ -10,8 +8,6 @@
}, },
{ {
"BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xAB", "EventCode": "0xAB",
"EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES", "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES",
"PublicDescription": "This event counts Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of the switch itself, for example, when Instruction Decode Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receiving the first MITE uop. \nMM is placed before Instruction Decode Queue (IDQ) to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths. Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode Stream Buffer (DSB)-to-MITE switch occurs.\nPenalty: A Decode Stream Buffer (DSB) hit followed by a Decode Stream Buffer (DSB) miss can cost up to six cycles in which no uops are delivered to the IDQ. Most often, such switches from the Decode Stream Buffer (DSB) to the legacy pipeline cost 02 cycles.", "PublicDescription": "This event counts Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of the switch itself, for example, when Instruction Decode Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receiving the first MITE uop. \nMM is placed before Instruction Decode Queue (IDQ) to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths. Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode Stream Buffer (DSB)-to-MITE switch occurs.\nPenalty: A Decode Stream Buffer (DSB) hit followed by a Decode Stream Buffer (DSB) miss can cost up to six cycles in which no uops are delivered to the IDQ. Most often, such switches from the Decode Stream Buffer (DSB) to the legacy pipeline cost 02 cycles.",
...@@ -20,8 +16,6 @@ ...@@ -20,8 +16,6 @@
}, },
{ {
"BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches", "BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x80", "EventCode": "0x80",
"EventName": "ICACHE.HIT", "EventName": "ICACHE.HIT",
"PublicDescription": "This event counts the number of both cacheable and noncacheable Instruction Cache, Streaming Buffer and Victim Cache Reads including UC fetches.", "PublicDescription": "This event counts the number of both cacheable and noncacheable Instruction Cache, Streaming Buffer and Victim Cache Reads including UC fetches.",
...@@ -30,8 +24,6 @@ ...@@ -30,8 +24,6 @@
}, },
{ {
"BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.", "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x80", "EventCode": "0x80",
"EventName": "ICACHE.IFDATA_STALL", "EventName": "ICACHE.IFDATA_STALL",
"PublicDescription": "This event counts cycles during which the demand fetch waits for data (wfdM104H) from L2 or iSB (opportunistic hit).", "PublicDescription": "This event counts cycles during which the demand fetch waits for data (wfdM104H) from L2 or iSB (opportunistic hit).",
...@@ -40,8 +32,6 @@ ...@@ -40,8 +32,6 @@
}, },
{ {
"BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes Uncacheable accesses.", "BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes Uncacheable accesses.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x80", "EventCode": "0x80",
"EventName": "ICACHE.MISSES", "EventName": "ICACHE.MISSES",
"PublicDescription": "This event counts the number of instruction cache, streaming buffer and victim cache misses. Counting includes UC accesses.", "PublicDescription": "This event counts the number of instruction cache, streaming buffer and victim cache misses. Counting includes UC accesses.",
...@@ -50,8 +40,6 @@ ...@@ -50,8 +40,6 @@
}, },
{ {
"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops", "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "4", "CounterMask": "4",
"EventCode": "0x79", "EventCode": "0x79",
"EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS", "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS",
...@@ -61,8 +49,6 @@ ...@@ -61,8 +49,6 @@
}, },
{ {
"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop", "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1", "CounterMask": "1",
"EventCode": "0x79", "EventCode": "0x79",
"EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS", "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS",
...@@ -72,8 +58,6 @@ ...@@ -72,8 +58,6 @@
}, },
{ {
"BriefDescription": "Cycles MITE is delivering 4 Uops", "BriefDescription": "Cycles MITE is delivering 4 Uops",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "4", "CounterMask": "4",
"EventCode": "0x79", "EventCode": "0x79",
"EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS", "EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS",
...@@ -83,8 +67,6 @@ ...@@ -83,8 +67,6 @@
}, },
{ {
"BriefDescription": "Cycles MITE is delivering any Uop", "BriefDescription": "Cycles MITE is delivering any Uop",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1", "CounterMask": "1",
"EventCode": "0x79", "EventCode": "0x79",
"EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS", "EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS",
...@@ -94,8 +76,6 @@ ...@@ -94,8 +76,6 @@
}, },
{ {
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path", "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1", "CounterMask": "1",
"EventCode": "0x79", "EventCode": "0x79",
"EventName": "IDQ.DSB_CYCLES", "EventName": "IDQ.DSB_CYCLES",
...@@ -105,8 +85,6 @@ ...@@ -105,8 +85,6 @@
}, },
{ {
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path", "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79", "EventCode": "0x79",
"EventName": "IDQ.DSB_UOPS", "EventName": "IDQ.DSB_UOPS",
"PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.", "PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.",
...@@ -115,8 +93,6 @@ ...@@ -115,8 +93,6 @@
}, },
{ {
"BriefDescription": "Instruction Decode Queue (IDQ) empty cycles", "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0x79", "EventCode": "0x79",
"EventName": "IDQ.EMPTY", "EventName": "IDQ.EMPTY",
"PublicDescription": "This counts the number of cycles that the instruction decoder queue is empty and can indicate that the application may be bound in the front end. It does not determine whether there are uops being delivered to the Alloc stage since uops can be delivered by bypass skipping the Instruction Decode Queue (IDQ) when it is empty.", "PublicDescription": "This counts the number of cycles that the instruction decoder queue is empty and can indicate that the application may be bound in the front end. It does not determine whether there are uops being delivered to the Alloc stage since uops can be delivered by bypass skipping the Instruction Decode Queue (IDQ) when it is empty.",
...@@ -125,8 +101,6 @@ ...@@ -125,8 +101,6 @@
}, },
{ {
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path", "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79", "EventCode": "0x79",
"EventName": "IDQ.MITE_ALL_UOPS", "EventName": "IDQ.MITE_ALL_UOPS",
"PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).", "PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
...@@ -135,8 +109,6 @@ ...@@ -135,8 +109,6 @@
}, },
{ {
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path", "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1", "CounterMask": "1",
"EventCode": "0x79", "EventCode": "0x79",
"EventName": "IDQ.MITE_CYCLES", "EventName": "IDQ.MITE_CYCLES",
...@@ -146,8 +118,6 @@ ...@@ -146,8 +118,6 @@
}, },
{ {
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path", "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79", "EventCode": "0x79",
"EventName": "IDQ.MITE_UOPS", "EventName": "IDQ.MITE_UOPS",
"PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).", "PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
...@@ -156,8 +126,6 @@ ...@@ -156,8 +126,6 @@
}, },
{ {
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1", "CounterMask": "1",
"EventCode": "0x79", "EventCode": "0x79",
"EventName": "IDQ.MS_CYCLES", "EventName": "IDQ.MS_CYCLES",
...@@ -167,8 +135,6 @@ ...@@ -167,8 +135,6 @@
}, },
{ {
"BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", "BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1", "CounterMask": "1",
"EventCode": "0x79", "EventCode": "0x79",
"EventName": "IDQ.MS_DSB_CYCLES", "EventName": "IDQ.MS_DSB_CYCLES",
...@@ -178,8 +144,6 @@ ...@@ -178,8 +144,6 @@
}, },
{ {
"BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy", "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1", "CounterMask": "1",
"EdgeDetect": "1", "EdgeDetect": "1",
"EventCode": "0x79", "EventCode": "0x79",
...@@ -190,8 +154,6 @@ ...@@ -190,8 +154,6 @@
}, },
{ {
"BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79", "EventCode": "0x79",
"EventName": "IDQ.MS_DSB_UOPS", "EventName": "IDQ.MS_DSB_UOPS",
"PublicDescription": "This event counts the number of uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ.", "PublicDescription": "This event counts the number of uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ.",
...@@ -200,8 +162,6 @@ ...@@ -200,8 +162,6 @@
}, },
{ {
"BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", "BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79", "EventCode": "0x79",
"EventName": "IDQ.MS_MITE_UOPS", "EventName": "IDQ.MS_MITE_UOPS",
"PublicDescription": "This event counts the number of uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ.", "PublicDescription": "This event counts the number of uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ.",
...@@ -210,8 +170,6 @@ ...@@ -210,8 +170,6 @@
}, },
{ {
"BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.", "BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1", "CounterMask": "1",
"EdgeDetect": "1", "EdgeDetect": "1",
"EventCode": "0x79", "EventCode": "0x79",
...@@ -221,8 +179,6 @@ ...@@ -221,8 +179,6 @@
}, },
{ {
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79", "EventCode": "0x79",
"EventName": "IDQ.MS_UOPS", "EventName": "IDQ.MS_UOPS",
"PublicDescription": "This event counts the total number of uops delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.", "PublicDescription": "This event counts the total number of uops delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.",
...@@ -231,8 +187,6 @@ ...@@ -231,8 +187,6 @@
}, },
{ {
"BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled", "BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0x9C", "EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CORE", "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE",
"PublicDescription": "This event counts the number of uops not delivered to Resource Allocation Table (RAT) per thread adding 4 x when Resource Allocation Table (RAT) is not stalled and Instruction Decode Queue (IDQ) delivers x uops to Resource Allocation Table (RAT) (where x belongs to {0,1,2,3}). Counting does not cover cases when:\n a. IDQ-Resource Allocation Table (RAT) pipe serves the other thread;\n b. Resource Allocation Table (RAT) is stalled for the thread (including uop drops and clear BE conditions); \n c. Instruction Decode Queue (IDQ) delivers four uops.", "PublicDescription": "This event counts the number of uops not delivered to Resource Allocation Table (RAT) per thread adding 4 x when Resource Allocation Table (RAT) is not stalled and Instruction Decode Queue (IDQ) delivers x uops to Resource Allocation Table (RAT) (where x belongs to {0,1,2,3}). Counting does not cover cases when:\n a. IDQ-Resource Allocation Table (RAT) pipe serves the other thread;\n b. Resource Allocation Table (RAT) is stalled for the thread (including uop drops and clear BE conditions); \n c. Instruction Decode Queue (IDQ) delivers four uops.",
...@@ -241,8 +195,6 @@ ...@@ -241,8 +195,6 @@
}, },
{ {
"BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled", "BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"CounterMask": "4", "CounterMask": "4",
"EventCode": "0x9C", "EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE",
...@@ -252,8 +204,6 @@ ...@@ -252,8 +204,6 @@
}, },
{ {
"BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.", "BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"CounterMask": "1", "CounterMask": "1",
"EventCode": "0x9C", "EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK", "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK",
...@@ -263,8 +213,6 @@ ...@@ -263,8 +213,6 @@
}, },
{ {
"BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled", "BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"CounterMask": "3", "CounterMask": "3",
"EventCode": "0x9C", "EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE", "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE",
...@@ -274,8 +222,6 @@ ...@@ -274,8 +222,6 @@
}, },
{ {
"BriefDescription": "Cycles with less than 2 uops delivered by the front end.", "BriefDescription": "Cycles with less than 2 uops delivered by the front end.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"CounterMask": "2", "CounterMask": "2",
"EventCode": "0x9C", "EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE", "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE",
...@@ -284,8 +230,6 @@ ...@@ -284,8 +230,6 @@
}, },
{ {
"BriefDescription": "Cycles with less than 3 uops delivered by the front end.", "BriefDescription": "Cycles with less than 3 uops delivered by the front end.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"CounterMask": "1", "CounterMask": "1",
"EventCode": "0x9C", "EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE", "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE",
......
tools/perf/pmu-events/arch/x86/broadwell/memory.json
View file @ fec57a8e
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tools/perf/pmu-events/arch/x86/broadwell/other.json
View file @ fec57a8e
[ [
{ {
"BriefDescription": "Unhalted core cycles when the thread is in ring 0", "BriefDescription": "Unhalted core cycles when the thread is in ring 0",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5C", "EventCode": "0x5C",
"EventName": "CPL_CYCLES.RING0", "EventName": "CPL_CYCLES.RING0",
"PublicDescription": "This event counts the unhalted core cycles during which the thread is in the ring 0 privileged mode.", "PublicDescription": "This event counts the unhalted core cycles during which the thread is in the ring 0 privileged mode.",
...@@ -11,8 +9,6 @@ ...@@ -11,8 +9,6 @@
}, },
{ {
"BriefDescription": "Number of intervals between processor halts while thread is in ring 0", "BriefDescription": "Number of intervals between processor halts while thread is in ring 0",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1", "CounterMask": "1",
"EdgeDetect": "1", "EdgeDetect": "1",
"EventCode": "0x5C", "EventCode": "0x5C",
...@@ -23,8 +19,6 @@ ...@@ -23,8 +19,6 @@
}, },
{ {
"BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3", "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5C", "EventCode": "0x5C",
"EventName": "CPL_CYCLES.RING123", "EventName": "CPL_CYCLES.RING123",
"PublicDescription": "This event counts unhalted core cycles during which the thread is in rings 1, 2, or 3.", "PublicDescription": "This event counts unhalted core cycles during which the thread is in rings 1, 2, or 3.",
...@@ -33,8 +27,6 @@ ...@@ -33,8 +27,6 @@
}, },
{ {
"BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock", "BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x63", "EventCode": "0x63",
"EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION",
"PublicDescription": "This event counts cycles in which the L1 and L2 are locked due to a UC lock or split lock. A lock is asserted in case of locked memory access, due to noncacheable memory, locked operation that spans two cache lines, or a page walk from the noncacheable page table. L1D and L2 locks have a very high performance penalty and it is highly recommended to avoid such access.", "PublicDescription": "This event counts cycles in which the L1 and L2 are locked due to a UC lock or split lock. A lock is asserted in case of locked memory access, due to noncacheable memory, locked operation that spans two cache lines, or a page walk from the noncacheable page table. L1D and L2 locks have a very high performance penalty and it is highly recommended to avoid such access.",
......
tools/perf/pmu-events/arch/x86/broadwell/pipeline.json
View file @ fec57a8e
[ [
{ {
"BriefDescription": "Cycles when divider is busy executing divide operations", "BriefDescription": "Cycles when divider is busy executing divide operations",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x14", "EventCode": "0x14",
"EventName": "ARITH.FPU_DIV_ACTIVE", "EventName": "ARITH.FPU_DIV_ACTIVE",
"PublicDescription": "This event counts the number of the divide operations executed. Uses edge-detect and a cmask value of 1 on ARITH.FPU_DIV_ACTIVE to get the number of the divide operations executed.", "PublicDescription": "This event counts the number of the divide operations executed. Uses edge-detect and a cmask value of 1 on ARITH.FPU_DIV_ACTIVE to get the number of the divide operations executed.",
...@@ -11,8 +9,6 @@ ...@@ -11,8 +9,6 @@
}, },
{ {
"BriefDescription": "Speculative and retired branches", "BriefDescription": "Speculative and retired branches",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88", "EventCode": "0x88",
"EventName": "BR_INST_EXEC.ALL_BRANCHES", "EventName": "BR_INST_EXEC.ALL_BRANCHES",
"PublicDescription": "This event counts both taken and not taken speculative and retired branch instructions.", "PublicDescription": "This event counts both taken and not taken speculative and retired branch instructions.",
...@@ -21,8 +17,6 @@ ...@@ -21,8 +17,6 @@
}, },
{ {
"BriefDescription": "Speculative and retired macro-conditional branches", "BriefDescription": "Speculative and retired macro-conditional branches",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88", "EventCode": "0x88",
"EventName": "BR_INST_EXEC.ALL_CONDITIONAL", "EventName": "BR_INST_EXEC.ALL_CONDITIONAL",
"PublicDescription": "This event counts both taken and not taken speculative and retired macro-conditional branch instructions.", "PublicDescription": "This event counts both taken and not taken speculative and retired macro-conditional branch instructions.",
...@@ -31,8 +25,6 @@ ...@@ -31,8 +25,6 @@
}, },
{ {
"BriefDescription": "Speculative and retired macro-unconditional branches excluding calls and indirects", "BriefDescription": "Speculative and retired macro-unconditional branches excluding calls and indirects",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88", "EventCode": "0x88",
"EventName": "BR_INST_EXEC.ALL_DIRECT_JMP", "EventName": "BR_INST_EXEC.ALL_DIRECT_JMP",
"PublicDescription": "This event counts both taken and not taken speculative and retired macro-unconditional branch instructions, excluding calls and indirects.", "PublicDescription": "This event counts both taken and not taken speculative and retired macro-unconditional branch instructions, excluding calls and indirects.",
...@@ -41,8 +33,6 @@ ...@@ -41,8 +33,6 @@
}, },
{ {
"BriefDescription": "Speculative and retired direct near calls", "BriefDescription": "Speculative and retired direct near calls",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88", "EventCode": "0x88",
"EventName": "BR_INST_EXEC.ALL_DIRECT_NEAR_CALL", "EventName": "BR_INST_EXEC.ALL_DIRECT_NEAR_CALL",
"PublicDescription": "This event counts both taken and not taken speculative and retired direct near calls.", "PublicDescription": "This event counts both taken and not taken speculative and retired direct near calls.",
...@@ -51,8 +41,6 @@ ...@@ -51,8 +41,6 @@
}, },
{ {
"BriefDescription": "Speculative and retired indirect branches excluding calls and returns", "BriefDescription": "Speculative and retired indirect branches excluding calls and returns",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88", "EventCode": "0x88",
"EventName": "BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", "EventName": "BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET",
"PublicDescription": "This event counts both taken and not taken speculative and retired indirect branches excluding calls and return branches.", "PublicDescription": "This event counts both taken and not taken speculative and retired indirect branches excluding calls and return branches.",
...@@ -61,8 +49,6 @@ ...@@ -61,8 +49,6 @@
}, },
{ {
"BriefDescription": "Speculative and retired indirect return branches.", "BriefDescription": "Speculative and retired indirect return branches.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88", "EventCode": "0x88",
"EventName": "BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN", "EventName": "BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN",
"PublicDescription": "This event counts both taken and not taken speculative and retired indirect branches that have a return mnemonic.", "PublicDescription": "This event counts both taken and not taken speculative and retired indirect branches that have a return mnemonic.",
...@@ -71,8 +57,6 @@ ...@@ -71,8 +57,6 @@
}, },
{ {
"BriefDescription": "Not taken macro-conditional branches", "BriefDescription": "Not taken macro-conditional branches",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88", "EventCode": "0x88",
"EventName": "BR_INST_EXEC.NONTAKEN_CONDITIONAL", "EventName": "BR_INST_EXEC.NONTAKEN_CONDITIONAL",
"PublicDescription": "This event counts not taken macro-conditional branch instructions.", "PublicDescription": "This event counts not taken macro-conditional branch instructions.",
...@@ -81,8 +65,6 @@ ...@@ -81,8 +65,6 @@
}, },
{ {
"BriefDescription": "Taken speculative and retired macro-conditional branches", "BriefDescription": "Taken speculative and retired macro-conditional branches",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88", "EventCode": "0x88",
"EventName": "BR_INST_EXEC.TAKEN_CONDITIONAL", "EventName": "BR_INST_EXEC.TAKEN_CONDITIONAL",
"PublicDescription": "This event counts taken speculative and retired macro-conditional branch instructions.", "PublicDescription": "This event counts taken speculative and retired macro-conditional branch instructions.",
...@@ -91,8 +73,6 @@ ...@@ -91,8 +73,6 @@
}, },
{ {
"BriefDescription": "Taken speculative and retired macro-conditional branch instructions excluding calls and indirects", "BriefDescription": "Taken speculative and retired macro-conditional branch instructions excluding calls and indirects",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88", "EventCode": "0x88",
"EventName": "BR_INST_EXEC.TAKEN_DIRECT_JUMP", "EventName": "BR_INST_EXEC.TAKEN_DIRECT_JUMP",
"PublicDescription": "This event counts taken speculative and retired macro-conditional branch instructions excluding calls and indirect branches.", "PublicDescription": "This event counts taken speculative and retired macro-conditional branch instructions excluding calls and indirect branches.",
...@@ -101,8 +81,6 @@ ...@@ -101,8 +81,6 @@
}, },
{ {
"BriefDescription": "Taken speculative and retired direct near calls", "BriefDescription": "Taken speculative and retired direct near calls",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88", "EventCode": "0x88",
"EventName": "BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL", "EventName": "BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL",
"PublicDescription": "This event counts taken speculative and retired direct near calls.", "PublicDescription": "This event counts taken speculative and retired direct near calls.",
...@@ -111,8 +89,6 @@ ...@@ -111,8 +89,6 @@
}, },
{ {
"BriefDescription": "Taken speculative and retired indirect branches excluding calls and returns", "BriefDescription": "Taken speculative and retired indirect branches excluding calls and returns",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88", "EventCode": "0x88",
"EventName": "BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET",
"PublicDescription": "This event counts taken speculative and retired indirect branches excluding calls and return branches.", "PublicDescription": "This event counts taken speculative and retired indirect branches excluding calls and return branches.",
...@@ -121,8 +97,6 @@ ...@@ -121,8 +97,6 @@
}, },
{ {
"BriefDescription": "Taken speculative and retired indirect calls", "BriefDescription": "Taken speculative and retired indirect calls",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88", "EventCode": "0x88",
"EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL", "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL",
"PublicDescription": "This event counts taken speculative and retired indirect calls including both register and memory indirect.", "PublicDescription": "This event counts taken speculative and retired indirect calls including both register and memory indirect.",
...@@ -131,8 +105,6 @@ ...@@ -131,8 +105,6 @@
}, },
{ {
"BriefDescription": "Taken speculative and retired indirect branches with return mnemonic", "BriefDescription": "Taken speculative and retired indirect branches with return mnemonic",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88", "EventCode": "0x88",
"EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN", "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN",
"PublicDescription": "This event counts taken speculative and retired indirect branches that have a return mnemonic.", "PublicDescription": "This event counts taken speculative and retired indirect branches that have a return mnemonic.",
...@@ -141,8 +113,6 @@ ...@@ -141,8 +113,6 @@
}, },
{ {
"BriefDescription": "All (macro) branch instructions retired.", "BriefDescription": "All (macro) branch instructions retired.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC4", "EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.ALL_BRANCHES", "EventName": "BR_INST_RETIRED.ALL_BRANCHES",
"PublicDescription": "This event counts all (macro) branch instructions retired.", "PublicDescription": "This event counts all (macro) branch instructions retired.",
...@@ -150,8 +120,6 @@ ...@@ -150,8 +120,6 @@
}, },
{ {
"BriefDescription": "All (macro) branch instructions retired. (Precise Event - PEBS)", "BriefDescription": "All (macro) branch instructions retired. (Precise Event - PEBS)",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"Errata": "BDW98", "Errata": "BDW98",
"EventCode": "0xC4", "EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS", "EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS",
...@@ -162,8 +130,6 @@ ...@@ -162,8 +130,6 @@
}, },
{ {
"BriefDescription": "Conditional branch instructions retired.", "BriefDescription": "Conditional branch instructions retired.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC4", "EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.CONDITIONAL", "EventName": "BR_INST_RETIRED.CONDITIONAL",
"PEBS": "1", "PEBS": "1",
...@@ -173,8 +139,6 @@ ...@@ -173,8 +139,6 @@
}, },
{ {
"BriefDescription": "Far branch instructions retired.", "BriefDescription": "Far branch instructions retired.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDW98", "Errata": "BDW98",
"EventCode": "0xC4", "EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.FAR_BRANCH", "EventName": "BR_INST_RETIRED.FAR_BRANCH",
...@@ -184,8 +148,6 @@ ...@@ -184,8 +148,6 @@
}, },
{ {
"BriefDescription": "Direct and indirect near call instructions retired.", "BriefDescription": "Direct and indirect near call instructions retired.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC4", "EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.NEAR_CALL", "EventName": "BR_INST_RETIRED.NEAR_CALL",
"PEBS": "1", "PEBS": "1",
...@@ -195,8 +157,6 @@ ...@@ -195,8 +157,6 @@
}, },
{ {
"BriefDescription": "Direct and indirect macro near call instructions retired (captured in ring 3).", "BriefDescription": "Direct and indirect macro near call instructions retired (captured in ring 3).",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC4", "EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.NEAR_CALL_R3", "EventName": "BR_INST_RETIRED.NEAR_CALL_R3",
"PEBS": "1", "PEBS": "1",
...@@ -206,8 +166,6 @@ ...@@ -206,8 +166,6 @@
}, },
{ {
"BriefDescription": "Return instructions retired.", "BriefDescription": "Return instructions retired.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC4", "EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.NEAR_RETURN", "EventName": "BR_INST_RETIRED.NEAR_RETURN",
"PEBS": "1", "PEBS": "1",
...@@ -217,8 +175,6 @@ ...@@ -217,8 +175,6 @@
}, },
{ {
"BriefDescription": "Taken branch instructions retired.", "BriefDescription": "Taken branch instructions retired.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC4", "EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.NEAR_TAKEN", "EventName": "BR_INST_RETIRED.NEAR_TAKEN",
"PEBS": "1", "PEBS": "1",
...@@ -228,8 +184,6 @@ ...@@ -228,8 +184,6 @@
}, },
{ {
"BriefDescription": "Not taken branch instructions retired.", "BriefDescription": "Not taken branch instructions retired.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC4", "EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.NOT_TAKEN", "EventName": "BR_INST_RETIRED.NOT_TAKEN",
"PublicDescription": "This event counts not taken branch instructions retired.", "PublicDescription": "This event counts not taken branch instructions retired.",
...@@ -238,8 +192,6 @@ ...@@ -238,8 +192,6 @@
}, },
{ {
"BriefDescription": "Speculative and retired mispredicted macro conditional branches", "BriefDescription": "Speculative and retired mispredicted macro conditional branches",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89", "EventCode": "0x89",
"EventName": "BR_MISP_EXEC.ALL_BRANCHES", "EventName": "BR_MISP_EXEC.ALL_BRANCHES",
"PublicDescription": "This event counts both taken and not taken speculative and retired mispredicted branch instructions.", "PublicDescription": "This event counts both taken and not taken speculative and retired mispredicted branch instructions.",
...@@ -248,8 +200,6 @@ ...@@ -248,8 +200,6 @@
}, },
{ {
"BriefDescription": "Speculative and retired mispredicted macro conditional branches", "BriefDescription": "Speculative and retired mispredicted macro conditional branches",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89", "EventCode": "0x89",
"EventName": "BR_MISP_EXEC.ALL_CONDITIONAL", "EventName": "BR_MISP_EXEC.ALL_CONDITIONAL",
"PublicDescription": "This event counts both taken and not taken speculative and retired mispredicted macro conditional branch instructions.", "PublicDescription": "This event counts both taken and not taken speculative and retired mispredicted macro conditional branch instructions.",
...@@ -258,8 +208,6 @@ ...@@ -258,8 +208,6 @@
}, },
{ {
"BriefDescription": "Mispredicted indirect branches excluding calls and returns", "BriefDescription": "Mispredicted indirect branches excluding calls and returns",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89", "EventCode": "0x89",
"EventName": "BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", "EventName": "BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET",
"PublicDescription": "This event counts both taken and not taken mispredicted indirect branches excluding calls and returns.", "PublicDescription": "This event counts both taken and not taken mispredicted indirect branches excluding calls and returns.",
...@@ -268,8 +216,6 @@ ...@@ -268,8 +216,6 @@
}, },
{ {
"BriefDescription": "Not taken speculative and retired mispredicted macro conditional branches", "BriefDescription": "Not taken speculative and retired mispredicted macro conditional branches",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89", "EventCode": "0x89",
"EventName": "BR_MISP_EXEC.NONTAKEN_CONDITIONAL", "EventName": "BR_MISP_EXEC.NONTAKEN_CONDITIONAL",
"PublicDescription": "This event counts not taken speculative and retired mispredicted macro conditional branch instructions.", "PublicDescription": "This event counts not taken speculative and retired mispredicted macro conditional branch instructions.",
...@@ -278,8 +224,6 @@ ...@@ -278,8 +224,6 @@
}, },
{ {
"BriefDescription": "Taken speculative and retired mispredicted macro conditional branches", "BriefDescription": "Taken speculative and retired mispredicted macro conditional branches",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89", "EventCode": "0x89",
"EventName": "BR_MISP_EXEC.TAKEN_CONDITIONAL", "EventName": "BR_MISP_EXEC.TAKEN_CONDITIONAL",
"PublicDescription": "This event counts taken speculative and retired mispredicted macro conditional branch instructions.", "PublicDescription": "This event counts taken speculative and retired mispredicted macro conditional branch instructions.",
...@@ -288,8 +232,6 @@ ...@@ -288,8 +232,6 @@
}, },
{ {
"BriefDescription": "Taken speculative and retired mispredicted indirect branches excluding calls and returns", "BriefDescription": "Taken speculative and retired mispredicted indirect branches excluding calls and returns",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89", "EventCode": "0x89",
"EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET",
"PublicDescription": "This event counts taken speculative and retired mispredicted indirect branches excluding calls and returns.", "PublicDescription": "This event counts taken speculative and retired mispredicted indirect branches excluding calls and returns.",
...@@ -298,8 +240,6 @@ ...@@ -298,8 +240,6 @@
}, },
{ {
"BriefDescription": "Taken speculative and retired mispredicted indirect calls.", "BriefDescription": "Taken speculative and retired mispredicted indirect calls.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89", "EventCode": "0x89",
"EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL", "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL",
"SampleAfterValue": "200003", "SampleAfterValue": "200003",
...@@ -307,8 +247,6 @@ ...@@ -307,8 +247,6 @@
}, },
{ {
"BriefDescription": "Taken speculative and retired mispredicted indirect branches with return mnemonic", "BriefDescription": "Taken speculative and retired mispredicted indirect branches with return mnemonic",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89", "EventCode": "0x89",
"EventName": "BR_MISP_EXEC.TAKEN_RETURN_NEAR", "EventName": "BR_MISP_EXEC.TAKEN_RETURN_NEAR",
"PublicDescription": "This event counts taken speculative and retired mispredicted indirect branches that have a return mnemonic.", "PublicDescription": "This event counts taken speculative and retired mispredicted indirect branches that have a return mnemonic.",
...@@ -317,8 +255,6 @@ ...@@ -317,8 +255,6 @@
}, },
{ {
"BriefDescription": "All mispredicted macro branch instructions retired.", "BriefDescription": "All mispredicted macro branch instructions retired.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC5", "EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.ALL_BRANCHES", "EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
"PublicDescription": "This event counts all mispredicted macro branch instructions retired.", "PublicDescription": "This event counts all mispredicted macro branch instructions retired.",
...@@ -326,8 +262,6 @@ ...@@ -326,8 +262,6 @@
}, },
{ {
"BriefDescription": "Mispredicted macro branch instructions retired. (Precise Event - PEBS)", "BriefDescription": "Mispredicted macro branch instructions retired. (Precise Event - PEBS)",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xC5", "EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS", "EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS",
"PEBS": "2", "PEBS": "2",
...@@ -337,8 +271,6 @@ ...@@ -337,8 +271,6 @@
}, },
{ {
"BriefDescription": "Mispredicted conditional branch instructions retired.", "BriefDescription": "Mispredicted conditional branch instructions retired.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC5", "EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.CONDITIONAL", "EventName": "BR_MISP_RETIRED.CONDITIONAL",
"PEBS": "1", "PEBS": "1",
...@@ -348,8 +280,6 @@ ...@@ -348,8 +280,6 @@
}, },
{ {
"BriefDescription": "number of near branch instructions retired that were mispredicted and taken.", "BriefDescription": "number of near branch instructions retired that were mispredicted and taken.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC5", "EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.NEAR_TAKEN", "EventName": "BR_MISP_RETIRED.NEAR_TAKEN",
"PEBS": "1", "PEBS": "1",
...@@ -359,8 +289,6 @@ ...@@ -359,8 +289,6 @@
}, },
{ {
"BriefDescription": "This event counts the number of mispredicted ret instructions retired. Non PEBS", "BriefDescription": "This event counts the number of mispredicted ret instructions retired. Non PEBS",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC5", "EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.RET", "EventName": "BR_MISP_RETIRED.RET",
"PEBS": "1", "PEBS": "1",
...@@ -370,8 +298,6 @@ ...@@ -370,8 +298,6 @@
}, },
{ {
"BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.", "BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0x3c", "EventCode": "0x3c",
"EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE", "EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
...@@ -379,8 +305,6 @@ ...@@ -379,8 +305,6 @@
}, },
{ {
"BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)", "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C", "EventCode": "0x3C",
"EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK", "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK",
"PublicDescription": "This is a fixed-frequency event programmed to general counters. It counts when the core is unhalted at 100 Mhz.", "PublicDescription": "This is a fixed-frequency event programmed to general counters. It counts when the core is unhalted at 100 Mhz.",
...@@ -390,8 +314,6 @@ ...@@ -390,8 +314,6 @@
{ {
"AnyThread": "1", "AnyThread": "1",
"BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).", "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C", "EventCode": "0x3C",
"EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY", "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
...@@ -399,8 +321,6 @@ ...@@ -399,8 +321,6 @@
}, },
{ {
"BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.", "BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C", "EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
...@@ -408,8 +328,6 @@ ...@@ -408,8 +328,6 @@
}, },
{ {
"BriefDescription": "Reference cycles when the core is not in halt state.", "BriefDescription": "Reference cycles when the core is not in halt state.",
"Counter": "Fixed counter 2",
"CounterHTOff": "Fixed counter 2",
"EventName": "CPU_CLK_UNHALTED.REF_TSC", "EventName": "CPU_CLK_UNHALTED.REF_TSC",
"PublicDescription": "This event counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. \nNote: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. This event is clocked by base clock (100 Mhz) on Sandy Bridge. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case.", "PublicDescription": "This event counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. \nNote: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. This event is clocked by base clock (100 Mhz) on Sandy Bridge. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case.",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
...@@ -417,8 +335,6 @@ ...@@ -417,8 +335,6 @@
}, },
{ {
"BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)", "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C", "EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.REF_XCLK", "EventName": "CPU_CLK_UNHALTED.REF_XCLK",
"PublicDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate).", "PublicDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate).",
...@@ -428,8 +344,6 @@ ...@@ -428,8 +344,6 @@
{ {
"AnyThread": "1", "AnyThread": "1",
"BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).", "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C", "EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY", "EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
...@@ -437,8 +351,6 @@ ...@@ -437,8 +351,6 @@
}, },
{ {
"BriefDescription": "Core cycles when the thread is not in halt state", "BriefDescription": "Core cycles when the thread is not in halt state",
"Counter": "Fixed counter 1",
"CounterHTOff": "Fixed counter 1",
"EventName": "CPU_CLK_UNHALTED.THREAD", "EventName": "CPU_CLK_UNHALTED.THREAD",
"PublicDescription": "This event counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events.", "PublicDescription": "This event counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events.",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
...@@ -447,16 +359,12 @@ ...@@ -447,16 +359,12 @@
{ {
"AnyThread": "1", "AnyThread": "1",
"BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.", "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.",
"Counter": "Fixed counter 1",
"CounterHTOff": "Fixed counter 1",
"EventName": "CPU_CLK_UNHALTED.THREAD_ANY", "EventName": "CPU_CLK_UNHALTED.THREAD_ANY",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"UMask": "0x2" "UMask": "0x2"
}, },
{ {
"BriefDescription": "Thread cycles when thread is not in halt state", "BriefDescription": "Thread cycles when thread is not in halt state",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C", "EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.THREAD_P", "EventName": "CPU_CLK_UNHALTED.THREAD_P",
"PublicDescription": "This is an architectural event that counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. For this reason, this event may have a changing ratio with regards to wall clock time.", "PublicDescription": "This is an architectural event that counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. For this reason, this event may have a changing ratio with regards to wall clock time.",
...@@ -465,16 +373,12 @@ ...@@ -465,16 +373,12 @@
{ {
"AnyThread": "1", "AnyThread": "1",
"BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.", "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C", "EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY", "EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY",
"SampleAfterValue": "2000003" "SampleAfterValue": "2000003"
}, },
{ {
"BriefDescription": "Cycles while L1 cache miss demand load is outstanding.", "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.",
"Counter": "2",
"CounterHTOff": "2",
"CounterMask": "8", "CounterMask": "8",
"EventCode": "0xA3", "EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS", "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS",
...@@ -483,8 +387,6 @@ ...@@ -483,8 +387,6 @@
}, },
{ {
"BriefDescription": "Cycles while L1 cache miss demand load is outstanding.", "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.",
"Counter": "2",
"CounterHTOff": "2",
"CounterMask": "8", "CounterMask": "8",
"EventCode": "0xA3", "EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.CYCLES_L1D_PENDING", "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_PENDING",
...@@ -494,8 +396,6 @@ ...@@ -494,8 +396,6 @@
}, },
{ {
"BriefDescription": "Cycles while L2 cache miss demand load is outstanding.", "BriefDescription": "Cycles while L2 cache miss demand load is outstanding.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1", "CounterMask": "1",
"EventCode": "0xA3", "EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS", "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS",
...@@ -504,8 +404,6 @@ ...@@ -504,8 +404,6 @@
}, },
{ {
"BriefDescription": "Cycles while L2 cache miss demand load is outstanding.", "BriefDescription": "Cycles while L2 cache miss demand load is outstanding.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1", "CounterMask": "1",
"EventCode": "0xA3", "EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.CYCLES_L2_PENDING", "EventName": "CYCLE_ACTIVITY.CYCLES_L2_PENDING",
...@@ -515,8 +413,6 @@ ...@@ -515,8 +413,6 @@
}, },
{ {
"BriefDescription": "Cycles while memory subsystem has an outstanding load.", "BriefDescription": "Cycles while memory subsystem has an outstanding load.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "2", "CounterMask": "2",
"EventCode": "0xA3", "EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.CYCLES_LDM_PENDING", "EventName": "CYCLE_ACTIVITY.CYCLES_LDM_PENDING",
...@@ -526,8 +422,6 @@ ...@@ -526,8 +422,6 @@
}, },
{ {
"BriefDescription": "Cycles while memory subsystem has an outstanding load.", "BriefDescription": "Cycles while memory subsystem has an outstanding load.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"CounterMask": "2", "CounterMask": "2",
"EventCode": "0xA3", "EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", "EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY",
...@@ -536,8 +430,6 @@ ...@@ -536,8 +430,6 @@
}, },
{ {
"BriefDescription": "This event increments by 1 for every cycle where there was no execute for this thread.", "BriefDescription": "This event increments by 1 for every cycle where there was no execute for this thread.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"CounterMask": "4", "CounterMask": "4",
"EventCode": "0xA3", "EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.CYCLES_NO_EXECUTE", "EventName": "CYCLE_ACTIVITY.CYCLES_NO_EXECUTE",
...@@ -547,8 +439,6 @@ ...@@ -547,8 +439,6 @@
}, },
{ {
"BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.", "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.",
"Counter": "2",
"CounterHTOff": "2",
"CounterMask": "12", "CounterMask": "12",
"EventCode": "0xA3", "EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS", "EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS",
...@@ -557,8 +447,6 @@ ...@@ -557,8 +447,6 @@
}, },
{ {
"BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.", "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.",
"Counter": "2",
"CounterHTOff": "2",
"CounterMask": "12", "CounterMask": "12",
"EventCode": "0xA3", "EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.STALLS_L1D_PENDING", "EventName": "CYCLE_ACTIVITY.STALLS_L1D_PENDING",
...@@ -568,8 +456,6 @@ ...@@ -568,8 +456,6 @@
}, },
{ {
"BriefDescription": "Execution stalls while L2 cache miss demand load is outstanding.", "BriefDescription": "Execution stalls while L2 cache miss demand load is outstanding.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "5", "CounterMask": "5",
"EventCode": "0xA3", "EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS", "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS",
...@@ -578,8 +464,6 @@ ...@@ -578,8 +464,6 @@
}, },
{ {
"BriefDescription": "Execution stalls while L2 cache miss demand load is outstanding.", "BriefDescription": "Execution stalls while L2 cache miss demand load is outstanding.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"CounterMask": "5", "CounterMask": "5",
"EventCode": "0xA3", "EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.STALLS_L2_PENDING", "EventName": "CYCLE_ACTIVITY.STALLS_L2_PENDING",
...@@ -589,8 +473,6 @@ ...@@ -589,8 +473,6 @@
}, },
{ {
"BriefDescription": "Execution stalls while memory subsystem has an outstanding load.", "BriefDescription": "Execution stalls while memory subsystem has an outstanding load.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"CounterMask": "6", "CounterMask": "6",
"EventCode": "0xA3", "EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.STALLS_LDM_PENDING", "EventName": "CYCLE_ACTIVITY.STALLS_LDM_PENDING",
...@@ -600,8 +482,6 @@ ...@@ -600,8 +482,6 @@
}, },
{ {
"BriefDescription": "Execution stalls while memory subsystem has an outstanding load.", "BriefDescription": "Execution stalls while memory subsystem has an outstanding load.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "6", "CounterMask": "6",
"EventCode": "0xA3", "EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY", "EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY",
...@@ -610,8 +490,6 @@ ...@@ -610,8 +490,6 @@
}, },
{ {
"BriefDescription": "Total execution stalls.", "BriefDescription": "Total execution stalls.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "4", "CounterMask": "4",
"EventCode": "0xA3", "EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.STALLS_TOTAL", "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL",
...@@ -620,8 +498,6 @@ ...@@ -620,8 +498,6 @@
}, },
{ {
"BriefDescription": "Stalls caused by changing prefix length of the instruction.", "BriefDescription": "Stalls caused by changing prefix length of the instruction.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x87", "EventCode": "0x87",
"EventName": "ILD_STALL.LCP", "EventName": "ILD_STALL.LCP",
"PublicDescription": "This event counts stalls occured due to changing prefix length (66, 67 or REX.W when they change the length of the decoded instruction). Occurrences counting is proportional to the number of prefixes in a 16B-line. This may result in the following penalties: three-cycle penalty for each LCP in a 16-byte chunk.", "PublicDescription": "This event counts stalls occured due to changing prefix length (66, 67 or REX.W when they change the length of the decoded instruction). Occurrences counting is proportional to the number of prefixes in a 16B-line. This may result in the following penalties: three-cycle penalty for each LCP in a 16-byte chunk.",
...@@ -630,8 +506,6 @@ ...@@ -630,8 +506,6 @@
}, },
{ {
"BriefDescription": "Instructions retired from execution.", "BriefDescription": "Instructions retired from execution.",
"Counter": "Fixed counter 0",
"CounterHTOff": "Fixed counter 0",
"EventName": "INST_RETIRED.ANY", "EventName": "INST_RETIRED.ANY",
"PublicDescription": "This event counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers. \nNotes: INST_RETIRED.ANY is counted by a designated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. INST_RETIRED.ANY_P is counted by a programmable counter and it is an architectural performance event. \nCounting: Faulting executions of GETSEC/VM entry/VM Exit/MWait will not count as retired instructions.", "PublicDescription": "This event counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers. \nNotes: INST_RETIRED.ANY is counted by a designated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. INST_RETIRED.ANY_P is counted by a programmable counter and it is an architectural performance event. \nCounting: Faulting executions of GETSEC/VM entry/VM Exit/MWait will not count as retired instructions.",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
...@@ -639,8 +513,6 @@ ...@@ -639,8 +513,6 @@
}, },
{ {
"BriefDescription": "Number of instructions retired. General Counter - architectural event", "BriefDescription": "Number of instructions retired. General Counter - architectural event",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM61", "Errata": "BDM61",
"EventCode": "0xC0", "EventCode": "0xC0",
"EventName": "INST_RETIRED.ANY_P", "EventName": "INST_RETIRED.ANY_P",
...@@ -649,8 +521,6 @@ ...@@ -649,8 +521,6 @@
}, },
{ {
"BriefDescription": "Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution", "BriefDescription": "Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution",
"Counter": "1",
"CounterHTOff": "1",
"Errata": "BDM11, BDM55", "Errata": "BDM11, BDM55",
"EventCode": "0xC0", "EventCode": "0xC0",
"EventName": "INST_RETIRED.PREC_DIST", "EventName": "INST_RETIRED.PREC_DIST",
...@@ -661,8 +531,6 @@ ...@@ -661,8 +531,6 @@
}, },
{ {
"BriefDescription": "FP operations retired. X87 FP operations that have no exceptions:", "BriefDescription": "FP operations retired. X87 FP operations that have no exceptions:",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC0", "EventCode": "0xC0",
"EventName": "INST_RETIRED.X87", "EventName": "INST_RETIRED.X87",
"PublicDescription": "This event counts FP operations retired. For X87 FP operations that have no exceptions counting also includes flows that have several X87, or flows that use X87 uops in the exception handling.", "PublicDescription": "This event counts FP operations retired. For X87 FP operations that have no exceptions counting also includes flows that have several X87, or flows that use X87 uops in the exception handling.",
...@@ -671,8 +539,6 @@ ...@@ -671,8 +539,6 @@
}, },
{ {
"BriefDescription": "Cycles when Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the thread", "BriefDescription": "Cycles when Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the thread",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x0D", "EventCode": "0x0D",
"EventName": "INT_MISC.RAT_STALL_CYCLES", "EventName": "INT_MISC.RAT_STALL_CYCLES",
"PublicDescription": "This event counts the number of cycles during which Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the current thread. This also includes the cycles during which the Allocator is serving another thread.", "PublicDescription": "This event counts the number of cycles during which Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the current thread. This also includes the cycles during which the Allocator is serving another thread.",
...@@ -681,8 +547,6 @@ ...@@ -681,8 +547,6 @@
}, },
{ {
"BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for this thread (e.g. misprediction or memory nuke)", "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for this thread (e.g. misprediction or memory nuke)",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1", "CounterMask": "1",
"EventCode": "0x0D", "EventCode": "0x0D",
"EventName": "INT_MISC.RECOVERY_CYCLES", "EventName": "INT_MISC.RECOVERY_CYCLES",
...@@ -693,8 +557,6 @@ ...@@ -693,8 +557,6 @@
{ {
"AnyThread": "1", "AnyThread": "1",
"BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke).", "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke).",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1", "CounterMask": "1",
"EventCode": "0x0D", "EventCode": "0x0D",
"EventName": "INT_MISC.RECOVERY_CYCLES_ANY", "EventName": "INT_MISC.RECOVERY_CYCLES_ANY",
...@@ -703,8 +565,6 @@ ...@@ -703,8 +565,6 @@
}, },
{ {
"BriefDescription": "This event counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.", "BriefDescription": "This event counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x03", "EventCode": "0x03",
"EventName": "LD_BLOCKS.NO_SR", "EventName": "LD_BLOCKS.NO_SR",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
...@@ -712,8 +572,6 @@ ...@@ -712,8 +572,6 @@
}, },
{ {
"BriefDescription": "Cases when loads get true Block-on-Store blocking code preventing store forwarding", "BriefDescription": "Cases when loads get true Block-on-Store blocking code preventing store forwarding",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x03", "EventCode": "0x03",
"EventName": "LD_BLOCKS.STORE_FORWARD", "EventName": "LD_BLOCKS.STORE_FORWARD",
"PublicDescription": "This event counts how many times the load operation got the true Block-on-Store blocking code preventing store forwarding. This includes cases when:\n - preceding store conflicts with the load (incomplete overlap);\n - store forwarding is impossible due to u-arch limitations;\n - preceding lock RMW operations are not forwarded;\n - store has the no-forward bit set (uncacheable/page-split/masked stores);\n - all-blocking stores are used (mostly, fences and port I/O);\nand others.\nThe most common case is a load blocked due to its address range overlapping with a preceding smaller uncompleted store. Note: This event does not take into account cases of out-of-SW-control (for example, SbTailHit), unknown physical STA, and cases of blocking loads on store due to being non-WB memory type or a lock. These cases are covered by other events.\nSee the table of not supported store forwards in the Optimization Guide.", "PublicDescription": "This event counts how many times the load operation got the true Block-on-Store blocking code preventing store forwarding. This includes cases when:\n - preceding store conflicts with the load (incomplete overlap);\n - store forwarding is impossible due to u-arch limitations;\n - preceding lock RMW operations are not forwarded;\n - store has the no-forward bit set (uncacheable/page-split/masked stores);\n - all-blocking stores are used (mostly, fences and port I/O);\nand others.\nThe most common case is a load blocked due to its address range overlapping with a preceding smaller uncompleted store. Note: This event does not take into account cases of out-of-SW-control (for example, SbTailHit), unknown physical STA, and cases of blocking loads on store due to being non-WB memory type or a lock. These cases are covered by other events.\nSee the table of not supported store forwards in the Optimization Guide.",
...@@ -722,8 +580,6 @@ ...@@ -722,8 +580,6 @@
}, },
{ {
"BriefDescription": "False dependencies in MOB due to partial compare", "BriefDescription": "False dependencies in MOB due to partial compare",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x07", "EventCode": "0x07",
"EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS",
"PublicDescription": "This event counts false dependencies in MOB when the partial comparison upon loose net check and dependency was resolved by the Enhanced Loose net mechanism. This may not result in high performance penalties. Loose net checks can fail when loads and stores are 4k aliased.", "PublicDescription": "This event counts false dependencies in MOB when the partial comparison upon loose net check and dependency was resolved by the Enhanced Loose net mechanism. This may not result in high performance penalties. Loose net checks can fail when loads and stores are 4k aliased.",
...@@ -732,8 +588,6 @@ ...@@ -732,8 +588,6 @@
}, },
{ {
"BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for hardware prefetch", "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for hardware prefetch",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x4C", "EventCode": "0x4C",
"EventName": "LOAD_HIT_PRE.HW_PF", "EventName": "LOAD_HIT_PRE.HW_PF",
"PublicDescription": "This event counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the hardware prefetch.", "PublicDescription": "This event counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the hardware prefetch.",
...@@ -742,8 +596,6 @@ ...@@ -742,8 +596,6 @@
}, },
{ {
"BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for software prefetch", "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for software prefetch",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x4c", "EventCode": "0x4c",
"EventName": "LOAD_HIT_PRE.SW_PF", "EventName": "LOAD_HIT_PRE.SW_PF",
"PublicDescription": "This event counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by asm inspection of the nearby instructions.", "PublicDescription": "This event counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by asm inspection of the nearby instructions.",
...@@ -752,8 +604,6 @@ ...@@ -752,8 +604,6 @@
}, },
{ {
"BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder.", "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "4", "CounterMask": "4",
"EventCode": "0xA8", "EventCode": "0xA8",
"EventName": "LSD.CYCLES_4_UOPS", "EventName": "LSD.CYCLES_4_UOPS",
...@@ -762,8 +612,6 @@ ...@@ -762,8 +612,6 @@
}, },
{ {
"BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.", "BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1", "CounterMask": "1",
"EventCode": "0xA8", "EventCode": "0xA8",
"EventName": "LSD.CYCLES_ACTIVE", "EventName": "LSD.CYCLES_ACTIVE",
...@@ -772,8 +620,6 @@ ...@@ -772,8 +620,6 @@
}, },
{ {
"BriefDescription": "Number of Uops delivered by the LSD.", "BriefDescription": "Number of Uops delivered by the LSD.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA8", "EventCode": "0xA8",
"EventName": "LSD.UOPS", "EventName": "LSD.UOPS",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
...@@ -781,8 +627,6 @@ ...@@ -781,8 +627,6 @@
}, },
{ {
"BriefDescription": "Number of machine clears (nukes) of any type.", "BriefDescription": "Number of machine clears (nukes) of any type.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1", "CounterMask": "1",
"EdgeDetect": "1", "EdgeDetect": "1",
"EventCode": "0xC3", "EventCode": "0xC3",
...@@ -792,8 +636,6 @@ ...@@ -792,8 +636,6 @@
}, },
{ {
"BriefDescription": "Cycles there was a Nuke. Account for both thread-specific and All Thread Nukes.", "BriefDescription": "Cycles there was a Nuke. Account for both thread-specific and All Thread Nukes.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC3", "EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.CYCLES", "EventName": "MACHINE_CLEARS.CYCLES",
"PublicDescription": "This event counts both thread-specific (TS) and all-thread (AT) nukes.", "PublicDescription": "This event counts both thread-specific (TS) and all-thread (AT) nukes.",
...@@ -802,8 +644,6 @@ ...@@ -802,8 +644,6 @@
}, },
{ {
"BriefDescription": "This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0.", "BriefDescription": "This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC3", "EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.MASKMOV", "EventName": "MACHINE_CLEARS.MASKMOV",
"PublicDescription": "Maskmov false fault - counts number of time ucode passes through Maskmov flow due to instruction's mask being 0 while the flow was completed without raising a fault.", "PublicDescription": "Maskmov false fault - counts number of time ucode passes through Maskmov flow due to instruction's mask being 0 while the flow was completed without raising a fault.",
...@@ -812,8 +652,6 @@ ...@@ -812,8 +652,6 @@
}, },
{ {
"BriefDescription": "Self-modifying code (SMC) detected.", "BriefDescription": "Self-modifying code (SMC) detected.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC3", "EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.SMC", "EventName": "MACHINE_CLEARS.SMC",
"PublicDescription": "This event counts self-modifying code (SMC) detected, which causes a machine clear.", "PublicDescription": "This event counts self-modifying code (SMC) detected, which causes a machine clear.",
...@@ -822,8 +660,6 @@ ...@@ -822,8 +660,6 @@
}, },
{ {
"BriefDescription": "Number of integer Move Elimination candidate uops that were eliminated.", "BriefDescription": "Number of integer Move Elimination candidate uops that were eliminated.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x58", "EventCode": "0x58",
"EventName": "MOVE_ELIMINATION.INT_ELIMINATED", "EventName": "MOVE_ELIMINATION.INT_ELIMINATED",
"SampleAfterValue": "1000003", "SampleAfterValue": "1000003",
...@@ -831,8 +667,6 @@ ...@@ -831,8 +667,6 @@
}, },
{ {
"BriefDescription": "Number of integer Move Elimination candidate uops that were not eliminated.", "BriefDescription": "Number of integer Move Elimination candidate uops that were not eliminated.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x58", "EventCode": "0x58",
"EventName": "MOVE_ELIMINATION.INT_NOT_ELIMINATED", "EventName": "MOVE_ELIMINATION.INT_NOT_ELIMINATED",
"SampleAfterValue": "1000003", "SampleAfterValue": "1000003",
...@@ -840,8 +674,6 @@ ...@@ -840,8 +674,6 @@
}, },
{ {
"BriefDescription": "Number of times any microcode assist is invoked by HW upon uop writeback.", "BriefDescription": "Number of times any microcode assist is invoked by HW upon uop writeback.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC1", "EventCode": "0xC1",
"EventName": "OTHER_ASSISTS.ANY_WB_ASSIST", "EventName": "OTHER_ASSISTS.ANY_WB_ASSIST",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
...@@ -849,8 +681,6 @@ ...@@ -849,8 +681,6 @@
}, },
{ {
"BriefDescription": "Resource-related stall cycles", "BriefDescription": "Resource-related stall cycles",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xa2", "EventCode": "0xa2",
"EventName": "RESOURCE_STALLS.ANY", "EventName": "RESOURCE_STALLS.ANY",
"PublicDescription": "This event counts resource-related stall cycles.", "PublicDescription": "This event counts resource-related stall cycles.",
...@@ -859,8 +689,6 @@ ...@@ -859,8 +689,6 @@
}, },
{ {
"BriefDescription": "Cycles stalled due to re-order buffer full.", "BriefDescription": "Cycles stalled due to re-order buffer full.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA2", "EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.ROB", "EventName": "RESOURCE_STALLS.ROB",
"PublicDescription": "This event counts ROB full stall cycles. This counts cycles that the pipeline backend blocked uop delivery from the front end.", "PublicDescription": "This event counts ROB full stall cycles. This counts cycles that the pipeline backend blocked uop delivery from the front end.",
...@@ -869,8 +697,6 @@ ...@@ -869,8 +697,6 @@
}, },
{ {
"BriefDescription": "Cycles stalled due to no eligible RS entry available.", "BriefDescription": "Cycles stalled due to no eligible RS entry available.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA2", "EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.RS", "EventName": "RESOURCE_STALLS.RS",
"PublicDescription": "This event counts stall cycles caused by absence of eligible entries in the reservation station (RS). This may result from RS overflow, or from RS deallocation because of the RS array Write Port allocation scheme (each RS entry has two write ports instead of four. As a result, empty entries could not be used, although RS is not really full). This counts cycles that the pipeline backend blocked uop delivery from the front end.", "PublicDescription": "This event counts stall cycles caused by absence of eligible entries in the reservation station (RS). This may result from RS overflow, or from RS deallocation because of the RS array Write Port allocation scheme (each RS entry has two write ports instead of four. As a result, empty entries could not be used, although RS is not really full). This counts cycles that the pipeline backend blocked uop delivery from the front end.",
...@@ -879,8 +705,6 @@ ...@@ -879,8 +705,6 @@
}, },
{ {
"BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).", "BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA2", "EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.SB", "EventName": "RESOURCE_STALLS.SB",
"PublicDescription": "This event counts stall cycles caused by the store buffer (SB) overflow (excluding draining from synch). This counts cycles that the pipeline backend blocked uop delivery from the front end.", "PublicDescription": "This event counts stall cycles caused by the store buffer (SB) overflow (excluding draining from synch). This counts cycles that the pipeline backend blocked uop delivery from the front end.",
...@@ -889,8 +713,6 @@ ...@@ -889,8 +713,6 @@
}, },
{ {
"BriefDescription": "Count cases of saving new LBR", "BriefDescription": "Count cases of saving new LBR",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xCC", "EventCode": "0xCC",
"EventName": "ROB_MISC_EVENTS.LBR_INSERTS", "EventName": "ROB_MISC_EVENTS.LBR_INSERTS",
"PublicDescription": "This event counts cases of saving new LBR records by hardware. This assumes proper enabling of LBRs and takes into account LBR filtering done by the LBR_SELECT register.", "PublicDescription": "This event counts cases of saving new LBR records by hardware. This assumes proper enabling of LBRs and takes into account LBR filtering done by the LBR_SELECT register.",
...@@ -899,8 +721,6 @@ ...@@ -899,8 +721,6 @@
}, },
{ {
"BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread", "BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5E", "EventCode": "0x5E",
"EventName": "RS_EVENTS.EMPTY_CYCLES", "EventName": "RS_EVENTS.EMPTY_CYCLES",
"PublicDescription": "This event counts cycles during which the reservation station (RS) is empty for the thread.\nNote: In ST-mode, not active thread should drive 0. This is usually caused by severely costly branch mispredictions, or allocator/FE issues.", "PublicDescription": "This event counts cycles during which the reservation station (RS) is empty for the thread.\nNote: In ST-mode, not active thread should drive 0. This is usually caused by severely costly branch mispredictions, or allocator/FE issues.",
...@@ -909,8 +729,6 @@ ...@@ -909,8 +729,6 @@
}, },
{ {
"BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.", "BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1", "CounterMask": "1",
"EdgeDetect": "1", "EdgeDetect": "1",
"EventCode": "0x5E", "EventCode": "0x5E",
...@@ -921,8 +739,6 @@ ...@@ -921,8 +739,6 @@
}, },
{ {
"BriefDescription": "Cycles per thread when uops are executed in port 0", "BriefDescription": "Cycles per thread when uops are executed in port 0",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1", "EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_0", "EventName": "UOPS_DISPATCHED_PORT.PORT_0",
"PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 0.", "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 0.",
...@@ -931,8 +747,6 @@ ...@@ -931,8 +747,6 @@
}, },
{ {
"BriefDescription": "Cycles per thread when uops are executed in port 1", "BriefDescription": "Cycles per thread when uops are executed in port 1",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1", "EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_1", "EventName": "UOPS_DISPATCHED_PORT.PORT_1",
"PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 1.", "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 1.",
...@@ -941,8 +755,6 @@ ...@@ -941,8 +755,6 @@
}, },
{ {
"BriefDescription": "Cycles per thread when uops are executed in port 2", "BriefDescription": "Cycles per thread when uops are executed in port 2",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1", "EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_2", "EventName": "UOPS_DISPATCHED_PORT.PORT_2",
"PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 2.", "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 2.",
...@@ -951,8 +763,6 @@ ...@@ -951,8 +763,6 @@
}, },
{ {
"BriefDescription": "Cycles per thread when uops are executed in port 3", "BriefDescription": "Cycles per thread when uops are executed in port 3",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1", "EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_3", "EventName": "UOPS_DISPATCHED_PORT.PORT_3",
"PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 3.", "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 3.",
...@@ -961,8 +771,6 @@ ...@@ -961,8 +771,6 @@
}, },
{ {
"BriefDescription": "Cycles per thread when uops are executed in port 4", "BriefDescription": "Cycles per thread when uops are executed in port 4",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1", "EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_4", "EventName": "UOPS_DISPATCHED_PORT.PORT_4",
"PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 4.", "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 4.",
...@@ -971,8 +779,6 @@ ...@@ -971,8 +779,6 @@
}, },
{ {
"BriefDescription": "Cycles per thread when uops are executed in port 5", "BriefDescription": "Cycles per thread when uops are executed in port 5",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1", "EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_5", "EventName": "UOPS_DISPATCHED_PORT.PORT_5",
"PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 5.", "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 5.",
...@@ -981,8 +787,6 @@ ...@@ -981,8 +787,6 @@
}, },
{ {
"BriefDescription": "Cycles per thread when uops are executed in port 6", "BriefDescription": "Cycles per thread when uops are executed in port 6",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1", "EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_6", "EventName": "UOPS_DISPATCHED_PORT.PORT_6",
"PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 6.", "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 6.",
...@@ -991,8 +795,6 @@ ...@@ -991,8 +795,6 @@
}, },
{ {
"BriefDescription": "Cycles per thread when uops are executed in port 7", "BriefDescription": "Cycles per thread when uops are executed in port 7",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1", "EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_7", "EventName": "UOPS_DISPATCHED_PORT.PORT_7",
"PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 7.", "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 7.",
...@@ -1001,8 +803,6 @@ ...@@ -1001,8 +803,6 @@
}, },
{ {
"BriefDescription": "Number of uops executed on the core.", "BriefDescription": "Number of uops executed on the core.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB1", "EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE", "EventName": "UOPS_EXECUTED.CORE",
"PublicDescription": "Number of uops executed from any thread.", "PublicDescription": "Number of uops executed from any thread.",
...@@ -1011,8 +811,6 @@ ...@@ -1011,8 +811,6 @@
}, },
{ {
"BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.", "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1", "CounterMask": "1",
"EventCode": "0xb1", "EventCode": "0xb1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1", "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1",
...@@ -1021,8 +819,6 @@ ...@@ -1021,8 +819,6 @@
}, },
{ {
"BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.", "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "2", "CounterMask": "2",
"EventCode": "0xb1", "EventCode": "0xb1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2", "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2",
...@@ -1031,8 +827,6 @@ ...@@ -1031,8 +827,6 @@
}, },
{ {
"BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.", "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "3", "CounterMask": "3",
"EventCode": "0xb1", "EventCode": "0xb1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3", "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3",
...@@ -1041,8 +835,6 @@ ...@@ -1041,8 +835,6 @@
}, },
{ {
"BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.", "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "4", "CounterMask": "4",
"EventCode": "0xb1", "EventCode": "0xb1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4", "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4",
...@@ -1051,8 +843,6 @@ ...@@ -1051,8 +843,6 @@
}, },
{ {
"BriefDescription": "Cycles with no micro-ops executed from any thread on physical core.", "BriefDescription": "Cycles with no micro-ops executed from any thread on physical core.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xb1", "EventCode": "0xb1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE", "EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE",
"Invert": "1", "Invert": "1",
...@@ -1061,8 +851,6 @@ ...@@ -1061,8 +851,6 @@
}, },
{ {
"BriefDescription": "Cycles where at least 1 uop was executed per-thread.", "BriefDescription": "Cycles where at least 1 uop was executed per-thread.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"CounterMask": "1", "CounterMask": "1",
"EventCode": "0xB1", "EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC", "EventName": "UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC",
...@@ -1071,8 +859,6 @@ ...@@ -1071,8 +859,6 @@
}, },
{ {
"BriefDescription": "Cycles where at least 2 uops were executed per-thread.", "BriefDescription": "Cycles where at least 2 uops were executed per-thread.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"CounterMask": "2", "CounterMask": "2",
"EventCode": "0xB1", "EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC", "EventName": "UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC",
...@@ -1081,8 +867,6 @@ ...@@ -1081,8 +867,6 @@
}, },
{ {
"BriefDescription": "Cycles where at least 3 uops were executed per-thread.", "BriefDescription": "Cycles where at least 3 uops were executed per-thread.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"CounterMask": "3", "CounterMask": "3",
"EventCode": "0xB1", "EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC", "EventName": "UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC",
...@@ -1091,8 +875,6 @@ ...@@ -1091,8 +875,6 @@
}, },
{ {
"BriefDescription": "Cycles where at least 4 uops were executed per-thread.", "BriefDescription": "Cycles where at least 4 uops were executed per-thread.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"CounterMask": "4", "CounterMask": "4",
"EventCode": "0xB1", "EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC", "EventName": "UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC",
...@@ -1101,8 +883,6 @@ ...@@ -1101,8 +883,6 @@
}, },
{ {
"BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.", "BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"CounterMask": "1", "CounterMask": "1",
"EventCode": "0xB1", "EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.STALL_CYCLES", "EventName": "UOPS_EXECUTED.STALL_CYCLES",
...@@ -1113,8 +893,6 @@ ...@@ -1113,8 +893,6 @@
}, },
{ {
"BriefDescription": "Counts the number of uops to be executed per-thread each cycle.", "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB1", "EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.THREAD", "EventName": "UOPS_EXECUTED.THREAD",
"PublicDescription": "Number of uops to be executed per-thread each cycle.", "PublicDescription": "Number of uops to be executed per-thread each cycle.",
...@@ -1123,8 +901,6 @@ ...@@ -1123,8 +901,6 @@
}, },
{ {
"BriefDescription": "Cycles per thread when uops are executed in port 0", "BriefDescription": "Cycles per thread when uops are executed in port 0",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1", "EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_0", "EventName": "UOPS_EXECUTED_PORT.PORT_0",
"PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 0.", "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 0.",
...@@ -1134,8 +910,6 @@ ...@@ -1134,8 +910,6 @@
{ {
"AnyThread": "1", "AnyThread": "1",
"BriefDescription": "Cycles per core when uops are exectuted in port 0.", "BriefDescription": "Cycles per core when uops are exectuted in port 0.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1", "EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_0_CORE", "EventName": "UOPS_EXECUTED_PORT.PORT_0_CORE",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
...@@ -1143,8 +917,6 @@ ...@@ -1143,8 +917,6 @@
}, },
{ {
"BriefDescription": "Cycles per thread when uops are executed in port 1", "BriefDescription": "Cycles per thread when uops are executed in port 1",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1", "EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_1", "EventName": "UOPS_EXECUTED_PORT.PORT_1",
"PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 1.", "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 1.",
...@@ -1154,8 +926,6 @@ ...@@ -1154,8 +926,6 @@
{ {
"AnyThread": "1", "AnyThread": "1",
"BriefDescription": "Cycles per core when uops are exectuted in port 1.", "BriefDescription": "Cycles per core when uops are exectuted in port 1.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1", "EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_1_CORE", "EventName": "UOPS_EXECUTED_PORT.PORT_1_CORE",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
...@@ -1163,8 +933,6 @@ ...@@ -1163,8 +933,6 @@
}, },
{ {
"BriefDescription": "Cycles per thread when uops are executed in port 2", "BriefDescription": "Cycles per thread when uops are executed in port 2",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1", "EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_2", "EventName": "UOPS_EXECUTED_PORT.PORT_2",
"PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 2.", "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 2.",
...@@ -1174,8 +942,6 @@ ...@@ -1174,8 +942,6 @@
{ {
"AnyThread": "1", "AnyThread": "1",
"BriefDescription": "Cycles per core when uops are dispatched to port 2.", "BriefDescription": "Cycles per core when uops are dispatched to port 2.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1", "EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_2_CORE", "EventName": "UOPS_EXECUTED_PORT.PORT_2_CORE",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
...@@ -1183,8 +949,6 @@ ...@@ -1183,8 +949,6 @@
}, },
{ {
"BriefDescription": "Cycles per thread when uops are executed in port 3", "BriefDescription": "Cycles per thread when uops are executed in port 3",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1", "EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_3", "EventName": "UOPS_EXECUTED_PORT.PORT_3",
"PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 3.", "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 3.",
...@@ -1194,8 +958,6 @@ ...@@ -1194,8 +958,6 @@
{ {
"AnyThread": "1", "AnyThread": "1",
"BriefDescription": "Cycles per core when uops are dispatched to port 3.", "BriefDescription": "Cycles per core when uops are dispatched to port 3.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1", "EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_3_CORE", "EventName": "UOPS_EXECUTED_PORT.PORT_3_CORE",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
...@@ -1203,8 +965,6 @@ ...@@ -1203,8 +965,6 @@
}, },
{ {
"BriefDescription": "Cycles per thread when uops are executed in port 4", "BriefDescription": "Cycles per thread when uops are executed in port 4",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1", "EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_4", "EventName": "UOPS_EXECUTED_PORT.PORT_4",
"PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 4.", "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 4.",
...@@ -1214,8 +974,6 @@ ...@@ -1214,8 +974,6 @@
{ {
"AnyThread": "1", "AnyThread": "1",
"BriefDescription": "Cycles per core when uops are exectuted in port 4.", "BriefDescription": "Cycles per core when uops are exectuted in port 4.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1", "EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_4_CORE", "EventName": "UOPS_EXECUTED_PORT.PORT_4_CORE",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
...@@ -1223,8 +981,6 @@ ...@@ -1223,8 +981,6 @@
}, },
{ {
"BriefDescription": "Cycles per thread when uops are executed in port 5", "BriefDescription": "Cycles per thread when uops are executed in port 5",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1", "EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_5", "EventName": "UOPS_EXECUTED_PORT.PORT_5",
"PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 5.", "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 5.",
...@@ -1234,8 +990,6 @@ ...@@ -1234,8 +990,6 @@
{ {
"AnyThread": "1", "AnyThread": "1",
"BriefDescription": "Cycles per core when uops are exectuted in port 5.", "BriefDescription": "Cycles per core when uops are exectuted in port 5.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1", "EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_5_CORE", "EventName": "UOPS_EXECUTED_PORT.PORT_5_CORE",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
...@@ -1243,8 +997,6 @@ ...@@ -1243,8 +997,6 @@
}, },
{ {
"BriefDescription": "Cycles per thread when uops are executed in port 6", "BriefDescription": "Cycles per thread when uops are executed in port 6",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1", "EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_6", "EventName": "UOPS_EXECUTED_PORT.PORT_6",
"PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 6.", "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 6.",
...@@ -1254,8 +1006,6 @@ ...@@ -1254,8 +1006,6 @@
{ {
"AnyThread": "1", "AnyThread": "1",
"BriefDescription": "Cycles per core when uops are exectuted in port 6.", "BriefDescription": "Cycles per core when uops are exectuted in port 6.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1", "EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_6_CORE", "EventName": "UOPS_EXECUTED_PORT.PORT_6_CORE",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
...@@ -1263,8 +1013,6 @@ ...@@ -1263,8 +1013,6 @@
}, },
{ {
"BriefDescription": "Cycles per thread when uops are executed in port 7", "BriefDescription": "Cycles per thread when uops are executed in port 7",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1", "EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_7", "EventName": "UOPS_EXECUTED_PORT.PORT_7",
"PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 7.", "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 7.",
...@@ -1274,8 +1022,6 @@ ...@@ -1274,8 +1022,6 @@
{ {
"AnyThread": "1", "AnyThread": "1",
"BriefDescription": "Cycles per core when uops are dispatched to port 7.", "BriefDescription": "Cycles per core when uops are dispatched to port 7.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1", "EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_7_CORE", "EventName": "UOPS_EXECUTED_PORT.PORT_7_CORE",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
...@@ -1283,8 +1029,6 @@ ...@@ -1283,8 +1029,6 @@
}, },
{ {
"BriefDescription": "Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS)", "BriefDescription": "Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS)",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x0E", "EventCode": "0x0E",
"EventName": "UOPS_ISSUED.ANY", "EventName": "UOPS_ISSUED.ANY",
"PublicDescription": "This event counts the number of Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS).", "PublicDescription": "This event counts the number of Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS).",
...@@ -1293,8 +1037,6 @@ ...@@ -1293,8 +1037,6 @@
}, },
{ {
"BriefDescription": "Number of flags-merge uops being allocated. Such uops considered perf sensitive; added by GSR u-arch.", "BriefDescription": "Number of flags-merge uops being allocated. Such uops considered perf sensitive; added by GSR u-arch.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x0E", "EventCode": "0x0E",
"EventName": "UOPS_ISSUED.FLAGS_MERGE", "EventName": "UOPS_ISSUED.FLAGS_MERGE",
"PublicDescription": "Number of flags-merge uops being allocated. Such uops considered perf sensitive\n added by GSR u-arch.", "PublicDescription": "Number of flags-merge uops being allocated. Such uops considered perf sensitive\n added by GSR u-arch.",
...@@ -1303,8 +1045,6 @@ ...@@ -1303,8 +1045,6 @@
}, },
{ {
"BriefDescription": "Number of Multiply packed/scalar single precision uops allocated.", "BriefDescription": "Number of Multiply packed/scalar single precision uops allocated.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x0E", "EventCode": "0x0E",
"EventName": "UOPS_ISSUED.SINGLE_MUL", "EventName": "UOPS_ISSUED.SINGLE_MUL",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
...@@ -1312,8 +1052,6 @@ ...@@ -1312,8 +1052,6 @@
}, },
{ {
"BriefDescription": "Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.", "BriefDescription": "Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x0E", "EventCode": "0x0E",
"EventName": "UOPS_ISSUED.SLOW_LEA", "EventName": "UOPS_ISSUED.SLOW_LEA",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
...@@ -1321,8 +1059,6 @@ ...@@ -1321,8 +1059,6 @@
}, },
{ {
"BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread", "BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"CounterMask": "1", "CounterMask": "1",
"EventCode": "0x0E", "EventCode": "0x0E",
"EventName": "UOPS_ISSUED.STALL_CYCLES", "EventName": "UOPS_ISSUED.STALL_CYCLES",
...@@ -1333,8 +1069,6 @@ ...@@ -1333,8 +1069,6 @@
}, },
{ {
"BriefDescription": "Actually retired uops.", "BriefDescription": "Actually retired uops.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC2", "EventCode": "0xC2",
"EventName": "UOPS_RETIRED.ALL", "EventName": "UOPS_RETIRED.ALL",
"PEBS": "1", "PEBS": "1",
...@@ -1344,8 +1078,6 @@ ...@@ -1344,8 +1078,6 @@
}, },
{ {
"BriefDescription": "Retirement slots used.", "BriefDescription": "Retirement slots used.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC2", "EventCode": "0xC2",
"EventName": "UOPS_RETIRED.RETIRE_SLOTS", "EventName": "UOPS_RETIRED.RETIRE_SLOTS",
"PEBS": "1", "PEBS": "1",
...@@ -1355,8 +1087,6 @@ ...@@ -1355,8 +1087,6 @@
}, },
{ {
"BriefDescription": "Cycles without actually retired uops.", "BriefDescription": "Cycles without actually retired uops.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"CounterMask": "1", "CounterMask": "1",
"EventCode": "0xC2", "EventCode": "0xC2",
"EventName": "UOPS_RETIRED.STALL_CYCLES", "EventName": "UOPS_RETIRED.STALL_CYCLES",
...@@ -1367,8 +1097,6 @@ ...@@ -1367,8 +1097,6 @@
}, },
{ {
"BriefDescription": "Cycles with less than 10 actually retired uops.", "BriefDescription": "Cycles with less than 10 actually retired uops.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"CounterMask": "10", "CounterMask": "10",
"EventCode": "0xC2", "EventCode": "0xC2",
"EventName": "UOPS_RETIRED.TOTAL_CYCLES", "EventName": "UOPS_RETIRED.TOTAL_CYCLES",
......
tools/perf/pmu-events/arch/x86/broadwell/uncore-cache.json
View file @ fec57a8e
[ [
{ {
"BriefDescription": "L3 Lookup any request that access cache and found line in E or S-state", "BriefDescription": "L3 Lookup any request that access cache and found line in E or S-state",
"Counter": "0,1",
"EventCode": "0x34", "EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.ANY_ES", "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_ES",
"PerPkg": "1", "PerPkg": "1",
...@@ -11,7 +10,6 @@ ...@@ -11,7 +10,6 @@
}, },
{ {
"BriefDescription": "L3 Lookup any request that access cache and found line in I-state", "BriefDescription": "L3 Lookup any request that access cache and found line in I-state",
"Counter": "0,1",
"EventCode": "0x34", "EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.ANY_I", "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_I",
"PerPkg": "1", "PerPkg": "1",
...@@ -21,7 +19,6 @@ ...@@ -21,7 +19,6 @@
}, },
{ {
"BriefDescription": "L3 Lookup any request that access cache and found line in M-state", "BriefDescription": "L3 Lookup any request that access cache and found line in M-state",
"Counter": "0,1",
"EventCode": "0x34", "EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.ANY_M", "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_M",
"PerPkg": "1", "PerPkg": "1",
...@@ -31,7 +28,6 @@ ...@@ -31,7 +28,6 @@
}, },
{ {
"BriefDescription": "L3 Lookup any request that access cache and found line in MESI-state", "BriefDescription": "L3 Lookup any request that access cache and found line in MESI-state",
"Counter": "0,1",
"EventCode": "0x34", "EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.ANY_MESI", "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_MESI",
"PerPkg": "1", "PerPkg": "1",
...@@ -41,7 +37,6 @@ ...@@ -41,7 +37,6 @@
}, },
{ {
"BriefDescription": "L3 Lookup read request that access cache and found line in E or S-state", "BriefDescription": "L3 Lookup read request that access cache and found line in E or S-state",
"Counter": "0,1",
"EventCode": "0x34", "EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.READ_ES", "EventName": "UNC_CBO_CACHE_LOOKUP.READ_ES",
"PerPkg": "1", "PerPkg": "1",
...@@ -51,7 +46,6 @@ ...@@ -51,7 +46,6 @@
}, },
{ {
"BriefDescription": "L3 Lookup read request that access cache and found line in I-state", "BriefDescription": "L3 Lookup read request that access cache and found line in I-state",
"Counter": "0,1",
"EventCode": "0x34", "EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.READ_I", "EventName": "UNC_CBO_CACHE_LOOKUP.READ_I",
"PerPkg": "1", "PerPkg": "1",
...@@ -61,7 +55,6 @@ ...@@ -61,7 +55,6 @@
}, },
{ {
"BriefDescription": "L3 Lookup read request that access cache and found line in M-state", "BriefDescription": "L3 Lookup read request that access cache and found line in M-state",
"Counter": "0,1",
"EventCode": "0x34", "EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.READ_M", "EventName": "UNC_CBO_CACHE_LOOKUP.READ_M",
"PerPkg": "1", "PerPkg": "1",
...@@ -71,7 +64,6 @@ ...@@ -71,7 +64,6 @@
}, },
{ {
"BriefDescription": "L3 Lookup read request that access cache and found line in any MESI-state", "BriefDescription": "L3 Lookup read request that access cache and found line in any MESI-state",
"Counter": "0,1",
"EventCode": "0x34", "EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.READ_MESI", "EventName": "UNC_CBO_CACHE_LOOKUP.READ_MESI",
"PerPkg": "1", "PerPkg": "1",
...@@ -81,7 +73,6 @@ ...@@ -81,7 +73,6 @@
}, },
{ {
"BriefDescription": "L3 Lookup write request that access cache and found line in E or S-state", "BriefDescription": "L3 Lookup write request that access cache and found line in E or S-state",
"Counter": "0,1",
"EventCode": "0x34", "EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_ES", "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_ES",
"PerPkg": "1", "PerPkg": "1",
...@@ -91,7 +82,6 @@ ...@@ -91,7 +82,6 @@
}, },
{ {
"BriefDescription": "L3 Lookup write request that access cache and found line in M-state", "BriefDescription": "L3 Lookup write request that access cache and found line in M-state",
"Counter": "0,1",
"EventCode": "0x34", "EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_M", "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_M",
"PerPkg": "1", "PerPkg": "1",
...@@ -101,7 +91,6 @@ ...@@ -101,7 +91,6 @@
}, },
{ {
"BriefDescription": "L3 Lookup write request that access cache and found line in MESI-state", "BriefDescription": "L3 Lookup write request that access cache and found line in MESI-state",
"Counter": "0,1",
"EventCode": "0x34", "EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_MESI", "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_MESI",
"PerPkg": "1", "PerPkg": "1",
...@@ -111,41 +100,33 @@ ...@@ -111,41 +100,33 @@
}, },
{ {
"BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a modified line in some processor core.", "BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a modified line in some processor core.",
"Counter": "0,1",
"EventCode": "0x22", "EventCode": "0x22",
"EventName": "UNC_CBO_XSNP_RESPONSE.HITM_XCORE", "EventName": "UNC_CBO_XSNP_RESPONSE.HITM_XCORE",
"PerPkg": "1", "PerPkg": "1",
"PublicDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a modified line in some processor core.",
"UMask": "0x48", "UMask": "0x48",
"Unit": "CBO" "Unit": "CBO"
}, },
{ {
"BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a non-modified line in some processor core.", "BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a non-modified line in some processor core.",
"Counter": "0,1",
"EventCode": "0x22", "EventCode": "0x22",
"EventName": "UNC_CBO_XSNP_RESPONSE.HIT_XCORE", "EventName": "UNC_CBO_XSNP_RESPONSE.HIT_XCORE",
"PerPkg": "1", "PerPkg": "1",
"PublicDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a non-modified line in some processor core.",
"UMask": "0x44", "UMask": "0x44",
"Unit": "CBO" "Unit": "CBO"
}, },
{ {
"BriefDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor core.", "BriefDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor core.",
"Counter": "0,1",
"EventCode": "0x22", "EventCode": "0x22",
"EventName": "UNC_CBO_XSNP_RESPONSE.MISS_EVICTION", "EventName": "UNC_CBO_XSNP_RESPONSE.MISS_EVICTION",
"PerPkg": "1", "PerPkg": "1",
"PublicDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor core.",
"UMask": "0x81", "UMask": "0x81",
"Unit": "CBO" "Unit": "CBO"
}, },
{ {
"BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which misses in some processor core.", "BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which misses in some processor core.",
"Counter": "0,1",
"EventCode": "0x22", "EventCode": "0x22",
"EventName": "UNC_CBO_XSNP_RESPONSE.MISS_XCORE", "EventName": "UNC_CBO_XSNP_RESPONSE.MISS_XCORE",
"PerPkg": "1", "PerPkg": "1",
"PublicDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which misses in some processor core.",
"UMask": "0x41", "UMask": "0x41",
"Unit": "CBO" "Unit": "CBO"
} }
......
tools/perf/pmu-events/arch/x86/broadwell/uncore-other.json
View file @ fec57a8e
[ [
{ {
"BriefDescription": "Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture, etc.", "BriefDescription": "Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture, etc.",
"Counter": "0,1",
"EventCode": "0x84", "EventCode": "0x84",
"EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL", "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL",
"PerPkg": "1", "PerPkg": "1",
"PublicDescription": "Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture, etc.", "UMask": "0x1",
"UMask": "0x01",
"Unit": "ARB" "Unit": "ARB"
}, },
{ {
"BriefDescription": "Each cycle count number of all Core outgoing valid entries. Such entry is defined as valid from it's allocation till first of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coherent traffic.", "BriefDescription": "Each cycle count number of all Core outgoing valid entries. Such entry is defined as valid from it's allocation till first of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coherent traffic.",
"Counter": "0,",
"EventCode": "0x80", "EventCode": "0x80",
"EventName": "UNC_ARB_TRK_OCCUPANCY.ALL", "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL",
"PerPkg": "1", "PerPkg": "1",
"PublicDescription": "Each cycle count number of all Core outgoing valid entries. Such entry is defined as valid from it's allocation till first of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coherent traffic.", "UMask": "0x1",
"UMask": "0x01",
"Unit": "ARB" "Unit": "ARB"
}, },
{ {
"BriefDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.;", "BriefDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.;",
"Counter": "0,",
"CounterMask": "1", "CounterMask": "1",
"EventCode": "0x80", "EventCode": "0x80",
"EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST", "EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST",
"PerPkg": "1", "PerPkg": "1",
"PublicDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.", "UMask": "0x1",
"UMask": "0x01",
"Unit": "ARB" "Unit": "ARB"
}, },
{ {
"BriefDescription": "Each cycle count number of 'valid' coherent Data Read entries that are in DirectData mode. Such entry is defined as valid when it is allocated till data sent to Core (first chunk, IDI0). Applicable for IA Cores' requests in normal case.", "BriefDescription": "Each cycle count number of 'valid' coherent Data Read entries that are in DirectData mode. Such entry is defined as valid when it is allocated till data sent to Core (first chunk, IDI0). Applicable for IA Cores' requests in normal case.",
"Counter": "0,",
"EventCode": "0x80", "EventCode": "0x80",
"EventName": "UNC_ARB_TRK_OCCUPANCY.DRD_DIRECT", "EventName": "UNC_ARB_TRK_OCCUPANCY.DRD_DIRECT",
"PerPkg": "1", "PerPkg": "1",
"PublicDescription": "Each cycle count number of valid coherent Data Read entries that are in DirectData mode. Such entry is defined as valid when it is allocated till data sent to Core (first chunk, IDI0). Applicable for IA Cores' requests in normal case.", "PublicDescription": "Each cycle count number of valid coherent Data Read entries that are in DirectData mode. Such entry is defined as valid when it is allocated till data sent to Core (first chunk, IDI0). Applicable for IA Cores' requests in normal case.",
"UMask": "0x02", "UMask": "0x2",
"Unit": "ARB" "Unit": "ARB"
}, },
{ {
"BriefDescription": "Total number of Core outgoing entries allocated. Accounts for Coherent and non-coherent traffic.", "BriefDescription": "Total number of Core outgoing entries allocated. Accounts for Coherent and non-coherent traffic.",
"Counter": "0,1",
"EventCode": "0x81", "EventCode": "0x81",
"EventName": "UNC_ARB_TRK_REQUESTS.ALL", "EventName": "UNC_ARB_TRK_REQUESTS.ALL",
"PerPkg": "1", "PerPkg": "1",
"PublicDescription": "Total number of Core outgoing entries allocated. Accounts for Coherent and non-coherent traffic.", "UMask": "0x1",
"UMask": "0x01",
"Unit": "ARB" "Unit": "ARB"
}, },
{ {
"BriefDescription": "Number of Core coherent Data Read entries allocated in DirectData mode", "BriefDescription": "Number of Core coherent Data Read entries allocated in DirectData mode",
"Counter": "0,1",
"EventCode": "0x81", "EventCode": "0x81",
"EventName": "UNC_ARB_TRK_REQUESTS.DRD_DIRECT", "EventName": "UNC_ARB_TRK_REQUESTS.DRD_DIRECT",
"PerPkg": "1", "PerPkg": "1",
"PublicDescription": "Number of Core coherent Data Read entries allocated in DirectData mode.", "PublicDescription": "Number of Core coherent Data Read entries allocated in DirectData mode.",
"UMask": "0x02", "UMask": "0x2",
"Unit": "ARB" "Unit": "ARB"
}, },
{ {
"BriefDescription": "Number of Writes allocated - any write transactions: full/partials writes and evictions.", "BriefDescription": "Number of Writes allocated - any write transactions: full/partials writes and evictions.",
"Counter": "0,1",
"EventCode": "0x81", "EventCode": "0x81",
"EventName": "UNC_ARB_TRK_REQUESTS.WRITES", "EventName": "UNC_ARB_TRK_REQUESTS.WRITES",
"PerPkg": "1", "PerPkg": "1",
"PublicDescription": "Number of Writes allocated - any write transactions: full/partials writes and evictions.",
"UMask": "0x20", "UMask": "0x20",
"Unit": "ARB" "Unit": "ARB"
}, },
{ {
"BriefDescription": "This 48-bit fixed counter counts the UCLK cycles", "BriefDescription": "This 48-bit fixed counter counts the UCLK cycles",
"Counter": "FIXED",
"EventCode": "0xff", "EventCode": "0xff",
"EventName": "UNC_CLOCK.SOCKET", "EventName": "UNC_CLOCK.SOCKET",
"PerPkg": "1", "PerPkg": "1",
......
tools/perf/pmu-events/arch/x86/broadwell/virtual-memory.json
View file @ fec57a8e
[ [
{ {
"BriefDescription": "Load misses in all DTLB levels that cause page walks", "BriefDescription": "Load misses in all DTLB levels that cause page walks",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69", "Errata": "BDM69",
"EventCode": "0x08", "EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK",
...@@ -12,8 +10,6 @@ ...@@ -12,8 +10,6 @@
}, },
{ {
"BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks.", "BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08", "EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.STLB_HIT", "EventName": "DTLB_LOAD_MISSES.STLB_HIT",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
...@@ -21,8 +17,6 @@ ...@@ -21,8 +17,6 @@
}, },
{ {
"BriefDescription": "Load misses that miss the DTLB and hit the STLB (2M).", "BriefDescription": "Load misses that miss the DTLB and hit the STLB (2M).",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08", "EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.STLB_HIT_2M", "EventName": "DTLB_LOAD_MISSES.STLB_HIT_2M",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
...@@ -30,8 +24,6 @@ ...@@ -30,8 +24,6 @@
}, },
{ {
"BriefDescription": "Load misses that miss the DTLB and hit the STLB (4K).", "BriefDescription": "Load misses that miss the DTLB and hit the STLB (4K).",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08", "EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.STLB_HIT_4K", "EventName": "DTLB_LOAD_MISSES.STLB_HIT_4K",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
...@@ -39,8 +31,6 @@ ...@@ -39,8 +31,6 @@
}, },
{ {
"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.", "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69", "Errata": "BDM69",
"EventCode": "0x08", "EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
...@@ -49,8 +39,6 @@ ...@@ -49,8 +39,6 @@
}, },
{ {
"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (1G)", "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (1G)",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69", "Errata": "BDM69",
"EventCode": "0x08", "EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G",
...@@ -60,8 +48,6 @@ ...@@ -60,8 +48,6 @@
}, },
{ {
"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (2M/4M).", "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (2M/4M).",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69", "Errata": "BDM69",
"EventCode": "0x08", "EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M",
...@@ -71,8 +57,6 @@ ...@@ -71,8 +57,6 @@
}, },
{ {
"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (4K).", "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (4K).",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69", "Errata": "BDM69",
"EventCode": "0x08", "EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K",
...@@ -82,8 +66,6 @@ ...@@ -82,8 +66,6 @@
}, },
{ {
"BriefDescription": "Cycles when PMH is busy with page walks", "BriefDescription": "Cycles when PMH is busy with page walks",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69", "Errata": "BDM69",
"EventCode": "0x08", "EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_DURATION", "EventName": "DTLB_LOAD_MISSES.WALK_DURATION",
...@@ -93,8 +75,6 @@ ...@@ -93,8 +75,6 @@
}, },
{ {
"BriefDescription": "Store misses in all DTLB levels that cause page walks", "BriefDescription": "Store misses in all DTLB levels that cause page walks",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69", "Errata": "BDM69",
"EventCode": "0x49", "EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK",
...@@ -104,8 +84,6 @@ ...@@ -104,8 +84,6 @@
}, },
{ {
"BriefDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks.", "BriefDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49", "EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.STLB_HIT", "EventName": "DTLB_STORE_MISSES.STLB_HIT",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
...@@ -113,8 +91,6 @@ ...@@ -113,8 +91,6 @@
}, },
{ {
"BriefDescription": "Store misses that miss the DTLB and hit the STLB (2M).", "BriefDescription": "Store misses that miss the DTLB and hit the STLB (2M).",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49", "EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.STLB_HIT_2M", "EventName": "DTLB_STORE_MISSES.STLB_HIT_2M",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
...@@ -122,8 +98,6 @@ ...@@ -122,8 +98,6 @@
}, },
{ {
"BriefDescription": "Store misses that miss the DTLB and hit the STLB (4K).", "BriefDescription": "Store misses that miss the DTLB and hit the STLB (4K).",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49", "EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.STLB_HIT_4K", "EventName": "DTLB_STORE_MISSES.STLB_HIT_4K",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
...@@ -131,8 +105,6 @@ ...@@ -131,8 +105,6 @@
}, },
{ {
"BriefDescription": "Store misses in all DTLB levels that cause completed page walks.", "BriefDescription": "Store misses in all DTLB levels that cause completed page walks.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69", "Errata": "BDM69",
"EventCode": "0x49", "EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
...@@ -141,8 +113,6 @@ ...@@ -141,8 +113,6 @@
}, },
{ {
"BriefDescription": "Store misses in all DTLB levels that cause completed page walks (1G)", "BriefDescription": "Store misses in all DTLB levels that cause completed page walks (1G)",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69", "Errata": "BDM69",
"EventCode": "0x49", "EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G",
...@@ -152,8 +122,6 @@ ...@@ -152,8 +122,6 @@
}, },
{ {
"BriefDescription": "Store misses in all DTLB levels that cause completed page walks (2M/4M)", "BriefDescription": "Store misses in all DTLB levels that cause completed page walks (2M/4M)",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69", "Errata": "BDM69",
"EventCode": "0x49", "EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M",
...@@ -163,8 +131,6 @@ ...@@ -163,8 +131,6 @@
}, },
{ {
"BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (4K)", "BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (4K)",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69", "Errata": "BDM69",
"EventCode": "0x49", "EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K",
...@@ -174,8 +140,6 @@ ...@@ -174,8 +140,6 @@
}, },
{ {
"BriefDescription": "Cycles when PMH is busy with page walks", "BriefDescription": "Cycles when PMH is busy with page walks",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69", "Errata": "BDM69",
"EventCode": "0x49", "EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_DURATION", "EventName": "DTLB_STORE_MISSES.WALK_DURATION",
...@@ -185,8 +149,6 @@ ...@@ -185,8 +149,6 @@
}, },
{ {
"BriefDescription": "Cycle count for an Extended Page table walk.", "BriefDescription": "Cycle count for an Extended Page table walk.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x4F", "EventCode": "0x4F",
"EventName": "EPT.WALK_CYCLES", "EventName": "EPT.WALK_CYCLES",
"PublicDescription": "This event counts cycles for an extended page table walk. The Extended Page directory cache differs from standard TLB caches by the operating system that use it. Virtual machine operating systems use the extended page directory cache, while guest operating systems use the standard TLB caches.", "PublicDescription": "This event counts cycles for an extended page table walk. The Extended Page directory cache differs from standard TLB caches by the operating system that use it. Virtual machine operating systems use the extended page directory cache, while guest operating systems use the standard TLB caches.",
...@@ -195,8 +157,6 @@ ...@@ -195,8 +157,6 @@
}, },
{ {
"BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.", "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xAE", "EventCode": "0xAE",
"EventName": "ITLB.ITLB_FLUSH", "EventName": "ITLB.ITLB_FLUSH",
"PublicDescription": "This event counts the number of flushes of the big or small ITLB pages. Counting include both TLB Flush (covering all sets) and TLB Set Clear (set-specific).", "PublicDescription": "This event counts the number of flushes of the big or small ITLB pages. Counting include both TLB Flush (covering all sets) and TLB Set Clear (set-specific).",
...@@ -205,8 +165,6 @@ ...@@ -205,8 +165,6 @@
}, },
{ {
"BriefDescription": "Misses at all ITLB levels that cause page walks", "BriefDescription": "Misses at all ITLB levels that cause page walks",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69", "Errata": "BDM69",
"EventCode": "0x85", "EventCode": "0x85",
"EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK", "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK",
...@@ -216,8 +174,6 @@ ...@@ -216,8 +174,6 @@
}, },
{ {
"BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks.", "BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85", "EventCode": "0x85",
"EventName": "ITLB_MISSES.STLB_HIT", "EventName": "ITLB_MISSES.STLB_HIT",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
...@@ -225,8 +181,6 @@ ...@@ -225,8 +181,6 @@
}, },
{ {
"BriefDescription": "Code misses that miss the DTLB and hit the STLB (2M).", "BriefDescription": "Code misses that miss the DTLB and hit the STLB (2M).",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85", "EventCode": "0x85",
"EventName": "ITLB_MISSES.STLB_HIT_2M", "EventName": "ITLB_MISSES.STLB_HIT_2M",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
...@@ -234,8 +188,6 @@ ...@@ -234,8 +188,6 @@
}, },
{ {
"BriefDescription": "Core misses that miss the DTLB and hit the STLB (4K).", "BriefDescription": "Core misses that miss the DTLB and hit the STLB (4K).",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85", "EventCode": "0x85",
"EventName": "ITLB_MISSES.STLB_HIT_4K", "EventName": "ITLB_MISSES.STLB_HIT_4K",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
...@@ -243,8 +195,6 @@ ...@@ -243,8 +195,6 @@
}, },
{ {
"BriefDescription": "Misses in all ITLB levels that cause completed page walks.", "BriefDescription": "Misses in all ITLB levels that cause completed page walks.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69", "Errata": "BDM69",
"EventCode": "0x85", "EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED", "EventName": "ITLB_MISSES.WALK_COMPLETED",
...@@ -253,8 +203,6 @@ ...@@ -253,8 +203,6 @@
}, },
{ {
"BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (1G)", "BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (1G)",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69", "Errata": "BDM69",
"EventCode": "0x85", "EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED_1G", "EventName": "ITLB_MISSES.WALK_COMPLETED_1G",
...@@ -264,8 +212,6 @@ ...@@ -264,8 +212,6 @@
}, },
{ {
"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)", "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69", "Errata": "BDM69",
"EventCode": "0x85", "EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M",
...@@ -275,8 +221,6 @@ ...@@ -275,8 +221,6 @@
}, },
{ {
"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)", "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69", "Errata": "BDM69",
"EventCode": "0x85", "EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED_4K", "EventName": "ITLB_MISSES.WALK_COMPLETED_4K",
...@@ -286,8 +230,6 @@ ...@@ -286,8 +230,6 @@
}, },
{ {
"BriefDescription": "Cycles when PMH is busy with page walks", "BriefDescription": "Cycles when PMH is busy with page walks",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69", "Errata": "BDM69",
"EventCode": "0x85", "EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_DURATION", "EventName": "ITLB_MISSES.WALK_DURATION",
...@@ -297,8 +239,6 @@ ...@@ -297,8 +239,6 @@
}, },
{ {
"BriefDescription": "Number of DTLB page walker hits in the L1+FB.", "BriefDescription": "Number of DTLB page walker hits in the L1+FB.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"Errata": "BDM69, BDM98", "Errata": "BDM69, BDM98",
"EventCode": "0xBC", "EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.DTLB_L1", "EventName": "PAGE_WALKER_LOADS.DTLB_L1",
...@@ -307,8 +247,6 @@ ...@@ -307,8 +247,6 @@
}, },
{ {
"BriefDescription": "Number of DTLB page walker hits in the L2.", "BriefDescription": "Number of DTLB page walker hits in the L2.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"Errata": "BDM69, BDM98", "Errata": "BDM69, BDM98",
"EventCode": "0xBC", "EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.DTLB_L2", "EventName": "PAGE_WALKER_LOADS.DTLB_L2",
...@@ -317,8 +255,6 @@ ...@@ -317,8 +255,6 @@
}, },
{ {
"BriefDescription": "Number of DTLB page walker hits in the L3 + XSNP.", "BriefDescription": "Number of DTLB page walker hits in the L3 + XSNP.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"Errata": "BDM69, BDM98", "Errata": "BDM69, BDM98",
"EventCode": "0xBC", "EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.DTLB_L3", "EventName": "PAGE_WALKER_LOADS.DTLB_L3",
...@@ -327,8 +263,6 @@ ...@@ -327,8 +263,6 @@
}, },
{ {
"BriefDescription": "Number of DTLB page walker hits in Memory.", "BriefDescription": "Number of DTLB page walker hits in Memory.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"Errata": "BDM69, BDM98", "Errata": "BDM69, BDM98",
"EventCode": "0xBC", "EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.DTLB_MEMORY", "EventName": "PAGE_WALKER_LOADS.DTLB_MEMORY",
...@@ -337,8 +271,6 @@ ...@@ -337,8 +271,6 @@
}, },
{ {
"BriefDescription": "Number of ITLB page walker hits in the L1+FB.", "BriefDescription": "Number of ITLB page walker hits in the L1+FB.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"Errata": "BDM69, BDM98", "Errata": "BDM69, BDM98",
"EventCode": "0xBC", "EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.ITLB_L1", "EventName": "PAGE_WALKER_LOADS.ITLB_L1",
...@@ -347,8 +279,6 @@ ...@@ -347,8 +279,6 @@
}, },
{ {
"BriefDescription": "Number of ITLB page walker hits in the L2.", "BriefDescription": "Number of ITLB page walker hits in the L2.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"Errata": "BDM69, BDM98", "Errata": "BDM69, BDM98",
"EventCode": "0xBC", "EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.ITLB_L2", "EventName": "PAGE_WALKER_LOADS.ITLB_L2",
...@@ -357,8 +287,6 @@ ...@@ -357,8 +287,6 @@
}, },
{ {
"BriefDescription": "Number of ITLB page walker hits in the L3 + XSNP.", "BriefDescription": "Number of ITLB page walker hits in the L3 + XSNP.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"Errata": "BDM69, BDM98", "Errata": "BDM69, BDM98",
"EventCode": "0xBC", "EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.ITLB_L3", "EventName": "PAGE_WALKER_LOADS.ITLB_L3",
...@@ -367,8 +295,6 @@ ...@@ -367,8 +295,6 @@
}, },
{ {
"BriefDescription": "DTLB flush attempts of the thread-specific entries", "BriefDescription": "DTLB flush attempts of the thread-specific entries",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xBD", "EventCode": "0xBD",
"EventName": "TLB_FLUSH.DTLB_THREAD", "EventName": "TLB_FLUSH.DTLB_THREAD",
"PublicDescription": "This event counts the number of DTLB flush attempts of the thread-specific entries.", "PublicDescription": "This event counts the number of DTLB flush attempts of the thread-specific entries.",
...@@ -377,8 +303,6 @@ ...@@ -377,8 +303,6 @@
}, },
{ {
"BriefDescription": "STLB flush attempts", "BriefDescription": "STLB flush attempts",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xBD", "EventCode": "0xBD",
"EventName": "TLB_FLUSH.STLB_ANY", "EventName": "TLB_FLUSH.STLB_ANY",
"PublicDescription": "This event counts the number of any STLB flush attempts (such as entire, VPID, PCID, InvPage, CR3 write, and so on).", "PublicDescription": "This event counts the number of any STLB flush attempts (such as entire, VPID, PCID, InvPage, CR3 write, and so on).",
......
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