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nexedi
dream
Commits
1d4fc3c6
Commit
1d4fc3c6
authored
Sep 09, 2014
by
Georgios Dagkakis
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CoreObject to send isRequested also in the new way
parent
9164973f
Changes
2
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2 changed files
with
5 additions
and
2 deletions
+5
-2
dream/simulation/Assembly.py
dream/simulation/Assembly.py
+1
-0
dream/simulation/CoreObject.py
dream/simulation/CoreObject.py
+4
-2
No files found.
dream/simulation/Assembly.py
View file @
1d4fc3c6
...
...
@@ -168,6 +168,7 @@ class Assembly(CoreObject):
for
i
in
range
(
self
.
getActiveObjectQueue
()[
0
].
capacity
):
#this loop will be carried until the Frame is full with the parts
self
.
printTrace
(
self
.
id
,
waitEvent
=
'(to load parts)'
)
self
.
expectedSignals
[
'isRequested'
]
=
1
yield
self
.
isRequested
if
self
.
isRequested
.
value
:
transmitter
,
eventTime
=
self
.
isRequested
.
value
...
...
dream/simulation/CoreObject.py
View file @
1d4fc3c6
...
...
@@ -493,8 +493,10 @@ class CoreObject(ManPyObject):
self
.
printTrace
(
self
.
id
,
signalReceiver
=
self
.
receiver
.
id
)
# assign the entry of the receiver
self
.
receiver
.
assignEntryTo
()
succeedTuple
=
(
self
,
self
.
env
.
now
)
self
.
receiver
.
isRequested
.
succeed
(
succeedTuple
)
if
self
.
receiver
.
expectedSignals
[
'isRequested'
]:
succeedTuple
=
(
self
,
self
.
env
.
now
)
self
.
receiver
.
isRequested
.
succeed
(
succeedTuple
)
self
.
receiver
.
expectedSignals
[
'isRequested'
]
=
0
return
True
# if no receiver can accept then try to preempt a receive if the stations holds a critical order
self
.
preemptReceiver
()
...
...
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