spi-pxa2xx.c 50 KB
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/*
 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
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 * Copyright (C) 2013, Intel Corporation
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 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

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#include <linux/bitops.h>
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#include <linux/init.h>
#include <linux/module.h>
#include <linux/device.h>
#include <linux/ioport.h>
#include <linux/errno.h>
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#include <linux/err.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/platform_device.h>
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#include <linux/spi/pxa2xx_spi.h>
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#include <linux/spi/spi.h>
#include <linux/delay.h>
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#include <linux/gpio.h>
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#include <linux/gpio/consumer.h>
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#include <linux/slab.h>
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#include <linux/clk.h>
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#include <linux/pm_runtime.h>
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#include <linux/acpi.h>
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#include <linux/of_device.h>
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#include "spi-pxa2xx.h"
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MODULE_AUTHOR("Stephen Street");
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MODULE_DESCRIPTION("PXA2xx SSP SPI Controller");
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MODULE_LICENSE("GPL");
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MODULE_ALIAS("platform:pxa2xx-spi");
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#define TIMOUT_DFLT		1000

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/*
 * for testing SSCR1 changes that require SSP restart, basically
 * everything except the service and interrupt enables, the pxa270 developer
 * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this
 * list, but the PXA255 dev man says all bits without really meaning the
 * service and interrupt enables
 */
#define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \
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				| SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
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				| SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \
				| SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \
				| SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \
				| SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
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#define QUARK_X1000_SSCR1_CHANGE_MASK (QUARK_X1000_SSCR1_STRF	\
				| QUARK_X1000_SSCR1_EFWR	\
				| QUARK_X1000_SSCR1_RFT		\
				| QUARK_X1000_SSCR1_TFT		\
				| SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)

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#define CE4100_SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \
				| SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
				| SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \
				| SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \
				| CE4100_SSCR1_RFT | CE4100_SSCR1_TFT | SSCR1_MWDS \
				| SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)

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#define LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE	BIT(24)
#define LPSS_CS_CONTROL_SW_MODE			BIT(0)
#define LPSS_CS_CONTROL_CS_HIGH			BIT(1)
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#define LPSS_CAPS_CS_EN_SHIFT			9
#define LPSS_CAPS_CS_EN_MASK			(0xf << LPSS_CAPS_CS_EN_SHIFT)
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struct lpss_config {
	/* LPSS offset from drv_data->ioaddr */
	unsigned offset;
	/* Register offsets from drv_data->lpss_base or -1 */
	int reg_general;
	int reg_ssp;
	int reg_cs_ctrl;
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	int reg_capabilities;
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	/* FIFO thresholds */
	u32 rx_threshold;
	u32 tx_threshold_lo;
	u32 tx_threshold_hi;
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	/* Chip select control */
	unsigned cs_sel_shift;
	unsigned cs_sel_mask;
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	unsigned cs_num;
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};

/* Keep these sorted with enum pxa_ssp_type */
static const struct lpss_config lpss_platforms[] = {
	{	/* LPSS_LPT_SSP */
		.offset = 0x800,
		.reg_general = 0x08,
		.reg_ssp = 0x0c,
		.reg_cs_ctrl = 0x18,
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		.reg_capabilities = -1,
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		.rx_threshold = 64,
		.tx_threshold_lo = 160,
		.tx_threshold_hi = 224,
	},
	{	/* LPSS_BYT_SSP */
		.offset = 0x400,
		.reg_general = 0x08,
		.reg_ssp = 0x0c,
		.reg_cs_ctrl = 0x18,
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		.reg_capabilities = -1,
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		.rx_threshold = 64,
		.tx_threshold_lo = 160,
		.tx_threshold_hi = 224,
	},
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	{	/* LPSS_BSW_SSP */
		.offset = 0x400,
		.reg_general = 0x08,
		.reg_ssp = 0x0c,
		.reg_cs_ctrl = 0x18,
		.reg_capabilities = -1,
		.rx_threshold = 64,
		.tx_threshold_lo = 160,
		.tx_threshold_hi = 224,
		.cs_sel_shift = 2,
		.cs_sel_mask = 1 << 2,
		.cs_num = 2,
	},
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	{	/* LPSS_SPT_SSP */
		.offset = 0x200,
		.reg_general = -1,
		.reg_ssp = 0x20,
		.reg_cs_ctrl = 0x24,
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		.reg_capabilities = -1,
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		.rx_threshold = 1,
		.tx_threshold_lo = 32,
		.tx_threshold_hi = 56,
	},
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	{	/* LPSS_BXT_SSP */
		.offset = 0x200,
		.reg_general = -1,
		.reg_ssp = 0x20,
		.reg_cs_ctrl = 0x24,
		.reg_capabilities = 0xfc,
		.rx_threshold = 1,
		.tx_threshold_lo = 16,
		.tx_threshold_hi = 48,
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		.cs_sel_shift = 8,
		.cs_sel_mask = 3 << 8,
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	},
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	{	/* LPSS_CNL_SSP */
		.offset = 0x200,
		.reg_general = -1,
		.reg_ssp = 0x20,
		.reg_cs_ctrl = 0x24,
		.reg_capabilities = 0xfc,
		.rx_threshold = 1,
		.tx_threshold_lo = 32,
		.tx_threshold_hi = 56,
		.cs_sel_shift = 8,
		.cs_sel_mask = 3 << 8,
	},
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};

static inline const struct lpss_config
*lpss_get_config(const struct driver_data *drv_data)
{
	return &lpss_platforms[drv_data->ssp_type - LPSS_LPT_SSP];
}

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static bool is_lpss_ssp(const struct driver_data *drv_data)
{
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	switch (drv_data->ssp_type) {
	case LPSS_LPT_SSP:
	case LPSS_BYT_SSP:
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	case LPSS_BSW_SSP:
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	case LPSS_SPT_SSP:
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	case LPSS_BXT_SSP:
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	case LPSS_CNL_SSP:
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		return true;
	default:
		return false;
	}
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}

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static bool is_quark_x1000_ssp(const struct driver_data *drv_data)
{
	return drv_data->ssp_type == QUARK_X1000_SSP;
}

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static u32 pxa2xx_spi_get_ssrc1_change_mask(const struct driver_data *drv_data)
{
	switch (drv_data->ssp_type) {
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	case QUARK_X1000_SSP:
		return QUARK_X1000_SSCR1_CHANGE_MASK;
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	case CE4100_SSP:
		return CE4100_SSCR1_CHANGE_MASK;
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	default:
		return SSCR1_CHANGE_MASK;
	}
}

static u32
pxa2xx_spi_get_rx_default_thre(const struct driver_data *drv_data)
{
	switch (drv_data->ssp_type) {
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	case QUARK_X1000_SSP:
		return RX_THRESH_QUARK_X1000_DFLT;
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	case CE4100_SSP:
		return RX_THRESH_CE4100_DFLT;
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	default:
		return RX_THRESH_DFLT;
	}
}

static bool pxa2xx_spi_txfifo_full(const struct driver_data *drv_data)
{
	u32 mask;

	switch (drv_data->ssp_type) {
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	case QUARK_X1000_SSP:
		mask = QUARK_X1000_SSSR_TFL_MASK;
		break;
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	case CE4100_SSP:
		mask = CE4100_SSSR_TFL_MASK;
		break;
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	default:
		mask = SSSR_TFL_MASK;
		break;
	}

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	return (pxa2xx_spi_read(drv_data, SSSR) & mask) == mask;
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}

static void pxa2xx_spi_clear_rx_thre(const struct driver_data *drv_data,
				     u32 *sccr1_reg)
{
	u32 mask;

	switch (drv_data->ssp_type) {
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	case QUARK_X1000_SSP:
		mask = QUARK_X1000_SSCR1_RFT;
		break;
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	case CE4100_SSP:
		mask = CE4100_SSCR1_RFT;
		break;
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	default:
		mask = SSCR1_RFT;
		break;
	}
	*sccr1_reg &= ~mask;
}

static void pxa2xx_spi_set_rx_thre(const struct driver_data *drv_data,
				   u32 *sccr1_reg, u32 threshold)
{
	switch (drv_data->ssp_type) {
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	case QUARK_X1000_SSP:
		*sccr1_reg |= QUARK_X1000_SSCR1_RxTresh(threshold);
		break;
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	case CE4100_SSP:
		*sccr1_reg |= CE4100_SSCR1_RxTresh(threshold);
		break;
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	default:
		*sccr1_reg |= SSCR1_RxTresh(threshold);
		break;
	}
}

static u32 pxa2xx_configure_sscr0(const struct driver_data *drv_data,
				  u32 clk_div, u8 bits)
{
	switch (drv_data->ssp_type) {
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	case QUARK_X1000_SSP:
		return clk_div
			| QUARK_X1000_SSCR0_Motorola
			| QUARK_X1000_SSCR0_DataSize(bits > 32 ? 8 : bits)
			| SSCR0_SSE;
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	default:
		return clk_div
			| SSCR0_Motorola
			| SSCR0_DataSize(bits > 16 ? bits - 16 : bits)
			| SSCR0_SSE
			| (bits > 16 ? SSCR0_EDSS : 0);
	}
}

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/*
 * Read and write LPSS SSP private registers. Caller must first check that
 * is_lpss_ssp() returns true before these can be called.
 */
static u32 __lpss_ssp_read_priv(struct driver_data *drv_data, unsigned offset)
{
	WARN_ON(!drv_data->lpss_base);
	return readl(drv_data->lpss_base + offset);
}

static void __lpss_ssp_write_priv(struct driver_data *drv_data,
				  unsigned offset, u32 value)
{
	WARN_ON(!drv_data->lpss_base);
	writel(value, drv_data->lpss_base + offset);
}

/*
 * lpss_ssp_setup - perform LPSS SSP specific setup
 * @drv_data: pointer to the driver private data
 *
 * Perform LPSS SSP specific setup. This function must be called first if
 * one is going to use LPSS SSP private registers.
 */
static void lpss_ssp_setup(struct driver_data *drv_data)
{
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	const struct lpss_config *config;
	u32 value;
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	config = lpss_get_config(drv_data);
	drv_data->lpss_base = drv_data->ioaddr + config->offset;
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	/* Enable software chip select control */
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	value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
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	value &= ~(LPSS_CS_CONTROL_SW_MODE | LPSS_CS_CONTROL_CS_HIGH);
	value |= LPSS_CS_CONTROL_SW_MODE | LPSS_CS_CONTROL_CS_HIGH;
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	__lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value);
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	/* Enable multiblock DMA transfers */
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	if (drv_data->controller_info->enable_dma) {
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		__lpss_ssp_write_priv(drv_data, config->reg_ssp, 1);
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		if (config->reg_general >= 0) {
			value = __lpss_ssp_read_priv(drv_data,
						     config->reg_general);
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			value |= LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE;
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			__lpss_ssp_write_priv(drv_data,
					      config->reg_general, value);
		}
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	}
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}

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static void lpss_ssp_select_cs(struct spi_device *spi,
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			       const struct lpss_config *config)
{
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	struct driver_data *drv_data =
		spi_controller_get_devdata(spi->controller);
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	u32 value, cs;

	if (!config->cs_sel_mask)
		return;

	value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);

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	cs = spi->chip_select;
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	cs <<= config->cs_sel_shift;
	if (cs != (value & config->cs_sel_mask)) {
		/*
		 * When switching another chip select output active the
		 * output must be selected first and wait 2 ssp_clk cycles
		 * before changing state to active. Otherwise a short
		 * glitch will occur on the previous chip select since
		 * output select is latched but state control is not.
		 */
		value &= ~config->cs_sel_mask;
		value |= cs;
		__lpss_ssp_write_priv(drv_data,
				      config->reg_cs_ctrl, value);
		ndelay(1000000000 /
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		       (drv_data->controller->max_speed_hz / 2));
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	}
}

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static void lpss_ssp_cs_control(struct spi_device *spi, bool enable)
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{
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	struct driver_data *drv_data =
		spi_controller_get_devdata(spi->controller);
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	const struct lpss_config *config;
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	u32 value;
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	config = lpss_get_config(drv_data);

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	if (enable)
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		lpss_ssp_select_cs(spi, config);
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	value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
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	if (enable)
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		value &= ~LPSS_CS_CONTROL_CS_HIGH;
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	else
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		value |= LPSS_CS_CONTROL_CS_HIGH;
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	__lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value);
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}

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static void cs_assert(struct spi_device *spi)
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{
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	struct chip_data *chip = spi_get_ctldata(spi);
	struct driver_data *drv_data =
		spi_controller_get_devdata(spi->controller);
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	if (drv_data->ssp_type == CE4100_SSP) {
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		pxa2xx_spi_write(drv_data, SSSR, chip->frm);
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		return;
	}

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	if (chip->cs_control) {
		chip->cs_control(PXA2XX_CS_ASSERT);
		return;
	}

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	if (chip->gpiod_cs) {
		gpiod_set_value(chip->gpiod_cs, chip->gpio_cs_inverted);
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		return;
	}

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	if (is_lpss_ssp(drv_data))
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		lpss_ssp_cs_control(spi, true);
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}

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static void cs_deassert(struct spi_device *spi)
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{
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	struct chip_data *chip = spi_get_ctldata(spi);
	struct driver_data *drv_data =
		spi_controller_get_devdata(spi->controller);
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	unsigned long timeout;
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	if (drv_data->ssp_type == CE4100_SSP)
		return;

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	/* Wait until SSP becomes idle before deasserting the CS */
	timeout = jiffies + msecs_to_jiffies(10);
	while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY &&
	       !time_after(jiffies, timeout))
		cpu_relax();

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	if (chip->cs_control) {
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		chip->cs_control(PXA2XX_CS_DEASSERT);
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		return;
	}

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	if (chip->gpiod_cs) {
		gpiod_set_value(chip->gpiod_cs, !chip->gpio_cs_inverted);
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		return;
	}

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	if (is_lpss_ssp(drv_data))
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		lpss_ssp_cs_control(spi, false);
}

static void pxa2xx_spi_set_cs(struct spi_device *spi, bool level)
{
	if (level)
		cs_deassert(spi);
	else
		cs_assert(spi);
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}

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int pxa2xx_spi_flush(struct driver_data *drv_data)
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{
	unsigned long limit = loops_per_jiffy << 1;

	do {
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		while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
			pxa2xx_spi_read(drv_data, SSDR);
	} while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY) && --limit);
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	write_SSSR_CS(drv_data, SSSR_ROR);
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	return limit;
}

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static int null_writer(struct driver_data *drv_data)
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{
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	u8 n_bytes = drv_data->n_bytes;
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	if (pxa2xx_spi_txfifo_full(drv_data)
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		|| (drv_data->tx == drv_data->tx_end))
		return 0;

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	pxa2xx_spi_write(drv_data, SSDR, 0);
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	drv_data->tx += n_bytes;

	return 1;
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}

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static int null_reader(struct driver_data *drv_data)
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{
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	u8 n_bytes = drv_data->n_bytes;
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	while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
	       && (drv_data->rx < drv_data->rx_end)) {
		pxa2xx_spi_read(drv_data, SSDR);
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		drv_data->rx += n_bytes;
	}
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	return drv_data->rx == drv_data->rx_end;
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}

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static int u8_writer(struct driver_data *drv_data)
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{
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	if (pxa2xx_spi_txfifo_full(drv_data)
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		|| (drv_data->tx == drv_data->tx_end))
		return 0;

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	pxa2xx_spi_write(drv_data, SSDR, *(u8 *)(drv_data->tx));
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	++drv_data->tx;

	return 1;
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}

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static int u8_reader(struct driver_data *drv_data)
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{
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	while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
	       && (drv_data->rx < drv_data->rx_end)) {
		*(u8 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
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		++drv_data->rx;
	}
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	return drv_data->rx == drv_data->rx_end;
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}

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static int u16_writer(struct driver_data *drv_data)
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{
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	if (pxa2xx_spi_txfifo_full(drv_data)
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		|| (drv_data->tx == drv_data->tx_end))
		return 0;

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	pxa2xx_spi_write(drv_data, SSDR, *(u16 *)(drv_data->tx));
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	drv_data->tx += 2;

	return 1;
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}

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static int u16_reader(struct driver_data *drv_data)
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{
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	while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
	       && (drv_data->rx < drv_data->rx_end)) {
		*(u16 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
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		drv_data->rx += 2;
	}
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	return drv_data->rx == drv_data->rx_end;
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}
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static int u32_writer(struct driver_data *drv_data)
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{
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	if (pxa2xx_spi_txfifo_full(drv_data)
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		|| (drv_data->tx == drv_data->tx_end))
		return 0;

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	pxa2xx_spi_write(drv_data, SSDR, *(u32 *)(drv_data->tx));
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	drv_data->tx += 4;

	return 1;
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}

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static int u32_reader(struct driver_data *drv_data)
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{
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	while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
	       && (drv_data->rx < drv_data->rx_end)) {
		*(u32 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
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		drv_data->rx += 4;
	}
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	return drv_data->rx == drv_data->rx_end;
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}

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static void reset_sccr1(struct driver_data *drv_data)
{
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	struct chip_data *chip =
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		spi_get_ctldata(drv_data->controller->cur_msg->spi);
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	u32 sccr1_reg;

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	sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1) & ~drv_data->int_cr1;
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	switch (drv_data->ssp_type) {
	case QUARK_X1000_SSP:
		sccr1_reg &= ~QUARK_X1000_SSCR1_RFT;
		break;
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	case CE4100_SSP:
		sccr1_reg &= ~CE4100_SSCR1_RFT;
		break;
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	default:
		sccr1_reg &= ~SSCR1_RFT;
		break;
	}
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	sccr1_reg |= chip->threshold;
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	pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
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}

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static void int_error_stop(struct driver_data *drv_data, const char* msg)
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{
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	/* Stop and reset SSP */
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	write_SSSR_CS(drv_data, drv_data->clear_sr);
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	reset_sccr1(drv_data);
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	if (!pxa25x_ssp_comp(drv_data))
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		pxa2xx_spi_write(drv_data, SSTO, 0);
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	pxa2xx_spi_flush(drv_data);
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	pxa2xx_spi_write(drv_data, SSCR0,
			 pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
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	dev_err(&drv_data->pdev->dev, "%s\n", msg);
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	drv_data->controller->cur_msg->status = -EIO;
	spi_finalize_current_transfer(drv_data->controller);
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}
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static void int_transfer_complete(struct driver_data *drv_data)
{
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	/* Clear and disable interrupts */
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	write_SSSR_CS(drv_data, drv_data->clear_sr);
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	reset_sccr1(drv_data);
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	if (!pxa25x_ssp_comp(drv_data))
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		pxa2xx_spi_write(drv_data, SSTO, 0);
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	spi_finalize_current_transfer(drv_data->controller);
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}
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static irqreturn_t interrupt_transfer(struct driver_data *drv_data)
{
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	u32 irq_mask = (pxa2xx_spi_read(drv_data, SSCR1) & SSCR1_TIE) ?
		       drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS;
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	u32 irq_status = pxa2xx_spi_read(drv_data, SSSR) & irq_mask;
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	if (irq_status & SSSR_ROR) {
		int_error_stop(drv_data, "interrupt_transfer: fifo overrun");
		return IRQ_HANDLED;
	}
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	if (irq_status & SSSR_TUR) {
		int_error_stop(drv_data, "interrupt_transfer: fifo underrun");
		return IRQ_HANDLED;
	}

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	if (irq_status & SSSR_TINT) {
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		pxa2xx_spi_write(drv_data, SSSR, SSSR_TINT);
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		if (drv_data->read(drv_data)) {
			int_transfer_complete(drv_data);
			return IRQ_HANDLED;
		}
	}
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	/* Drain rx fifo, Fill tx fifo and prevent overruns */
	do {
		if (drv_data->read(drv_data)) {
			int_transfer_complete(drv_data);
			return IRQ_HANDLED;
		}
	} while (drv_data->write(drv_data));
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	if (drv_data->read(drv_data)) {
		int_transfer_complete(drv_data);
		return IRQ_HANDLED;
	}
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	if (drv_data->tx == drv_data->tx_end) {
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		u32 bytes_left;
		u32 sccr1_reg;

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		sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1);
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		sccr1_reg &= ~SSCR1_TIE;

		/*
		 * PXA25x_SSP has no timeout, set up rx threshould for the
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		 * remaining RX bytes.
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		 */
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		if (pxa25x_ssp_comp(drv_data)) {
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			u32 rx_thre;
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			pxa2xx_spi_clear_rx_thre(drv_data, &sccr1_reg);
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			bytes_left = drv_data->rx_end - drv_data->rx;
			switch (drv_data->n_bytes) {
			case 4:
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				bytes_left >>= 2;
				break;
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			case 2:
				bytes_left >>= 1;
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				break;
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			}
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			rx_thre = pxa2xx_spi_get_rx_default_thre(drv_data);
			if (rx_thre > bytes_left)
				rx_thre = bytes_left;
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			pxa2xx_spi_set_rx_thre(drv_data, &sccr1_reg, rx_thre);
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		}
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		pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
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	}

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	/* We did something */
	return IRQ_HANDLED;
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}

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static void handle_bad_msg(struct driver_data *drv_data)
{
	pxa2xx_spi_write(drv_data, SSCR0,
			 pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
	pxa2xx_spi_write(drv_data, SSCR1,
			 pxa2xx_spi_read(drv_data, SSCR1) & ~drv_data->int_cr1);
	if (!pxa25x_ssp_comp(drv_data))
		pxa2xx_spi_write(drv_data, SSTO, 0);
	write_SSSR_CS(drv_data, drv_data->clear_sr);

	dev_err(&drv_data->pdev->dev,
		"bad message state in interrupt handler\n");
}

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static irqreturn_t ssp_int(int irq, void *dev_id)
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{
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	struct driver_data *drv_data = dev_id;
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	u32 sccr1_reg;
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	u32 mask = drv_data->mask_sr;
	u32 status;

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	/*
	 * The IRQ might be shared with other peripherals so we must first
	 * check that are we RPM suspended or not. If we are we assume that
	 * the IRQ was not for us (we shouldn't be RPM suspended when the
	 * interrupt is enabled).
	 */
	if (pm_runtime_suspended(&drv_data->pdev->dev))
		return IRQ_NONE;

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	/*
	 * If the device is not yet in RPM suspended state and we get an
	 * interrupt that is meant for another device, check if status bits
	 * are all set to one. That means that the device is already
	 * powered off.
	 */
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	status = pxa2xx_spi_read(drv_data, SSSR);
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	if (status == ~0)
		return IRQ_NONE;

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	sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1);
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	/* Ignore possible writes if we don't need to write */
	if (!(sccr1_reg & SSCR1_TIE))
		mask &= ~SSSR_TFS;

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	/* Ignore RX timeout interrupt if it is disabled */
	if (!(sccr1_reg & SSCR1_TINTE))
		mask &= ~SSSR_TINT;

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	if (!(status & mask))
		return IRQ_NONE;
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	pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg & ~drv_data->int_cr1);
	pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
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	if (!drv_data->controller->cur_msg) {
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		handle_bad_msg(drv_data);
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		/* Never fail */
		return IRQ_HANDLED;
	}

	return drv_data->transfer_handler(drv_data);
}

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/*
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 * The Quark SPI has an additional 24 bit register (DDS_CLK_RATE) to multiply
 * input frequency by fractions of 2^24. It also has a divider by 5.
 *
 * There are formulas to get baud rate value for given input frequency and
 * divider parameters, such as DDS_CLK_RATE and SCR:
 *
 * Fsys = 200MHz
 *
 * Fssp = Fsys * DDS_CLK_RATE / 2^24			(1)
 * Baud rate = Fsclk = Fssp / (2 * (SCR + 1))		(2)
 *
 * DDS_CLK_RATE either 2^n or 2^n / 5.
 * SCR is in range 0 .. 255
 *
 * Divisor = 5^i * 2^j * 2 * k
 *       i = [0, 1]      i = 1 iff j = 0 or j > 3
 *       j = [0, 23]     j = 0 iff i = 1
 *       k = [1, 256]
 * Special case: j = 0, i = 1: Divisor = 2 / 5
 *
 * Accordingly to the specification the recommended values for DDS_CLK_RATE
 * are:
 *	Case 1:		2^n, n = [0, 23]
 *	Case 2:		2^24 * 2 / 5 (0x666666)
 *	Case 3:		less than or equal to 2^24 / 5 / 16 (0x33333)
 *
 * In all cases the lowest possible value is better.
 *
 * The function calculates parameters for all cases and chooses the one closest
 * to the asked baud rate.
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 */
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static unsigned int quark_x1000_get_clk_div(int rate, u32 *dds)
{
	unsigned long xtal = 200000000;
	unsigned long fref = xtal / 2;		/* mandatory division by 2,
						   see (2) */
						/* case 3 */
	unsigned long fref1 = fref / 2;		/* case 1 */
	unsigned long fref2 = fref * 2 / 5;	/* case 2 */
	unsigned long scale;
	unsigned long q, q1, q2;
	long r, r1, r2;
	u32 mul;

	/* Case 1 */

	/* Set initial value for DDS_CLK_RATE */
	mul = (1 << 24) >> 1;

	/* Calculate initial quot */
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	q1 = DIV_ROUND_UP(fref1, rate);
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	/* Scale q1 if it's too big */
	if (q1 > 256) {
		/* Scale q1 to range [1, 512] */
		scale = fls_long(q1 - 1);
		if (scale > 9) {
			q1 >>= scale - 9;
			mul >>= scale - 9;
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		}
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		/* Round the result if we have a remainder */
		q1 += q1 & 1;
	}

	/* Decrease DDS_CLK_RATE as much as we can without loss in precision */
	scale = __ffs(q1);
	q1 >>= scale;
	mul >>= scale;

	/* Get the remainder */
	r1 = abs(fref1 / (1 << (24 - fls_long(mul))) / q1 - rate);

	/* Case 2 */

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	q2 = DIV_ROUND_UP(fref2, rate);
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	r2 = abs(fref2 / q2 - rate);

	/*
	 * Choose the best between two: less remainder we have the better. We
	 * can't go case 2 if q2 is greater than 256 since SCR register can
	 * hold only values 0 .. 255.
	 */
	if (r2 >= r1 || q2 > 256) {
		/* case 1 is better */
		r = r1;
		q = q1;
	} else {
		/* case 2 is better */
		r = r2;
		q = q2;
		mul = (1 << 24) * 2 / 5;
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	}

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	/* Check case 3 only if the divisor is big enough */
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	if (fref / rate >= 80) {
		u64 fssp;
		u32 m;

		/* Calculate initial quot */
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		q1 = DIV_ROUND_UP(fref, rate);
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		m = (1 << 24) / q1;

		/* Get the remainder */
		fssp = (u64)fref * m;
		do_div(fssp, 1 << 24);
		r1 = abs(fssp - rate);

		/* Choose this one if it suits better */
		if (r1 < r) {
			/* case 3 is better */
			q = 1;
			mul = m;
		}
	}
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	*dds = mul;
	return q - 1;
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}

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static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate)
881
{
882
	unsigned long ssp_clk = drv_data->controller->max_speed_hz;
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	const struct ssp_device *ssp = drv_data->ssp;

	rate = min_t(int, ssp_clk, rate);
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	if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP)
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		return (ssp_clk / (2 * rate) - 1) & 0xff;
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	else
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		return (ssp_clk / rate - 1) & 0xfff;
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}

893
static unsigned int pxa2xx_ssp_get_clk_div(struct driver_data *drv_data,
894
					   int rate)
895
{
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	struct chip_data *chip =
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		spi_get_ctldata(drv_data->controller->cur_msg->spi);
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	unsigned int clk_div;
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	switch (drv_data->ssp_type) {
	case QUARK_X1000_SSP:
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		clk_div = quark_x1000_get_clk_div(rate, &chip->dds_rate);
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		break;
904
	default:
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		clk_div = ssp_get_clk_div(drv_data, rate);
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		break;
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	}
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	return clk_div << 8;
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}

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static bool pxa2xx_spi_can_dma(struct spi_controller *controller,
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			       struct spi_device *spi,
			       struct spi_transfer *xfer)
{
	struct chip_data *chip = spi_get_ctldata(spi);

	return chip->enable_dma &&
	       xfer->len <= MAX_DMA_LEN &&
	       xfer->len >= chip->dma_burst_size;
}

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static int pxa2xx_spi_transfer_one(struct spi_controller *controller,
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				   struct spi_device *spi,
				   struct spi_transfer *transfer)
925
{
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	struct driver_data *drv_data = spi_controller_get_devdata(controller);
	struct spi_message *message = controller->cur_msg;
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	struct chip_data *chip = spi_get_ctldata(message->spi);
	u32 dma_thresh = chip->dma_threshold;
	u32 dma_burst = chip->dma_burst_size;
	u32 change_mask = pxa2xx_spi_get_ssrc1_change_mask(drv_data);
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	u32 clk_div;
	u8 bits;
	u32 speed;
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	u32 cr0;
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	u32 cr1;
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	int err;
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	int dma_mapped;
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940
	/* Check if we can DMA this transfer */
941
	if (transfer->len > MAX_DMA_LEN && chip->enable_dma) {
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		/* reject already-mapped transfers; PIO won't always work */
		if (message->is_dma_mapped
				|| transfer->rx_dma || transfer->tx_dma) {
			dev_err(&drv_data->pdev->dev,
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				"Mapped transfer length of %u is greater than %d\n",
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				transfer->len, MAX_DMA_LEN);
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			return -EINVAL;
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		}

		/* warn ... we force this to PIO mode */
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		dev_warn_ratelimited(&message->spi->dev,
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				     "DMA disabled for transfer length %ld greater than %d\n",
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				     (long)transfer->len, MAX_DMA_LEN);
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	}

958
	/* Setup the transfer state based on the type of transfer */
959
	if (pxa2xx_spi_flush(drv_data) == 0) {
960
		dev_err(&drv_data->pdev->dev, "Flush failed\n");
961
		return -EIO;
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	}
963
	drv_data->n_bytes = chip->n_bytes;
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	drv_data->tx = (void *)transfer->tx_buf;
	drv_data->tx_end = drv_data->tx + transfer->len;
	drv_data->rx = transfer->rx_buf;
	drv_data->rx_end = drv_data->rx + transfer->len;
	drv_data->write = drv_data->tx ? chip->write : null_writer;
	drv_data->read = drv_data->rx ? chip->read : null_reader;
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	/* Change speed and bit per word on a per transfer */
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	bits = transfer->bits_per_word;
	speed = transfer->speed_hz;

975
	clk_div = pxa2xx_ssp_get_clk_div(drv_data, speed);
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	if (bits <= 8) {
		drv_data->n_bytes = 1;
		drv_data->read = drv_data->read != null_reader ?
					u8_reader : null_reader;
		drv_data->write = drv_data->write != null_writer ?
					u8_writer : null_writer;
	} else if (bits <= 16) {
		drv_data->n_bytes = 2;
		drv_data->read = drv_data->read != null_reader ?
					u16_reader : null_reader;
		drv_data->write = drv_data->write != null_writer ?
					u16_writer : null_writer;
	} else if (bits <= 32) {
		drv_data->n_bytes = 4;
		drv_data->read = drv_data->read != null_reader ?
					u32_reader : null_reader;
		drv_data->write = drv_data->write != null_writer ?
					u32_writer : null_writer;
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	}
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	/*
	 * if bits/word is changed in dma mode, then must check the
	 * thresholds and burst also
	 */
	if (chip->enable_dma) {
		if (pxa2xx_spi_set_dma_burst_and_threshold(chip,
						message->spi,
						bits, &dma_burst,
						&dma_thresh))
			dev_warn_ratelimited(&message->spi->dev,
1006
					     "DMA burst size reduced to match bits_per_word\n");
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	}

1009 1010 1011
	dma_mapped = controller->can_dma &&
		     controller->can_dma(controller, message->spi, transfer) &&
		     controller->cur_msg_mapped;
1012
	if (dma_mapped) {
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		/* Ensure we have the correct interrupt handler */
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		drv_data->transfer_handler = pxa2xx_spi_dma_transfer;

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		err = pxa2xx_spi_dma_prepare(drv_data, transfer);
		if (err)
			return err;
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1021 1022
		/* Clear status and start DMA engine */
		cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1;
1023
		pxa2xx_spi_write(drv_data, SSSR, drv_data->clear_sr);
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		pxa2xx_spi_dma_start(drv_data);
1026 1027 1028 1029
	} else {
		/* Ensure we have the correct interrupt handler	*/
		drv_data->transfer_handler = interrupt_transfer;

1030 1031
		/* Clear status  */
		cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1;
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		write_SSSR_CS(drv_data, drv_data->clear_sr);
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	}

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	/* NOTE:  PXA25x_SSP _could_ use external clocking ... */
	cr0 = pxa2xx_configure_sscr0(drv_data, clk_div, bits);
	if (!pxa25x_ssp_comp(drv_data))
		dev_dbg(&message->spi->dev, "%u Hz actual, %s\n",
1039
			controller->max_speed_hz
1040
				/ (1 + ((cr0 & SSCR0_SCR(0xfff)) >> 8)),
1041
			dma_mapped ? "DMA" : "PIO");
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	else
		dev_dbg(&message->spi->dev, "%u Hz actual, %s\n",
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			controller->max_speed_hz / 2
1045
				/ (1 + ((cr0 & SSCR0_SCR(0x0ff)) >> 8)),
1046
			dma_mapped ? "DMA" : "PIO");
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1048
	if (is_lpss_ssp(drv_data)) {
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		if ((pxa2xx_spi_read(drv_data, SSIRF) & 0xff)
		    != chip->lpss_rx_threshold)
			pxa2xx_spi_write(drv_data, SSIRF,
					 chip->lpss_rx_threshold);
		if ((pxa2xx_spi_read(drv_data, SSITF) & 0xffff)
		    != chip->lpss_tx_threshold)
			pxa2xx_spi_write(drv_data, SSITF,
					 chip->lpss_tx_threshold);
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	}

1059
	if (is_quark_x1000_ssp(drv_data) &&
1060 1061
	    (pxa2xx_spi_read(drv_data, DDS_RATE) != chip->dds_rate))
		pxa2xx_spi_write(drv_data, DDS_RATE, chip->dds_rate);
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1063
	/* see if we need to reload the config registers */
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	if ((pxa2xx_spi_read(drv_data, SSCR0) != cr0)
	    || (pxa2xx_spi_read(drv_data, SSCR1) & change_mask)
	    != (cr1 & change_mask)) {
1067
		/* stop the SSP, and update the other bits */
1068
		pxa2xx_spi_write(drv_data, SSCR0, cr0 & ~SSCR0_SSE);
1069
		if (!pxa25x_ssp_comp(drv_data))
1070
			pxa2xx_spi_write(drv_data, SSTO, chip->timeout);
1071
		/* first set CR1 without interrupt and service enables */
1072
		pxa2xx_spi_write(drv_data, SSCR1, cr1 & change_mask);
1073
		/* restart the SSP */
1074
		pxa2xx_spi_write(drv_data, SSCR0, cr0);
1075

1076
	} else {
1077
		if (!pxa25x_ssp_comp(drv_data))
1078
			pxa2xx_spi_write(drv_data, SSTO, chip->timeout);
1079
	}
1080

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	if (drv_data->ssp_type == MMP2_SSP) {
		u8 tx_level = (pxa2xx_spi_read(drv_data, SSSR)
					& SSSR_TFL_MASK) >> 8;

		if (tx_level) {
			/* On MMP2, flipping SSE doesn't to empty TXFIFO. */
			dev_warn(&spi->dev, "%d bytes of garbage in TXFIFO!\n",
								tx_level);
			if (tx_level > transfer->len)
				tx_level = transfer->len;
			drv_data->tx += tx_level;
		}
	}

1095
	if (spi_controller_is_slave(controller)) {
1096 1097
		while (drv_data->write(drv_data))
			;
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		if (drv_data->gpiod_ready) {
			gpiod_set_value(drv_data->gpiod_ready, 1);
			udelay(1);
			gpiod_set_value(drv_data->gpiod_ready, 0);
		}
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	}

1105 1106 1107 1108
	/*
	 * Release the data by enabling service requests and interrupts,
	 * without changing any mode bits
	 */
1109
	pxa2xx_spi_write(drv_data, SSCR1, cr1);
1110 1111

	return 1;
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}

1114
static int pxa2xx_spi_slave_abort(struct spi_controller *controller)
1115
{
1116
	struct driver_data *drv_data = spi_controller_get_devdata(controller);
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	/* Stop and reset SSP */
	write_SSSR_CS(drv_data, drv_data->clear_sr);
	reset_sccr1(drv_data);
	if (!pxa25x_ssp_comp(drv_data))
		pxa2xx_spi_write(drv_data, SSTO, 0);
	pxa2xx_spi_flush(drv_data);
	pxa2xx_spi_write(drv_data, SSCR0,
			 pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);

	dev_dbg(&drv_data->pdev->dev, "transfer aborted\n");

1129 1130
	drv_data->controller->cur_msg->status = -EINTR;
	spi_finalize_current_transfer(drv_data->controller);
1131 1132 1133 1134

	return 0;
}

1135
static void pxa2xx_spi_handle_err(struct spi_controller *controller,
1136
				 struct spi_message *msg)
1137
{
1138
	struct driver_data *drv_data = spi_controller_get_devdata(controller);
1139

1140 1141 1142 1143 1144 1145 1146 1147 1148 1149
	/* Disable the SSP */
	pxa2xx_spi_write(drv_data, SSCR0,
			 pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
	/* Clear and disable interrupts and service requests */
	write_SSSR_CS(drv_data, drv_data->clear_sr);
	pxa2xx_spi_write(drv_data, SSCR1,
			 pxa2xx_spi_read(drv_data, SSCR1)
			 & ~(drv_data->int_cr1 | drv_data->dma_cr1));
	if (!pxa25x_ssp_comp(drv_data))
		pxa2xx_spi_write(drv_data, SSTO, 0);
1150

1151 1152 1153 1154 1155 1156 1157 1158 1159
	/*
	 * Stop the DMA if running. Note DMA callback handler may have unset
	 * the dma_running already, which is fine as stopping is not needed
	 * then but we shouldn't rely this flag for anything else than
	 * stopping. For instance to differentiate between PIO and DMA
	 * transfers.
	 */
	if (atomic_read(&drv_data->dma_running))
		pxa2xx_spi_dma_stop(drv_data);
1160 1161
}

1162
static int pxa2xx_spi_unprepare_transfer(struct spi_controller *controller)
1163
{
1164
	struct driver_data *drv_data = spi_controller_get_devdata(controller);
1165 1166

	/* Disable the SSP now */
1167 1168
	pxa2xx_spi_write(drv_data, SSCR0,
			 pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
1169 1170 1171 1172

	return 0;
}

1173 1174 1175
static int setup_cs(struct spi_device *spi, struct chip_data *chip,
		    struct pxa2xx_spi_chip *chip_info)
{
1176 1177
	struct driver_data *drv_data =
		spi_controller_get_devdata(spi->controller);
1178
	struct gpio_desc *gpiod;
1179 1180
	int err = 0;

1181 1182 1183
	if (chip == NULL)
		return 0;

1184 1185 1186
	if (drv_data->cs_gpiods) {
		gpiod = drv_data->cs_gpiods[spi->chip_select];
		if (gpiod) {
1187
			chip->gpiod_cs = gpiod;
1188 1189
			chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH;
			gpiod_set_value(gpiod, chip->gpio_cs_inverted);
1190 1191 1192 1193 1194 1195
		}

		return 0;
	}

	if (chip_info == NULL)
1196 1197 1198 1199 1200
		return 0;

	/* NOTE: setup() can be called multiple times, possibly with
	 * different chip_info, release previously requested GPIO
	 */
1201
	if (chip->gpiod_cs) {
1202
		gpiod_put(chip->gpiod_cs);
1203 1204
		chip->gpiod_cs = NULL;
	}
1205 1206 1207 1208 1209 1210 1211 1212 1213 1214

	/* If (*cs_control) is provided, ignore GPIO chip select */
	if (chip_info->cs_control) {
		chip->cs_control = chip_info->cs_control;
		return 0;
	}

	if (gpio_is_valid(chip_info->gpio_cs)) {
		err = gpio_request(chip_info->gpio_cs, "SPI_CS");
		if (err) {
1215 1216
			dev_err(&spi->dev, "failed to request chip select GPIO%d\n",
				chip_info->gpio_cs);
1217 1218 1219
			return err;
		}

1220 1221
		gpiod = gpio_to_desc(chip_info->gpio_cs);
		chip->gpiod_cs = gpiod;
1222 1223
		chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH;

1224
		err = gpiod_direction_output(gpiod, !chip->gpio_cs_inverted);
1225 1226 1227 1228 1229
	}

	return err;
}

1230 1231
static int setup(struct spi_device *spi)
{
1232
	struct pxa2xx_spi_chip *chip_info;
1233
	struct chip_data *chip;
1234
	const struct lpss_config *config;
1235 1236
	struct driver_data *drv_data =
		spi_controller_get_devdata(spi->controller);
1237 1238
	uint tx_thres, tx_hi_thres, rx_thres;

1239 1240 1241 1242 1243 1244
	switch (drv_data->ssp_type) {
	case QUARK_X1000_SSP:
		tx_thres = TX_THRESH_QUARK_X1000_DFLT;
		tx_hi_thres = 0;
		rx_thres = RX_THRESH_QUARK_X1000_DFLT;
		break;
1245 1246 1247 1248 1249
	case CE4100_SSP:
		tx_thres = TX_THRESH_CE4100_DFLT;
		tx_hi_thres = 0;
		rx_thres = RX_THRESH_CE4100_DFLT;
		break;
1250 1251
	case LPSS_LPT_SSP:
	case LPSS_BYT_SSP:
1252
	case LPSS_BSW_SSP:
1253
	case LPSS_SPT_SSP:
1254
	case LPSS_BXT_SSP:
1255
	case LPSS_CNL_SSP:
1256 1257 1258 1259
		config = lpss_get_config(drv_data);
		tx_thres = config->tx_threshold_lo;
		tx_hi_thres = config->tx_threshold_hi;
		rx_thres = config->rx_threshold;
1260 1261
		break;
	default:
1262
		tx_hi_thres = 0;
1263
		if (spi_controller_is_slave(drv_data->controller)) {
1264 1265 1266 1267 1268 1269
			tx_thres = 1;
			rx_thres = 2;
		} else {
			tx_thres = TX_THRESH_DFLT;
			rx_thres = RX_THRESH_DFLT;
		}
1270
		break;
1271
	}
1272

1273
	/* Only alloc on first setup */
1274
	chip = spi_get_ctldata(spi);
1275
	if (!chip) {
1276
		chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1277
		if (!chip)
1278 1279
			return -ENOMEM;

1280 1281
		if (drv_data->ssp_type == CE4100_SSP) {
			if (spi->chip_select > 4) {
1282 1283
				dev_err(&spi->dev,
					"failed setup: cs number must not be > 4.\n");
1284 1285 1286 1287 1288
				kfree(chip);
				return -EINVAL;
			}

			chip->frm = spi->chip_select;
1289
		}
1290
		chip->enable_dma = drv_data->controller_info->enable_dma;
1291
		chip->timeout = TIMOUT_DFLT;
1292 1293
	}

1294 1295 1296 1297
	/* protocol drivers may change the chip settings, so...
	 * if chip_info exists, use it */
	chip_info = spi->controller_data;

1298
	/* chip_info isn't always needed */
1299
	chip->cr1 = 0;
1300
	if (chip_info) {
1301 1302 1303 1304
		if (chip_info->timeout)
			chip->timeout = chip_info->timeout;
		if (chip_info->tx_threshold)
			tx_thres = chip_info->tx_threshold;
1305 1306
		if (chip_info->tx_hi_threshold)
			tx_hi_thres = chip_info->tx_hi_threshold;
1307 1308
		if (chip_info->rx_threshold)
			rx_thres = chip_info->rx_threshold;
1309 1310 1311 1312
		chip->dma_threshold = 0;
		if (chip_info->enable_loopback)
			chip->cr1 = SSCR1_LBM;
	}
1313
	if (spi_controller_is_slave(drv_data->controller)) {
1314 1315 1316 1317 1318
		chip->cr1 |= SSCR1_SCFR;
		chip->cr1 |= SSCR1_SCLKDIR;
		chip->cr1 |= SSCR1_SFRMDIR;
		chip->cr1 |= SSCR1_SPH;
	}
1319

1320 1321 1322 1323
	chip->lpss_rx_threshold = SSIRF_RxThresh(rx_thres);
	chip->lpss_tx_threshold = SSITF_TxLoThresh(tx_thres)
				| SSITF_TxHiThresh(tx_hi_thres);

1324 1325 1326 1327 1328
	/* set dma burst and threshold outside of chip_info path so that if
	 * chip_info goes away after setting chip->enable_dma, the
	 * burst and threshold can still respond to changes in bits_per_word */
	if (chip->enable_dma) {
		/* set up legal burst and threshold for dma */
1329 1330
		if (pxa2xx_spi_set_dma_burst_and_threshold(chip, spi,
						spi->bits_per_word,
1331 1332
						&chip->dma_burst_size,
						&chip->dma_threshold)) {
1333 1334
			dev_warn(&spi->dev,
				 "in setup: DMA burst size reduced to match bits_per_word\n");
1335
		}
1336 1337 1338
		dev_dbg(&spi->dev,
			"in setup: DMA burst size set to %u\n",
			chip->dma_burst_size);
1339 1340
	}

1341 1342 1343 1344 1345 1346 1347
	switch (drv_data->ssp_type) {
	case QUARK_X1000_SSP:
		chip->threshold = (QUARK_X1000_SSCR1_RxTresh(rx_thres)
				   & QUARK_X1000_SSCR1_RFT)
				   | (QUARK_X1000_SSCR1_TxTresh(tx_thres)
				   & QUARK_X1000_SSCR1_TFT);
		break;
1348 1349 1350 1351
	case CE4100_SSP:
		chip->threshold = (CE4100_SSCR1_RxTresh(rx_thres) & CE4100_SSCR1_RFT) |
			(CE4100_SSCR1_TxTresh(tx_thres) & CE4100_SSCR1_TFT);
		break;
1352 1353 1354 1355 1356 1357
	default:
		chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) |
			(SSCR1_TxTresh(tx_thres) & SSCR1_TFT);
		break;
	}

1358 1359 1360
	chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH);
	chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0)
			| (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0);
1361

1362 1363 1364
	if (spi->mode & SPI_LOOP)
		chip->cr1 |= SSCR1_LBM;

1365 1366 1367 1368 1369 1370 1371 1372 1373 1374 1375 1376 1377 1378 1379 1380
	if (spi->bits_per_word <= 8) {
		chip->n_bytes = 1;
		chip->read = u8_reader;
		chip->write = u8_writer;
	} else if (spi->bits_per_word <= 16) {
		chip->n_bytes = 2;
		chip->read = u16_reader;
		chip->write = u16_writer;
	} else if (spi->bits_per_word <= 32) {
		chip->n_bytes = 4;
		chip->read = u32_reader;
		chip->write = u32_writer;
	}

	spi_set_ctldata(spi, chip);

1381 1382 1383
	if (drv_data->ssp_type == CE4100_SSP)
		return 0;

1384
	return setup_cs(spi, chip, chip_info);
1385 1386
}

1387
static void cleanup(struct spi_device *spi)
1388
{
1389
	struct chip_data *chip = spi_get_ctldata(spi);
1390 1391
	struct driver_data *drv_data =
		spi_controller_get_devdata(spi->controller);
1392

1393 1394 1395
	if (!chip)
		return;

1396
	if (drv_data->ssp_type != CE4100_SSP && !drv_data->cs_gpiods &&
1397
	    chip->gpiod_cs)
1398
		gpiod_put(chip->gpiod_cs);
1399

1400 1401 1402
	kfree(chip);
}

1403
static const struct acpi_device_id pxa2xx_spi_acpi_match[] = {
1404 1405 1406 1407 1408
	{ "INT33C0", LPSS_LPT_SSP },
	{ "INT33C1", LPSS_LPT_SSP },
	{ "INT3430", LPSS_LPT_SSP },
	{ "INT3431", LPSS_LPT_SSP },
	{ "80860F0E", LPSS_BYT_SSP },
1409
	{ "8086228E", LPSS_BSW_SSP },
1410 1411 1412 1413
	{ },
};
MODULE_DEVICE_TABLE(acpi, pxa2xx_spi_acpi_match);

1414 1415 1416 1417 1418 1419 1420 1421 1422 1423 1424 1425
/*
 * PCI IDs of compound devices that integrate both host controller and private
 * integrated DMA engine. Please note these are not used in module
 * autoloading and probing in this module but matching the LPSS SSP type.
 */
static const struct pci_device_id pxa2xx_spi_pci_compound_match[] = {
	/* SPT-LP */
	{ PCI_VDEVICE(INTEL, 0x9d29), LPSS_SPT_SSP },
	{ PCI_VDEVICE(INTEL, 0x9d2a), LPSS_SPT_SSP },
	/* SPT-H */
	{ PCI_VDEVICE(INTEL, 0xa129), LPSS_SPT_SSP },
	{ PCI_VDEVICE(INTEL, 0xa12a), LPSS_SPT_SSP },
1426 1427 1428
	/* KBL-H */
	{ PCI_VDEVICE(INTEL, 0xa2a9), LPSS_SPT_SSP },
	{ PCI_VDEVICE(INTEL, 0xa2aa), LPSS_SPT_SSP },
1429
	/* BXT A-Step */
1430 1431 1432
	{ PCI_VDEVICE(INTEL, 0x0ac2), LPSS_BXT_SSP },
	{ PCI_VDEVICE(INTEL, 0x0ac4), LPSS_BXT_SSP },
	{ PCI_VDEVICE(INTEL, 0x0ac6), LPSS_BXT_SSP },
1433 1434 1435 1436
	/* BXT B-Step */
	{ PCI_VDEVICE(INTEL, 0x1ac2), LPSS_BXT_SSP },
	{ PCI_VDEVICE(INTEL, 0x1ac4), LPSS_BXT_SSP },
	{ PCI_VDEVICE(INTEL, 0x1ac6), LPSS_BXT_SSP },
1437 1438 1439 1440
	/* GLK */
	{ PCI_VDEVICE(INTEL, 0x31c2), LPSS_BXT_SSP },
	{ PCI_VDEVICE(INTEL, 0x31c4), LPSS_BXT_SSP },
	{ PCI_VDEVICE(INTEL, 0x31c6), LPSS_BXT_SSP },
1441 1442 1443 1444
	/* ICL-LP */
	{ PCI_VDEVICE(INTEL, 0x34aa), LPSS_CNL_SSP },
	{ PCI_VDEVICE(INTEL, 0x34ab), LPSS_CNL_SSP },
	{ PCI_VDEVICE(INTEL, 0x34fb), LPSS_CNL_SSP },
1445 1446 1447 1448
	/* APL */
	{ PCI_VDEVICE(INTEL, 0x5ac2), LPSS_BXT_SSP },
	{ PCI_VDEVICE(INTEL, 0x5ac4), LPSS_BXT_SSP },
	{ PCI_VDEVICE(INTEL, 0x5ac6), LPSS_BXT_SSP },
1449 1450 1451 1452 1453 1454 1455 1456
	/* CNL-LP */
	{ PCI_VDEVICE(INTEL, 0x9daa), LPSS_CNL_SSP },
	{ PCI_VDEVICE(INTEL, 0x9dab), LPSS_CNL_SSP },
	{ PCI_VDEVICE(INTEL, 0x9dfb), LPSS_CNL_SSP },
	/* CNL-H */
	{ PCI_VDEVICE(INTEL, 0xa32a), LPSS_CNL_SSP },
	{ PCI_VDEVICE(INTEL, 0xa32b), LPSS_CNL_SSP },
	{ PCI_VDEVICE(INTEL, 0xa37b), LPSS_CNL_SSP },
1457
	{ },
1458 1459
};

1460 1461 1462 1463 1464 1465 1466 1467 1468 1469 1470 1471 1472 1473 1474 1475 1476 1477 1478 1479 1480 1481 1482 1483 1484 1485 1486 1487 1488 1489 1490
static const struct of_device_id pxa2xx_spi_of_match[] = {
	{ .compatible = "marvell,mmp2-ssp", .data = (void *)MMP2_SSP },
	{},
};
MODULE_DEVICE_TABLE(of, pxa2xx_spi_of_match);

#ifdef CONFIG_ACPI

static int pxa2xx_spi_get_port_id(struct acpi_device *adev)
{
	unsigned int devid;
	int port_id = -1;

	if (adev && adev->pnp.unique_id &&
	    !kstrtouint(adev->pnp.unique_id, 0, &devid))
		port_id = devid;
	return port_id;
}

#else /* !CONFIG_ACPI */

static int pxa2xx_spi_get_port_id(struct acpi_device *adev)
{
	return -1;
}

#endif /* CONFIG_ACPI */


#ifdef CONFIG_PCI

1491 1492 1493 1494 1495 1496 1497 1498 1499 1500
static bool pxa2xx_spi_idma_filter(struct dma_chan *chan, void *param)
{
	struct device *dev = param;

	if (dev != chan->device->dev->parent)
		return false;

	return true;
}

1501 1502
#endif /* CONFIG_PCI */

1503
static struct pxa2xx_spi_controller *
1504
pxa2xx_spi_init_pdata(struct platform_device *pdev)
1505
{
1506
	struct pxa2xx_spi_controller *pdata;
1507 1508 1509
	struct acpi_device *adev;
	struct ssp_device *ssp;
	struct resource *res;
1510 1511
	const struct acpi_device_id *adev_id = NULL;
	const struct pci_device_id *pcidev_id = NULL;
1512
	const struct of_device_id *of_id = NULL;
1513
	enum pxa_ssp_type type;
1514

1515
	adev = ACPI_COMPANION(&pdev->dev);
1516

1517 1518 1519 1520
	if (pdev->dev.of_node)
		of_id = of_match_device(pdev->dev.driver->of_match_table,
					&pdev->dev);
	else if (dev_is_pci(pdev->dev.parent))
1521 1522
		pcidev_id = pci_match_id(pxa2xx_spi_pci_compound_match,
					 to_pci_dev(pdev->dev.parent));
1523
	else if (adev)
1524 1525
		adev_id = acpi_match_device(pdev->dev.driver->acpi_match_table,
					    &pdev->dev);
1526 1527
	else
		return NULL;
1528 1529

	if (adev_id)
1530
		type = (enum pxa_ssp_type)adev_id->driver_data;
1531
	else if (pcidev_id)
1532
		type = (enum pxa_ssp_type)pcidev_id->driver_data;
1533 1534
	else if (of_id)
		type = (enum pxa_ssp_type)of_id->data;
1535 1536 1537
	else
		return NULL;

1538
	pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1539
	if (!pdata)
1540 1541 1542 1543 1544 1545 1546 1547 1548
		return NULL;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!res)
		return NULL;

	ssp = &pdata->ssp;

	ssp->phys_base = res->start;
1549 1550
	ssp->mmio_base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(ssp->mmio_base))
1551
		return NULL;
1552

1553
#ifdef CONFIG_PCI
1554 1555 1556 1557 1558
	if (pcidev_id) {
		pdata->tx_param = pdev->dev.parent;
		pdata->rx_param = pdev->dev.parent;
		pdata->dma_filter = pxa2xx_spi_idma_filter;
	}
1559
#endif
1560

1561 1562
	ssp->clk = devm_clk_get(&pdev->dev, NULL);
	ssp->irq = platform_get_irq(pdev, 0);
1563
	ssp->type = type;
1564
	ssp->pdev = pdev;
1565
	ssp->port_id = pxa2xx_spi_get_port_id(adev);
1566

1567
	pdata->is_slave = of_property_read_bool(pdev->dev.of_node, "spi-slave");
1568
	pdata->num_chipselect = 1;
1569
	pdata->enable_dma = true;
1570
	pdata->dma_burst_size = 1;
1571 1572 1573 1574

	return pdata;
}

1575
static int pxa2xx_spi_fw_translate_cs(struct spi_controller *controller,
1576
				      unsigned int cs)
1577
{
1578
	struct driver_data *drv_data = spi_controller_get_devdata(controller);
1579 1580 1581 1582 1583 1584 1585 1586 1587

	if (has_acpi_companion(&drv_data->pdev->dev)) {
		switch (drv_data->ssp_type) {
		/*
		 * For Atoms the ACPI DeviceSelection used by the Windows
		 * driver starts from 1 instead of 0 so translate it here
		 * to match what Linux expects.
		 */
		case LPSS_BYT_SSP:
1588
		case LPSS_BSW_SSP:
1589 1590 1591 1592 1593 1594 1595 1596 1597 1598
			return cs - 1;

		default:
			break;
		}
	}

	return cs;
}

1599
static int pxa2xx_spi_probe(struct platform_device *pdev)
1600 1601
{
	struct device *dev = &pdev->dev;
1602 1603
	struct pxa2xx_spi_controller *platform_info;
	struct spi_controller *controller;
1604
	struct driver_data *drv_data;
1605
	struct ssp_device *ssp;
1606
	const struct lpss_config *config;
1607
	int status, count;
1608
	u32 tmp;
1609

1610 1611
	platform_info = dev_get_platdata(dev);
	if (!platform_info) {
1612
		platform_info = pxa2xx_spi_init_pdata(pdev);
1613 1614 1615 1616
		if (!platform_info) {
			dev_err(&pdev->dev, "missing platform data\n");
			return -ENODEV;
		}
1617
	}
1618

1619
	ssp = pxa_ssp_request(pdev->id, pdev->name);
1620 1621 1622 1623 1624
	if (!ssp)
		ssp = &platform_info->ssp;

	if (!ssp->mmio_base) {
		dev_err(&pdev->dev, "failed to get ssp\n");
1625 1626 1627
		return -ENODEV;
	}

1628
	if (platform_info->is_slave)
1629
		controller = spi_alloc_slave(dev, sizeof(struct driver_data));
1630
	else
1631
		controller = spi_alloc_master(dev, sizeof(struct driver_data));
1632

1633 1634
	if (!controller) {
		dev_err(&pdev->dev, "cannot alloc spi_controller\n");
1635
		pxa_ssp_free(ssp);
1636 1637
		return -ENOMEM;
	}
1638 1639 1640
	drv_data = spi_controller_get_devdata(controller);
	drv_data->controller = controller;
	drv_data->controller_info = platform_info;
1641
	drv_data->pdev = pdev;
1642
	drv_data->ssp = ssp;
1643

1644
	controller->dev.of_node = pdev->dev.of_node;
1645
	/* the spi->mode bits understood by this driver: */
1646 1647 1648 1649 1650 1651 1652 1653 1654 1655 1656 1657 1658 1659
	controller->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;

	controller->bus_num = ssp->port_id;
	controller->dma_alignment = DMA_ALIGNMENT;
	controller->cleanup = cleanup;
	controller->setup = setup;
	controller->set_cs = pxa2xx_spi_set_cs;
	controller->transfer_one = pxa2xx_spi_transfer_one;
	controller->slave_abort = pxa2xx_spi_slave_abort;
	controller->handle_err = pxa2xx_spi_handle_err;
	controller->unprepare_transfer_hardware = pxa2xx_spi_unprepare_transfer;
	controller->fw_translate_cs = pxa2xx_spi_fw_translate_cs;
	controller->auto_runtime_pm = true;
	controller->flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX;
1660

1661
	drv_data->ssp_type = ssp->type;
1662

1663 1664
	drv_data->ioaddr = ssp->mmio_base;
	drv_data->ssdr_physical = ssp->phys_base + SSDR;
1665
	if (pxa25x_ssp_comp(drv_data)) {
1666 1667
		switch (drv_data->ssp_type) {
		case QUARK_X1000_SSP:
1668
			controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1669 1670
			break;
		default:
1671
			controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
1672 1673 1674
			break;
		}

1675 1676 1677 1678 1679
		drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE;
		drv_data->dma_cr1 = 0;
		drv_data->clear_sr = SSSR_ROR;
		drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR;
	} else {
1680
		controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1681
		drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE;
1682
		drv_data->dma_cr1 = DEFAULT_DMA_CR1;
1683
		drv_data->clear_sr = SSSR_ROR | SSSR_TINT;
1684 1685
		drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS
						| SSSR_ROR | SSSR_TUR;
1686 1687
	}

1688 1689
	status = request_irq(ssp->irq, ssp_int, IRQF_SHARED, dev_name(dev),
			drv_data);
1690
	if (status < 0) {
1691
		dev_err(&pdev->dev, "cannot get IRQ %d\n", ssp->irq);
1692
		goto out_error_controller_alloc;
1693 1694 1695 1696
	}

	/* Setup DMA if requested */
	if (platform_info->enable_dma) {
1697 1698
		status = pxa2xx_spi_dma_setup(drv_data);
		if (status) {
1699
			dev_dbg(dev, "no DMA channels available, using PIO\n");
1700
			platform_info->enable_dma = false;
1701
		} else {
1702
			controller->can_dma = pxa2xx_spi_can_dma;
1703
			controller->max_dma_len = MAX_DMA_LEN;
1704 1705 1706 1707
		}
	}

	/* Enable SOC clock */
1708 1709 1710
	status = clk_prepare_enable(ssp->clk);
	if (status)
		goto out_error_dma_irq_alloc;
1711

1712
	controller->max_speed_hz = clk_get_rate(ssp->clk);
1713 1714

	/* Load default SSP configuration */
1715
	pxa2xx_spi_write(drv_data, SSCR0, 0);
1716 1717
	switch (drv_data->ssp_type) {
	case QUARK_X1000_SSP:
1718 1719
		tmp = QUARK_X1000_SSCR1_RxTresh(RX_THRESH_QUARK_X1000_DFLT) |
		      QUARK_X1000_SSCR1_TxTresh(TX_THRESH_QUARK_X1000_DFLT);
1720
		pxa2xx_spi_write(drv_data, SSCR1, tmp);
1721 1722

		/* using the Motorola SPI protocol and use 8 bit frame */
1723 1724
		tmp = QUARK_X1000_SSCR0_Motorola | QUARK_X1000_SSCR0_DataSize(8);
		pxa2xx_spi_write(drv_data, SSCR0, tmp);
1725
		break;
1726 1727 1728 1729 1730 1731
	case CE4100_SSP:
		tmp = CE4100_SSCR1_RxTresh(RX_THRESH_CE4100_DFLT) |
		      CE4100_SSCR1_TxTresh(TX_THRESH_CE4100_DFLT);
		pxa2xx_spi_write(drv_data, SSCR1, tmp);
		tmp = SSCR0_SCR(2) | SSCR0_Motorola | SSCR0_DataSize(8);
		pxa2xx_spi_write(drv_data, SSCR0, tmp);
1732
		break;
1733
	default:
1734

1735
		if (spi_controller_is_slave(controller)) {
1736 1737 1738 1739 1740 1741 1742 1743 1744 1745
			tmp = SSCR1_SCFR |
			      SSCR1_SCLKDIR |
			      SSCR1_SFRMDIR |
			      SSCR1_RxTresh(2) |
			      SSCR1_TxTresh(1) |
			      SSCR1_SPH;
		} else {
			tmp = SSCR1_RxTresh(RX_THRESH_DFLT) |
			      SSCR1_TxTresh(TX_THRESH_DFLT);
		}
1746
		pxa2xx_spi_write(drv_data, SSCR1, tmp);
1747
		tmp = SSCR0_Motorola | SSCR0_DataSize(8);
1748
		if (!spi_controller_is_slave(controller))
1749
			tmp |= SSCR0_SCR(2);
1750
		pxa2xx_spi_write(drv_data, SSCR0, tmp);
1751 1752 1753
		break;
	}

1754
	if (!pxa25x_ssp_comp(drv_data))
1755
		pxa2xx_spi_write(drv_data, SSTO, 0);
1756 1757

	if (!is_quark_x1000_ssp(drv_data))
1758
		pxa2xx_spi_write(drv_data, SSPSP, 0);
1759

1760 1761 1762 1763 1764 1765 1766 1767 1768
	if (is_lpss_ssp(drv_data)) {
		lpss_ssp_setup(drv_data);
		config = lpss_get_config(drv_data);
		if (config->reg_capabilities >= 0) {
			tmp = __lpss_ssp_read_priv(drv_data,
						   config->reg_capabilities);
			tmp &= LPSS_CAPS_CS_EN_MASK;
			tmp >>= LPSS_CAPS_CS_EN_SHIFT;
			platform_info->num_chipselect = ffz(tmp);
1769 1770
		} else if (config->cs_num) {
			platform_info->num_chipselect = config->cs_num;
1771 1772
		}
	}
1773
	controller->num_chipselect = platform_info->num_chipselect;
1774

1775
	count = gpiod_count(&pdev->dev, "cs");
1776 1777 1778
	if (count > 0) {
		int i;

1779 1780
		controller->num_chipselect = max_t(int, count,
			controller->num_chipselect);
1781

1782
		drv_data->cs_gpiods = devm_kcalloc(&pdev->dev,
1783
			controller->num_chipselect, sizeof(struct gpio_desc *),
1784 1785 1786 1787 1788 1789
			GFP_KERNEL);
		if (!drv_data->cs_gpiods) {
			status = -ENOMEM;
			goto out_error_clock_enabled;
		}

1790
		for (i = 0; i < controller->num_chipselect; i++) {
1791 1792
			struct gpio_desc *gpiod;

1793
			gpiod = devm_gpiod_get_index(dev, "cs", i, GPIOD_ASIS);
1794 1795 1796 1797 1798
			if (IS_ERR(gpiod)) {
				/* Means use native chip select */
				if (PTR_ERR(gpiod) == -ENOENT)
					continue;

1799
				status = PTR_ERR(gpiod);
1800 1801 1802 1803 1804 1805 1806
				goto out_error_clock_enabled;
			} else {
				drv_data->cs_gpiods[i] = gpiod;
			}
		}
	}

1807 1808 1809 1810 1811 1812 1813 1814 1815
	if (platform_info->is_slave) {
		drv_data->gpiod_ready = devm_gpiod_get_optional(dev,
						"ready", GPIOD_OUT_LOW);
		if (IS_ERR(drv_data->gpiod_ready)) {
			status = PTR_ERR(drv_data->gpiod_ready);
			goto out_error_clock_enabled;
		}
	}

1816 1817 1818 1819 1820
	pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
	pm_runtime_use_autosuspend(&pdev->dev);
	pm_runtime_set_active(&pdev->dev);
	pm_runtime_enable(&pdev->dev);

1821 1822
	/* Register with the SPI framework */
	platform_set_drvdata(pdev, drv_data);
1823
	status = devm_spi_register_controller(&pdev->dev, controller);
1824
	if (status != 0) {
1825
		dev_err(&pdev->dev, "problem registering spi controller\n");
1826
		goto out_error_clock_enabled;
1827 1828 1829 1830 1831
	}

	return status;

out_error_clock_enabled:
1832 1833
	pm_runtime_put_noidle(&pdev->dev);
	pm_runtime_disable(&pdev->dev);
1834
	clk_disable_unprepare(ssp->clk);
1835 1836

out_error_dma_irq_alloc:
1837
	pxa2xx_spi_dma_release(drv_data);
1838
	free_irq(ssp->irq, drv_data);
1839

1840 1841
out_error_controller_alloc:
	spi_controller_put(controller);
1842
	pxa_ssp_free(ssp);
1843 1844 1845 1846 1847 1848
	return status;
}

static int pxa2xx_spi_remove(struct platform_device *pdev)
{
	struct driver_data *drv_data = platform_get_drvdata(pdev);
1849
	struct ssp_device *ssp;
1850 1851 1852

	if (!drv_data)
		return 0;
1853
	ssp = drv_data->ssp;
1854

1855 1856
	pm_runtime_get_sync(&pdev->dev);

1857
	/* Disable the SSP at the peripheral and SOC level */
1858
	pxa2xx_spi_write(drv_data, SSCR0, 0);
1859
	clk_disable_unprepare(ssp->clk);
1860 1861

	/* Release DMA */
1862
	if (drv_data->controller_info->enable_dma)
1863
		pxa2xx_spi_dma_release(drv_data);
1864

1865 1866 1867
	pm_runtime_put_noidle(&pdev->dev);
	pm_runtime_disable(&pdev->dev);

1868
	/* Release IRQ */
1869 1870 1871
	free_irq(ssp->irq, drv_data);

	/* Release SSP */
1872
	pxa_ssp_free(ssp);
1873 1874 1875 1876

	return 0;
}

1877
#ifdef CONFIG_PM_SLEEP
1878
static int pxa2xx_spi_suspend(struct device *dev)
1879
{
1880
	struct driver_data *drv_data = dev_get_drvdata(dev);
1881
	struct ssp_device *ssp = drv_data->ssp;
1882
	int status;
1883

1884
	status = spi_controller_suspend(drv_data->controller);
1885 1886
	if (status != 0)
		return status;
1887
	pxa2xx_spi_write(drv_data, SSCR0, 0);
1888 1889 1890

	if (!pm_runtime_suspended(dev))
		clk_disable_unprepare(ssp->clk);
1891 1892 1893 1894

	return 0;
}

1895
static int pxa2xx_spi_resume(struct device *dev)
1896
{
1897
	struct driver_data *drv_data = dev_get_drvdata(dev);
1898
	struct ssp_device *ssp = drv_data->ssp;
1899
	int status;
1900 1901

	/* Enable the SSP clock */
1902 1903 1904 1905 1906
	if (!pm_runtime_suspended(dev)) {
		status = clk_prepare_enable(ssp->clk);
		if (status)
			return status;
	}
1907 1908

	/* Start the queue running */
1909
	return spi_controller_resume(drv_data->controller);
1910
}
1911 1912
#endif

1913
#ifdef CONFIG_PM
1914 1915 1916 1917 1918 1919 1920 1921 1922 1923 1924
static int pxa2xx_spi_runtime_suspend(struct device *dev)
{
	struct driver_data *drv_data = dev_get_drvdata(dev);

	clk_disable_unprepare(drv_data->ssp->clk);
	return 0;
}

static int pxa2xx_spi_runtime_resume(struct device *dev)
{
	struct driver_data *drv_data = dev_get_drvdata(dev);
1925
	int status;
1926

1927 1928
	status = clk_prepare_enable(drv_data->ssp->clk);
	return status;
1929 1930
}
#endif
1931

1932
static const struct dev_pm_ops pxa2xx_spi_pm_ops = {
1933 1934 1935
	SET_SYSTEM_SLEEP_PM_OPS(pxa2xx_spi_suspend, pxa2xx_spi_resume)
	SET_RUNTIME_PM_OPS(pxa2xx_spi_runtime_suspend,
			   pxa2xx_spi_runtime_resume, NULL)
1936
};
1937 1938 1939

static struct platform_driver driver = {
	.driver = {
1940 1941
		.name	= "pxa2xx-spi",
		.pm	= &pxa2xx_spi_pm_ops,
1942
		.acpi_match_table = ACPI_PTR(pxa2xx_spi_acpi_match),
1943
		.of_match_table = of_match_ptr(pxa2xx_spi_of_match),
1944
	},
1945
	.probe = pxa2xx_spi_probe,
1946
	.remove = pxa2xx_spi_remove,
1947 1948 1949 1950
};

static int __init pxa2xx_spi_init(void)
{
1951
	return platform_driver_register(&driver);
1952
}
1953
subsys_initcall(pxa2xx_spi_init);
1954 1955 1956 1957 1958 1959

static void __exit pxa2xx_spi_exit(void)
{
	platform_driver_unregister(&driver);
}
module_exit(pxa2xx_spi_exit);