i915_debugfs.c 135 KB
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/*
 * Copyright © 2008 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 * Authors:
 *    Eric Anholt <eric@anholt.net>
 *    Keith Packard <keithp@keithp.com>
 *
 */

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#include <linux/debugfs.h>
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#include <linux/sort.h>
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#include <linux/sched/mm.h>
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#include "intel_drv.h"
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#include "intel_guc_submission.h"
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static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node)
{
	return to_i915(node->minor->dev);
}

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static int i915_capabilities(struct seq_file *m, void *data)
{
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	struct drm_i915_private *dev_priv = node_to_i915(m->private);
	const struct intel_device_info *info = INTEL_INFO(dev_priv);
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	struct drm_printer p = drm_seq_file_printer(m);
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	seq_printf(m, "gen: %d\n", INTEL_GEN(dev_priv));
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	seq_printf(m, "platform: %s\n", intel_platform_name(info->platform));
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	seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev_priv));
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	intel_device_info_dump_flags(info, &p);
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	intel_device_info_dump_runtime(info, &p);
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	intel_driver_caps_print(&dev_priv->caps, &p);
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	kernel_param_lock(THIS_MODULE);
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	i915_params_dump(&i915_modparams, &p);
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	kernel_param_unlock(THIS_MODULE);

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	return 0;
}
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static char get_active_flag(struct drm_i915_gem_object *obj)
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{
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	return i915_gem_object_is_active(obj) ? '*' : ' ';
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}

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static char get_pin_flag(struct drm_i915_gem_object *obj)
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{
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	return obj->pin_global ? 'p' : ' ';
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}

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static char get_tiling_flag(struct drm_i915_gem_object *obj)
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{
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	switch (i915_gem_object_get_tiling(obj)) {
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	default:
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	case I915_TILING_NONE: return ' ';
	case I915_TILING_X: return 'X';
	case I915_TILING_Y: return 'Y';
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	}
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}

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static char get_global_flag(struct drm_i915_gem_object *obj)
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{
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	return obj->userfault_count ? 'g' : ' ';
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}

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static char get_pin_mapped_flag(struct drm_i915_gem_object *obj)
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{
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	return obj->mm.mapping ? 'M' : ' ';
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}

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static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj)
{
	u64 size = 0;
	struct i915_vma *vma;

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	for_each_ggtt_vma(vma, obj) {
		if (drm_mm_node_allocated(&vma->node))
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			size += vma->node.size;
	}

	return size;
}

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static const char *
stringify_page_sizes(unsigned int page_sizes, char *buf, size_t len)
{
	size_t x = 0;

	switch (page_sizes) {
	case 0:
		return "";
	case I915_GTT_PAGE_SIZE_4K:
		return "4K";
	case I915_GTT_PAGE_SIZE_64K:
		return "64K";
	case I915_GTT_PAGE_SIZE_2M:
		return "2M";
	default:
		if (!buf)
			return "M";

		if (page_sizes & I915_GTT_PAGE_SIZE_2M)
			x += snprintf(buf + x, len - x, "2M, ");
		if (page_sizes & I915_GTT_PAGE_SIZE_64K)
			x += snprintf(buf + x, len - x, "64K, ");
		if (page_sizes & I915_GTT_PAGE_SIZE_4K)
			x += snprintf(buf + x, len - x, "4K, ");
		buf[x-2] = '\0';

		return buf;
	}
}

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static void
describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
{
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	struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
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	struct intel_engine_cs *engine;
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	struct i915_vma *vma;
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	unsigned int frontbuffer_bits;
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	int pin_count = 0;

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	lockdep_assert_held(&obj->base.dev->struct_mutex);

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	seq_printf(m, "%pK: %c%c%c%c%c %8zdKiB %02x %02x %s%s%s",
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		   &obj->base,
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		   get_active_flag(obj),
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		   get_pin_flag(obj),
		   get_tiling_flag(obj),
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		   get_global_flag(obj),
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		   get_pin_mapped_flag(obj),
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		   obj->base.size / 1024,
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		   obj->read_domains,
		   obj->write_domain,
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		   i915_cache_level_str(dev_priv, obj->cache_level),
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		   obj->mm.dirty ? " dirty" : "",
		   obj->mm.madv == I915_MADV_DONTNEED ? " purgeable" : "");
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	if (obj->base.name)
		seq_printf(m, " (name: %d)", obj->base.name);
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	list_for_each_entry(vma, &obj->vma_list, obj_link) {
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		if (i915_vma_is_pinned(vma))
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			pin_count++;
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	}
	seq_printf(m, " (pinned x %d)", pin_count);
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	if (obj->pin_global)
		seq_printf(m, " (global)");
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	list_for_each_entry(vma, &obj->vma_list, obj_link) {
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		if (!drm_mm_node_allocated(&vma->node))
			continue;

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		seq_printf(m, " (%sgtt offset: %08llx, size: %08llx, pages: %s",
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			   i915_vma_is_ggtt(vma) ? "g" : "pp",
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			   vma->node.start, vma->node.size,
			   stringify_page_sizes(vma->page_sizes.gtt, NULL, 0));
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		if (i915_vma_is_ggtt(vma)) {
			switch (vma->ggtt_view.type) {
			case I915_GGTT_VIEW_NORMAL:
				seq_puts(m, ", normal");
				break;

			case I915_GGTT_VIEW_PARTIAL:
				seq_printf(m, ", partial [%08llx+%x]",
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					   vma->ggtt_view.partial.offset << PAGE_SHIFT,
					   vma->ggtt_view.partial.size << PAGE_SHIFT);
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				break;

			case I915_GGTT_VIEW_ROTATED:
				seq_printf(m, ", rotated [(%ux%u, stride=%u, offset=%u), (%ux%u, stride=%u, offset=%u)]",
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					   vma->ggtt_view.rotated.plane[0].width,
					   vma->ggtt_view.rotated.plane[0].height,
					   vma->ggtt_view.rotated.plane[0].stride,
					   vma->ggtt_view.rotated.plane[0].offset,
					   vma->ggtt_view.rotated.plane[1].width,
					   vma->ggtt_view.rotated.plane[1].height,
					   vma->ggtt_view.rotated.plane[1].stride,
					   vma->ggtt_view.rotated.plane[1].offset);
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				break;

			default:
				MISSING_CASE(vma->ggtt_view.type);
				break;
			}
		}
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		if (vma->fence)
			seq_printf(m, " , fence: %d%s",
				   vma->fence->id,
				   i915_gem_active_isset(&vma->last_fence) ? "*" : "");
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		seq_puts(m, ")");
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	}
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	if (obj->stolen)
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		seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
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	engine = i915_gem_object_last_write_engine(obj);
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	if (engine)
		seq_printf(m, " (%s)", engine->name);

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	frontbuffer_bits = atomic_read(&obj->frontbuffer_bits);
	if (frontbuffer_bits)
		seq_printf(m, " (frontbuffer: 0x%03x)", frontbuffer_bits);
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}

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static int obj_rank_by_stolen(const void *A, const void *B)
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{
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	const struct drm_i915_gem_object *a =
		*(const struct drm_i915_gem_object **)A;
	const struct drm_i915_gem_object *b =
		*(const struct drm_i915_gem_object **)B;
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	if (a->stolen->start < b->stolen->start)
		return -1;
	if (a->stolen->start > b->stolen->start)
		return 1;
	return 0;
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}

static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
{
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	struct drm_i915_private *dev_priv = node_to_i915(m->private);
	struct drm_device *dev = &dev_priv->drm;
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	struct drm_i915_gem_object **objects;
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	struct drm_i915_gem_object *obj;
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	u64 total_obj_size, total_gtt_size;
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	unsigned long total, count, n;
	int ret;

	total = READ_ONCE(dev_priv->mm.object_count);
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	objects = kvmalloc_array(total, sizeof(*objects), GFP_KERNEL);
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	if (!objects)
		return -ENOMEM;
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	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
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		goto out;
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	total_obj_size = total_gtt_size = count = 0;
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	spin_lock(&dev_priv->mm.obj_lock);
	list_for_each_entry(obj, &dev_priv->mm.bound_list, mm.link) {
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		if (count == total)
			break;

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		if (obj->stolen == NULL)
			continue;

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		objects[count++] = obj;
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		total_obj_size += obj->base.size;
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		total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
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	}
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	list_for_each_entry(obj, &dev_priv->mm.unbound_list, mm.link) {
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		if (count == total)
			break;

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		if (obj->stolen == NULL)
			continue;

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		objects[count++] = obj;
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		total_obj_size += obj->base.size;
	}
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	spin_unlock(&dev_priv->mm.obj_lock);
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	sort(objects, count, sizeof(*objects), obj_rank_by_stolen, NULL);

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	seq_puts(m, "Stolen:\n");
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	for (n = 0; n < count; n++) {
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		seq_puts(m, "   ");
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		describe_obj(m, objects[n]);
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		seq_putc(m, '\n');
	}
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	seq_printf(m, "Total %lu objects, %llu bytes, %llu GTT size\n",
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		   count, total_obj_size, total_gtt_size);
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	mutex_unlock(&dev->struct_mutex);
out:
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	kvfree(objects);
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	return ret;
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}

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struct file_stats {
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	struct drm_i915_file_private *file_priv;
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	unsigned long count;
	u64 total, unbound;
	u64 global, shared;
	u64 active, inactive;
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};

static int per_file_stats(int id, void *ptr, void *data)
{
	struct drm_i915_gem_object *obj = ptr;
	struct file_stats *stats = data;
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	struct i915_vma *vma;
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	lockdep_assert_held(&obj->base.dev->struct_mutex);

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	stats->count++;
	stats->total += obj->base.size;
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	if (!obj->bind_count)
		stats->unbound += obj->base.size;
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	if (obj->base.name || obj->base.dma_buf)
		stats->shared += obj->base.size;

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	list_for_each_entry(vma, &obj->vma_list, obj_link) {
		if (!drm_mm_node_allocated(&vma->node))
			continue;
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		if (i915_vma_is_ggtt(vma)) {
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			stats->global += vma->node.size;
		} else {
			struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vma->vm);
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			if (ppgtt->vm.file != stats->file_priv)
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				continue;
		}
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		if (i915_vma_is_active(vma))
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			stats->active += vma->node.size;
		else
			stats->inactive += vma->node.size;
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	}

	return 0;
}

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#define print_file_stats(m, name, stats) do { \
	if (stats.count) \
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		seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \
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			   name, \
			   stats.count, \
			   stats.total, \
			   stats.active, \
			   stats.inactive, \
			   stats.global, \
			   stats.shared, \
			   stats.unbound); \
} while (0)
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static void print_batch_pool_stats(struct seq_file *m,
				   struct drm_i915_private *dev_priv)
{
	struct drm_i915_gem_object *obj;
	struct file_stats stats;
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	struct intel_engine_cs *engine;
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	enum intel_engine_id id;
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	int j;
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	memset(&stats, 0, sizeof(stats));

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	for_each_engine(engine, dev_priv, id) {
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		for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
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			list_for_each_entry(obj,
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					    &engine->batch_pool.cache_list[j],
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					    batch_pool_link)
				per_file_stats(0, obj, &stats);
		}
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	}
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	print_file_stats(m, "[k]batch pool", stats);
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}

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static int per_file_ctx_stats(int idx, void *ptr, void *data)
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{
	struct i915_gem_context *ctx = ptr;
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	struct intel_engine_cs *engine;
	enum intel_engine_id id;

	for_each_engine(engine, ctx->i915, id) {
		struct intel_context *ce = to_intel_context(ctx, engine);
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		if (ce->state)
			per_file_stats(0, ce->state->obj, data);
		if (ce->ring)
			per_file_stats(0, ce->ring->vma->obj, data);
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	}

	return 0;
}

static void print_context_stats(struct seq_file *m,
				struct drm_i915_private *dev_priv)
{
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	struct drm_device *dev = &dev_priv->drm;
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	struct file_stats stats;
	struct drm_file *file;

	memset(&stats, 0, sizeof(stats));

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	mutex_lock(&dev->struct_mutex);
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	if (dev_priv->kernel_context)
		per_file_ctx_stats(0, dev_priv->kernel_context, &stats);

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	list_for_each_entry(file, &dev->filelist, lhead) {
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		struct drm_i915_file_private *fpriv = file->driver_priv;
		idr_for_each(&fpriv->context_idr, per_file_ctx_stats, &stats);
	}
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	mutex_unlock(&dev->struct_mutex);
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	print_file_stats(m, "[k]contexts", stats);
}

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static int i915_gem_object_info(struct seq_file *m, void *data)
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{
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	struct drm_i915_private *dev_priv = node_to_i915(m->private);
	struct drm_device *dev = &dev_priv->drm;
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	struct i915_ggtt *ggtt = &dev_priv->ggtt;
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	u32 count, mapped_count, purgeable_count, dpy_count, huge_count;
	u64 size, mapped_size, purgeable_size, dpy_size, huge_size;
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	struct drm_i915_gem_object *obj;
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	unsigned int page_sizes = 0;
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	struct drm_file *file;
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	char buf[80];
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	int ret;

	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;

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	seq_printf(m, "%u objects, %llu bytes\n",
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		   dev_priv->mm.object_count,
		   dev_priv->mm.object_memory);

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	size = count = 0;
	mapped_size = mapped_count = 0;
	purgeable_size = purgeable_count = 0;
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	huge_size = huge_count = 0;
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	spin_lock(&dev_priv->mm.obj_lock);
	list_for_each_entry(obj, &dev_priv->mm.unbound_list, mm.link) {
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		size += obj->base.size;
		++count;

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		if (obj->mm.madv == I915_MADV_DONTNEED) {
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			purgeable_size += obj->base.size;
			++purgeable_count;
		}

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		if (obj->mm.mapping) {
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			mapped_count++;
			mapped_size += obj->base.size;
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		}
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		if (obj->mm.page_sizes.sg > I915_GTT_PAGE_SIZE) {
			huge_count++;
			huge_size += obj->base.size;
			page_sizes |= obj->mm.page_sizes.sg;
		}
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	}
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	seq_printf(m, "%u unbound objects, %llu bytes\n", count, size);
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	size = count = dpy_size = dpy_count = 0;
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	list_for_each_entry(obj, &dev_priv->mm.bound_list, mm.link) {
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		size += obj->base.size;
		++count;

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		if (obj->pin_global) {
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			dpy_size += obj->base.size;
			++dpy_count;
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		}
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		if (obj->mm.madv == I915_MADV_DONTNEED) {
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			purgeable_size += obj->base.size;
			++purgeable_count;
		}
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		if (obj->mm.mapping) {
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			mapped_count++;
			mapped_size += obj->base.size;
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		}
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		if (obj->mm.page_sizes.sg > I915_GTT_PAGE_SIZE) {
			huge_count++;
			huge_size += obj->base.size;
			page_sizes |= obj->mm.page_sizes.sg;
		}
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	}
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	spin_unlock(&dev_priv->mm.obj_lock);

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	seq_printf(m, "%u bound objects, %llu bytes\n",
		   count, size);
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	seq_printf(m, "%u purgeable objects, %llu bytes\n",
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		   purgeable_count, purgeable_size);
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	seq_printf(m, "%u mapped objects, %llu bytes\n",
		   mapped_count, mapped_size);
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	seq_printf(m, "%u huge-paged objects (%s) %llu bytes\n",
		   huge_count,
		   stringify_page_sizes(page_sizes, buf, sizeof(buf)),
		   huge_size);
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	seq_printf(m, "%u display objects (globally pinned), %llu bytes\n",
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		   dpy_count, dpy_size);
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	seq_printf(m, "%llu [%pa] gtt total\n",
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		   ggtt->vm.total, &ggtt->mappable_end);
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	seq_printf(m, "Supported page sizes: %s\n",
		   stringify_page_sizes(INTEL_INFO(dev_priv)->page_sizes,
					buf, sizeof(buf)));
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	seq_putc(m, '\n');
	print_batch_pool_stats(m, dev_priv);
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	mutex_unlock(&dev->struct_mutex);

	mutex_lock(&dev->filelist_mutex);
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	print_context_stats(m, dev_priv);
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	list_for_each_entry_reverse(file, &dev->filelist, lhead) {
		struct file_stats stats;
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		struct drm_i915_file_private *file_priv = file->driver_priv;
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		struct i915_request *request;
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		struct task_struct *task;
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		mutex_lock(&dev->struct_mutex);

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		memset(&stats, 0, sizeof(stats));
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		stats.file_priv = file->driver_priv;
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		spin_lock(&file->table_lock);
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		idr_for_each(&file->object_idr, per_file_stats, &stats);
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		spin_unlock(&file->table_lock);
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		/*
		 * Although we have a valid reference on file->pid, that does
		 * not guarantee that the task_struct who called get_pid() is
		 * still alive (e.g. get_pid(current) => fork() => exit()).
		 * Therefore, we need to protect this ->comm access using RCU.
		 */
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		request = list_first_entry_or_null(&file_priv->mm.request_list,
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						   struct i915_request,
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						   client_link);
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		rcu_read_lock();
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		task = pid_task(request && request->gem_context->pid ?
				request->gem_context->pid : file->pid,
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				PIDTYPE_PID);
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		print_file_stats(m, task ? task->comm : "<unknown>", stats);
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		rcu_read_unlock();
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		mutex_unlock(&dev->struct_mutex);
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	}
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	mutex_unlock(&dev->filelist_mutex);
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	return 0;
}

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static int i915_gem_gtt_info(struct seq_file *m, void *data)
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{
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	struct drm_info_node *node = m->private;
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	struct drm_i915_private *dev_priv = node_to_i915(node);
	struct drm_device *dev = &dev_priv->drm;
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	struct drm_i915_gem_object **objects;
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	struct drm_i915_gem_object *obj;
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	u64 total_obj_size, total_gtt_size;
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	unsigned long nobject, n;
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	int count, ret;

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	nobject = READ_ONCE(dev_priv->mm.object_count);
	objects = kvmalloc_array(nobject, sizeof(*objects), GFP_KERNEL);
	if (!objects)
		return -ENOMEM;

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	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;

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	count = 0;
	spin_lock(&dev_priv->mm.obj_lock);
	list_for_each_entry(obj, &dev_priv->mm.bound_list, mm.link) {
		objects[count++] = obj;
		if (count == nobject)
			break;
	}
	spin_unlock(&dev_priv->mm.obj_lock);

	total_obj_size = total_gtt_size = 0;
	for (n = 0;  n < count; n++) {
		obj = objects[n];

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		seq_puts(m, "   ");
592
		describe_obj(m, obj);
593
		seq_putc(m, '\n');
594
		total_obj_size += obj->base.size;
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		total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
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	}

	mutex_unlock(&dev->struct_mutex);

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	seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
601
		   count, total_obj_size, total_gtt_size);
602
	kvfree(objects);
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	return 0;
}

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static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
{
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	struct drm_i915_private *dev_priv = node_to_i915(m->private);
	struct drm_device *dev = &dev_priv->drm;
611
	struct drm_i915_gem_object *obj;
612
	struct intel_engine_cs *engine;
613
	enum intel_engine_id id;
614
	int total = 0;
615
	int ret, j;
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	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;

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	for_each_engine(engine, dev_priv, id) {
622
		for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
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			int count;

			count = 0;
			list_for_each_entry(obj,
627
					    &engine->batch_pool.cache_list[j],
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					    batch_pool_link)
				count++;
			seq_printf(m, "%s cache[%d]: %d objects\n",
631
				   engine->name, j, count);
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			list_for_each_entry(obj,
634
					    &engine->batch_pool.cache_list[j],
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					    batch_pool_link) {
				seq_puts(m, "   ");
				describe_obj(m, obj);
				seq_putc(m, '\n');
			}

			total += count;
642
		}
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	}

645
	seq_printf(m, "total: %d\n", total);
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	mutex_unlock(&dev->struct_mutex);

	return 0;
}

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static void gen8_display_interrupt_info(struct seq_file *m)
{
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
	int pipe;

	for_each_pipe(dev_priv, pipe) {
		enum intel_display_power_domain power_domain;

		power_domain = POWER_DOMAIN_PIPE(pipe);
		if (!intel_display_power_get_if_enabled(dev_priv,
							power_domain)) {
			seq_printf(m, "Pipe %c power disabled\n",
				   pipe_name(pipe));
			continue;
		}
		seq_printf(m, "Pipe %c IMR:\t%08x\n",
			   pipe_name(pipe),
			   I915_READ(GEN8_DE_PIPE_IMR(pipe)));
		seq_printf(m, "Pipe %c IIR:\t%08x\n",
			   pipe_name(pipe),
			   I915_READ(GEN8_DE_PIPE_IIR(pipe)));
		seq_printf(m, "Pipe %c IER:\t%08x\n",
			   pipe_name(pipe),
			   I915_READ(GEN8_DE_PIPE_IER(pipe)));

		intel_display_power_put(dev_priv, power_domain);
	}

	seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
		   I915_READ(GEN8_DE_PORT_IMR));
	seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
		   I915_READ(GEN8_DE_PORT_IIR));
	seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
		   I915_READ(GEN8_DE_PORT_IER));

	seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
		   I915_READ(GEN8_DE_MISC_IMR));
	seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
		   I915_READ(GEN8_DE_MISC_IIR));
	seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
		   I915_READ(GEN8_DE_MISC_IER));

	seq_printf(m, "PCU interrupt mask:\t%08x\n",
		   I915_READ(GEN8_PCU_IMR));
	seq_printf(m, "PCU interrupt identity:\t%08x\n",
		   I915_READ(GEN8_PCU_IIR));
	seq_printf(m, "PCU interrupt enable:\t%08x\n",
		   I915_READ(GEN8_PCU_IER));
}

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static int i915_interrupt_info(struct seq_file *m, void *data)
{
704
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
705
	struct intel_engine_cs *engine;
706
	enum intel_engine_id id;
707
	int i, pipe;
708

709
	intel_runtime_pm_get(dev_priv);
710

711
	if (IS_CHERRYVIEW(dev_priv)) {
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		seq_printf(m, "Master Interrupt Control:\t%08x\n",
			   I915_READ(GEN8_MASTER_IRQ));

		seq_printf(m, "Display IER:\t%08x\n",
			   I915_READ(VLV_IER));
		seq_printf(m, "Display IIR:\t%08x\n",
			   I915_READ(VLV_IIR));
		seq_printf(m, "Display IIR_RW:\t%08x\n",
			   I915_READ(VLV_IIR_RW));
		seq_printf(m, "Display IMR:\t%08x\n",
			   I915_READ(VLV_IMR));
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		for_each_pipe(dev_priv, pipe) {
			enum intel_display_power_domain power_domain;

			power_domain = POWER_DOMAIN_PIPE(pipe);
			if (!intel_display_power_get_if_enabled(dev_priv,
								power_domain)) {
				seq_printf(m, "Pipe %c power disabled\n",
					   pipe_name(pipe));
				continue;
			}

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			seq_printf(m, "Pipe %c stat:\t%08x\n",
				   pipe_name(pipe),
				   I915_READ(PIPESTAT(pipe)));

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			intel_display_power_put(dev_priv, power_domain);
		}

		intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
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		seq_printf(m, "Port hotplug:\t%08x\n",
			   I915_READ(PORT_HOTPLUG_EN));
		seq_printf(m, "DPFLIPSTAT:\t%08x\n",
			   I915_READ(VLV_DPFLIPSTAT));
		seq_printf(m, "DPINVGTT:\t%08x\n",
			   I915_READ(DPINVGTT));
748
		intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
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		for (i = 0; i < 4; i++) {
			seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
				   i, I915_READ(GEN8_GT_IMR(i)));
			seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
				   i, I915_READ(GEN8_GT_IIR(i)));
			seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
				   i, I915_READ(GEN8_GT_IER(i)));
		}

		seq_printf(m, "PCU interrupt mask:\t%08x\n",
			   I915_READ(GEN8_PCU_IMR));
		seq_printf(m, "PCU interrupt identity:\t%08x\n",
			   I915_READ(GEN8_PCU_IIR));
		seq_printf(m, "PCU interrupt enable:\t%08x\n",
			   I915_READ(GEN8_PCU_IER));
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	} else if (INTEL_GEN(dev_priv) >= 11) {
		seq_printf(m, "Master Interrupt Control:  %08x\n",
			   I915_READ(GEN11_GFX_MSTR_IRQ));

		seq_printf(m, "Render/Copy Intr Enable:   %08x\n",
			   I915_READ(GEN11_RENDER_COPY_INTR_ENABLE));
		seq_printf(m, "VCS/VECS Intr Enable:      %08x\n",
			   I915_READ(GEN11_VCS_VECS_INTR_ENABLE));
		seq_printf(m, "GUC/SG Intr Enable:\t   %08x\n",
			   I915_READ(GEN11_GUC_SG_INTR_ENABLE));
		seq_printf(m, "GPM/WGBOXPERF Intr Enable: %08x\n",
			   I915_READ(GEN11_GPM_WGBOXPERF_INTR_ENABLE));
		seq_printf(m, "Crypto Intr Enable:\t   %08x\n",
			   I915_READ(GEN11_CRYPTO_RSVD_INTR_ENABLE));
		seq_printf(m, "GUnit/CSME Intr Enable:\t   %08x\n",
			   I915_READ(GEN11_GUNIT_CSME_INTR_ENABLE));

		seq_printf(m, "Display Interrupt Control:\t%08x\n",
			   I915_READ(GEN11_DISPLAY_INT_CTL));

		gen8_display_interrupt_info(m);
786
	} else if (INTEL_GEN(dev_priv) >= 8) {
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		seq_printf(m, "Master Interrupt Control:\t%08x\n",
			   I915_READ(GEN8_MASTER_IRQ));

		for (i = 0; i < 4; i++) {
			seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
				   i, I915_READ(GEN8_GT_IMR(i)));
			seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
				   i, I915_READ(GEN8_GT_IIR(i)));
			seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
				   i, I915_READ(GEN8_GT_IER(i)));
		}

799
		gen8_display_interrupt_info(m);
800
	} else if (IS_VALLEYVIEW(dev_priv)) {
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		seq_printf(m, "Display IER:\t%08x\n",
			   I915_READ(VLV_IER));
		seq_printf(m, "Display IIR:\t%08x\n",
			   I915_READ(VLV_IIR));
		seq_printf(m, "Display IIR_RW:\t%08x\n",
			   I915_READ(VLV_IIR_RW));
		seq_printf(m, "Display IMR:\t%08x\n",
			   I915_READ(VLV_IMR));
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		for_each_pipe(dev_priv, pipe) {
			enum intel_display_power_domain power_domain;

			power_domain = POWER_DOMAIN_PIPE(pipe);
			if (!intel_display_power_get_if_enabled(dev_priv,
								power_domain)) {
				seq_printf(m, "Pipe %c power disabled\n",
					   pipe_name(pipe));
				continue;
			}

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			seq_printf(m, "Pipe %c stat:\t%08x\n",
				   pipe_name(pipe),
				   I915_READ(PIPESTAT(pipe)));
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			intel_display_power_put(dev_priv, power_domain);
		}
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		seq_printf(m, "Master IER:\t%08x\n",
			   I915_READ(VLV_MASTER_IER));

		seq_printf(m, "Render IER:\t%08x\n",
			   I915_READ(GTIER));
		seq_printf(m, "Render IIR:\t%08x\n",
			   I915_READ(GTIIR));
		seq_printf(m, "Render IMR:\t%08x\n",
			   I915_READ(GTIMR));

		seq_printf(m, "PM IER:\t\t%08x\n",
			   I915_READ(GEN6_PMIER));
		seq_printf(m, "PM IIR:\t\t%08x\n",
			   I915_READ(GEN6_PMIIR));
		seq_printf(m, "PM IMR:\t\t%08x\n",
			   I915_READ(GEN6_PMIMR));

		seq_printf(m, "Port hotplug:\t%08x\n",
			   I915_READ(PORT_HOTPLUG_EN));
		seq_printf(m, "DPFLIPSTAT:\t%08x\n",
			   I915_READ(VLV_DPFLIPSTAT));
		seq_printf(m, "DPINVGTT:\t%08x\n",
			   I915_READ(DPINVGTT));

850
	} else if (!HAS_PCH_SPLIT(dev_priv)) {
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		seq_printf(m, "Interrupt enable:    %08x\n",
			   I915_READ(IER));
		seq_printf(m, "Interrupt identity:  %08x\n",
			   I915_READ(IIR));
		seq_printf(m, "Interrupt mask:      %08x\n",
			   I915_READ(IMR));
857
		for_each_pipe(dev_priv, pipe)
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			seq_printf(m, "Pipe %c stat:         %08x\n",
				   pipe_name(pipe),
				   I915_READ(PIPESTAT(pipe)));
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	} else {
		seq_printf(m, "North Display Interrupt enable:		%08x\n",
			   I915_READ(DEIER));
		seq_printf(m, "North Display Interrupt identity:	%08x\n",
			   I915_READ(DEIIR));
		seq_printf(m, "North Display Interrupt mask:		%08x\n",
			   I915_READ(DEIMR));
		seq_printf(m, "South Display Interrupt enable:		%08x\n",
			   I915_READ(SDEIER));
		seq_printf(m, "South Display Interrupt identity:	%08x\n",
			   I915_READ(SDEIIR));
		seq_printf(m, "South Display Interrupt mask:		%08x\n",
			   I915_READ(SDEIMR));
		seq_printf(m, "Graphics Interrupt enable:		%08x\n",
			   I915_READ(GTIER));
		seq_printf(m, "Graphics Interrupt identity:		%08x\n",
			   I915_READ(GTIIR));
		seq_printf(m, "Graphics Interrupt mask:		%08x\n",
			   I915_READ(GTIMR));
	}
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	if (INTEL_GEN(dev_priv) >= 11) {
		seq_printf(m, "RCS Intr Mask:\t %08x\n",
			   I915_READ(GEN11_RCS0_RSVD_INTR_MASK));
		seq_printf(m, "BCS Intr Mask:\t %08x\n",
			   I915_READ(GEN11_BCS_RSVD_INTR_MASK));
		seq_printf(m, "VCS0/VCS1 Intr Mask:\t %08x\n",
			   I915_READ(GEN11_VCS0_VCS1_INTR_MASK));
		seq_printf(m, "VCS2/VCS3 Intr Mask:\t %08x\n",
			   I915_READ(GEN11_VCS2_VCS3_INTR_MASK));
		seq_printf(m, "VECS0/VECS1 Intr Mask:\t %08x\n",
			   I915_READ(GEN11_VECS0_VECS1_INTR_MASK));
		seq_printf(m, "GUC/SG Intr Mask:\t %08x\n",
			   I915_READ(GEN11_GUC_SG_INTR_MASK));
		seq_printf(m, "GPM/WGBOXPERF Intr Mask: %08x\n",
			   I915_READ(GEN11_GPM_WGBOXPERF_INTR_MASK));
		seq_printf(m, "Crypto Intr Mask:\t %08x\n",
			   I915_READ(GEN11_CRYPTO_RSVD_INTR_MASK));
		seq_printf(m, "Gunit/CSME Intr Mask:\t %08x\n",
			   I915_READ(GEN11_GUNIT_CSME_INTR_MASK));

	} else if (INTEL_GEN(dev_priv) >= 6) {
903
		for_each_engine(engine, dev_priv, id) {
904 905
			seq_printf(m,
				   "Graphics Interrupt mask (%s):	%08x\n",
906
				   engine->name, I915_READ_IMR(engine));
907 908
		}
	}
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910
	intel_runtime_pm_put(dev_priv);
911

912 913 914
	return 0;
}

915 916
static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
{
917 918
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
	struct drm_device *dev = &dev_priv->drm;
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	int i, ret;

	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;
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	seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
	for (i = 0; i < dev_priv->num_fence_regs; i++) {
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		struct i915_vma *vma = dev_priv->fence_regs[i].vma;
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Chris Wilson's avatar
Chris Wilson committed
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		seq_printf(m, "Fence %d, pin count = %d, object = ",
			   i, dev_priv->fence_regs[i].pin_count);
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		if (!vma)
932
			seq_puts(m, "unused");
933
		else
934
			describe_obj(m, vma->obj);
935
		seq_putc(m, '\n');
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	}

938
	mutex_unlock(&dev->struct_mutex);
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	return 0;
}

942
#if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
943 944
static ssize_t gpu_state_read(struct file *file, char __user *ubuf,
			      size_t count, loff_t *pos)
945
{
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	struct i915_gpu_state *error = file->private_data;
	struct drm_i915_error_state_buf str;
	ssize_t ret;
	loff_t tmp;
950

951 952
	if (!error)
		return 0;
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	ret = i915_error_state_buf_init(&str, error->i915, count, *pos);
	if (ret)
		return ret;
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	ret = i915_error_state_to_str(&str, error);
	if (ret)
		goto out;
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	tmp = 0;
	ret = simple_read_from_buffer(ubuf, count, &tmp, str.buf, str.bytes);
	if (ret < 0)
		goto out;
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	*pos = str.start + ret;
out:
	i915_error_state_buf_release(&str);
	return ret;
}
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static int gpu_state_release(struct inode *inode, struct file *file)
{
	i915_gpu_state_put(file->private_data);
976
	return 0;
977 978
}

979
static int i915_gpu_info_open(struct inode *inode, struct file *file)
980
{
981
	struct drm_i915_private *i915 = inode->i_private;
982
	struct i915_gpu_state *gpu;
983

984 985 986
	intel_runtime_pm_get(i915);
	gpu = i915_capture_gpu_state(i915);
	intel_runtime_pm_put(i915);
987 988
	if (!gpu)
		return -ENOMEM;
989

990
	file->private_data = gpu;
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	return 0;
}

994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006
static const struct file_operations i915_gpu_info_fops = {
	.owner = THIS_MODULE,
	.open = i915_gpu_info_open,
	.read = gpu_state_read,
	.llseek = default_llseek,
	.release = gpu_state_release,
};

static ssize_t
i915_error_state_write(struct file *filp,
		       const char __user *ubuf,
		       size_t cnt,
		       loff_t *ppos)
1007
{
1008
	struct i915_gpu_state *error = filp->private_data;
1009

1010 1011
	if (!error)
		return 0;
1012

1013 1014
	DRM_DEBUG_DRIVER("Resetting error state\n");
	i915_reset_error_state(error->i915);
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1016 1017
	return cnt;
}
1018

1019 1020 1021 1022
static int i915_error_state_open(struct inode *inode, struct file *file)
{
	file->private_data = i915_first_error_state(inode->i_private);
	return 0;
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}

static const struct file_operations i915_error_state_fops = {
	.owner = THIS_MODULE,
	.open = i915_error_state_open,
1028
	.read = gpu_state_read,
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	.write = i915_error_state_write,
	.llseek = default_llseek,
1031
	.release = gpu_state_release,
1032
};
1033 1034
#endif

1035 1036 1037
static int
i915_next_seqno_set(void *data, u64 val)
{
1038 1039
	struct drm_i915_private *dev_priv = data;
	struct drm_device *dev = &dev_priv->drm;
1040 1041 1042 1043 1044 1045
	int ret;

	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;

1046
	intel_runtime_pm_get(dev_priv);
1047
	ret = i915_gem_set_global_seqno(dev, val);
1048 1049
	intel_runtime_pm_put(dev_priv);

1050 1051
	mutex_unlock(&dev->struct_mutex);

1052
	return ret;
1053 1054
}

1055
DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1056
			NULL, i915_next_seqno_set,
1057
			"0x%llx\n");
1058

1059
static int i915_frequency_info(struct seq_file *m, void *unused)
1060
{
1061
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
1062
	struct intel_rps *rps = &dev_priv->gt_pm.rps;
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	int ret = 0;

	intel_runtime_pm_get(dev_priv);
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1067
	if (IS_GEN5(dev_priv)) {
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		u16 rgvswctl = I915_READ16(MEMSWCTL);
		u16 rgvstat = I915_READ16(MEMSTAT_ILK);

		seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
		seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
		seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
			   MEMSTAT_VID_SHIFT);
		seq_printf(m, "Current P-state: %d\n",
			   (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
1077
	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1078
		u32 rpmodectl, freq_sts;
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1080
		mutex_lock(&dev_priv->pcu_lock);
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		rpmodectl = I915_READ(GEN6_RP_CONTROL);
		seq_printf(m, "Video Turbo Mode: %s\n",
			   yesno(rpmodectl & GEN6_RP_MEDIA_TURBO));
		seq_printf(m, "HW control enabled: %s\n",
			   yesno(rpmodectl & GEN6_RP_ENABLE));
		seq_printf(m, "SW control enabled: %s\n",
			   yesno((rpmodectl & GEN6_RP_MEDIA_MODE_MASK) ==
				  GEN6_RP_MEDIA_SW_MODE));

1091 1092 1093 1094 1095 1096 1097 1098
		freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
		seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
		seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);

		seq_printf(m, "actual GPU freq: %d MHz\n",
			   intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));

		seq_printf(m, "current GPU freq: %d MHz\n",
1099
			   intel_gpu_freq(dev_priv, rps->cur_freq));
1100 1101

		seq_printf(m, "max GPU freq: %d MHz\n",
1102
			   intel_gpu_freq(dev_priv, rps->max_freq));
1103 1104

		seq_printf(m, "min GPU freq: %d MHz\n",
1105
			   intel_gpu_freq(dev_priv, rps->min_freq));
1106 1107

		seq_printf(m, "idle GPU freq: %d MHz\n",
1108
			   intel_gpu_freq(dev_priv, rps->idle_freq));
1109 1110 1111

		seq_printf(m,
			   "efficient (RPe) frequency: %d MHz\n",
1112
			   intel_gpu_freq(dev_priv, rps->efficient_freq));
1113
		mutex_unlock(&dev_priv->pcu_lock);
1114
	} else if (INTEL_GEN(dev_priv) >= 6) {
1115 1116 1117
		u32 rp_state_limits;
		u32 gt_perf_status;
		u32 rp_state_cap;
1118
		u32 rpmodectl, rpinclimit, rpdeclimit;
1119
		u32 rpstat, cagf, reqf;
1120 1121
		u32 rpupei, rpcurup, rpprevup;
		u32 rpdownei, rpcurdown, rpprevdown;
1122
		u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
1123 1124
		int max_freq;

1125
		rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1126
		if (IS_GEN9_LP(dev_priv)) {
1127 1128 1129 1130 1131 1132 1133
			rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
			gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);
		} else {
			rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
			gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
		}

1134
		/* RPSTAT1 is in the GT power well */
1135
		intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1136

1137
		reqf = I915_READ(GEN6_RPNSWREQ);
1138
		if (INTEL_GEN(dev_priv) >= 9)
1139 1140 1141
			reqf >>= 23;
		else {
			reqf &= ~GEN6_TURBO_DISABLE;
1142
			if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1143 1144 1145 1146
				reqf >>= 24;
			else
				reqf >>= 25;
		}
1147
		reqf = intel_gpu_freq(dev_priv, reqf);
1148

1149 1150 1151 1152
		rpmodectl = I915_READ(GEN6_RP_CONTROL);
		rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
		rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);

1153
		rpstat = I915_READ(GEN6_RPSTAT1);
1154 1155 1156 1157 1158 1159
		rpupei = I915_READ(GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK;
		rpcurup = I915_READ(GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK;
		rpprevup = I915_READ(GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK;
		rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK;
		rpcurdown = I915_READ(GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK;
		rpprevdown = I915_READ(GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK;
1160 1161
		cagf = intel_gpu_freq(dev_priv,
				      intel_get_cagf(dev_priv, rpstat));
1162

1163
		intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1164

1165 1166 1167 1168 1169 1170 1171 1172 1173 1174
		if (INTEL_GEN(dev_priv) >= 11) {
			pm_ier = I915_READ(GEN11_GPM_WGBOXPERF_INTR_ENABLE);
			pm_imr = I915_READ(GEN11_GPM_WGBOXPERF_INTR_MASK);
			/*
			 * The equivalent to the PM ISR & IIR cannot be read
			 * without affecting the current state of the system
			 */
			pm_isr = 0;
			pm_iir = 0;
		} else if (INTEL_GEN(dev_priv) >= 8) {
1175 1176 1177 1178
			pm_ier = I915_READ(GEN8_GT_IER(2));
			pm_imr = I915_READ(GEN8_GT_IMR(2));
			pm_isr = I915_READ(GEN8_GT_ISR(2));
			pm_iir = I915_READ(GEN8_GT_IIR(2));
1179 1180 1181 1182 1183
		} else {
			pm_ier = I915_READ(GEN6_PMIER);
			pm_imr = I915_READ(GEN6_PMIMR);
			pm_isr = I915_READ(GEN6_PMISR);
			pm_iir = I915_READ(GEN6_PMIIR);
1184
		}
1185 1186
		pm_mask = I915_READ(GEN6_PMINTRMSK);

1187 1188 1189 1190 1191 1192 1193
		seq_printf(m, "Video Turbo Mode: %s\n",
			   yesno(rpmodectl & GEN6_RP_MEDIA_TURBO));
		seq_printf(m, "HW control enabled: %s\n",
			   yesno(rpmodectl & GEN6_RP_ENABLE));
		seq_printf(m, "SW control enabled: %s\n",
			   yesno((rpmodectl & GEN6_RP_MEDIA_MODE_MASK) ==
				  GEN6_RP_MEDIA_SW_MODE));
1194 1195 1196 1197 1198 1199

		seq_printf(m, "PM IER=0x%08x IMR=0x%08x, MASK=0x%08x\n",
			   pm_ier, pm_imr, pm_mask);
		if (INTEL_GEN(dev_priv) <= 10)
			seq_printf(m, "PM ISR=0x%08x IIR=0x%08x\n",
				   pm_isr, pm_iir);
1200
		seq_printf(m, "pm_intrmsk_mbz: 0x%08x\n",
1201
			   rps->pm_intrmsk_mbz);
1202 1203
		seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
		seq_printf(m, "Render p-state ratio: %d\n",
1204
			   (gt_perf_status & (INTEL_GEN(dev_priv) >= 9 ? 0x1ff00 : 0xff00)) >> 8);
1205 1206 1207 1208
		seq_printf(m, "Render p-state VID: %d\n",
			   gt_perf_status & 0xff);
		seq_printf(m, "Render p-state limit: %d\n",
			   rp_state_limits & 0xff);
1209 1210 1211 1212
		seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
		seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
		seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
		seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
1213
		seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
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1214
		seq_printf(m, "CAGF: %dMHz\n", cagf);
1215 1216 1217 1218 1219 1220
		seq_printf(m, "RP CUR UP EI: %d (%dus)\n",
			   rpupei, GT_PM_INTERVAL_TO_US(dev_priv, rpupei));
		seq_printf(m, "RP CUR UP: %d (%dus)\n",
			   rpcurup, GT_PM_INTERVAL_TO_US(dev_priv, rpcurup));
		seq_printf(m, "RP PREV UP: %d (%dus)\n",
			   rpprevup, GT_PM_INTERVAL_TO_US(dev_priv, rpprevup));
1221 1222
		seq_printf(m, "Up threshold: %d%%\n",
			   rps->power.up_threshold);
1223

1224 1225 1226 1227 1228 1229
		seq_printf(m, "RP CUR DOWN EI: %d (%dus)\n",
			   rpdownei, GT_PM_INTERVAL_TO_US(dev_priv, rpdownei));
		seq_printf(m, "RP CUR DOWN: %d (%dus)\n",
			   rpcurdown, GT_PM_INTERVAL_TO_US(dev_priv, rpcurdown));
		seq_printf(m, "RP PREV DOWN: %d (%dus)\n",
			   rpprevdown, GT_PM_INTERVAL_TO_US(dev_priv, rpprevdown));
1230 1231
		seq_printf(m, "Down threshold: %d%%\n",
			   rps->power.down_threshold);
1232

1233
		max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 0 :
1234
			    rp_state_cap >> 16) & 0xff;
1235
		max_freq *= (IS_GEN9_BC(dev_priv) ||
1236
			     INTEL_GEN(dev_priv) >= 10 ? GEN9_FREQ_SCALER : 1);
1237
		seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
1238
			   intel_gpu_freq(dev_priv, max_freq));
1239 1240

		max_freq = (rp_state_cap & 0xff00) >> 8;
1241
		max_freq *= (IS_GEN9_BC(dev_priv) ||
1242
			     INTEL_GEN(dev_priv) >= 10 ? GEN9_FREQ_SCALER : 1);
1243
		seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
1244
			   intel_gpu_freq(dev_priv, max_freq));
1245

1246
		max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 16 :
1247
			    rp_state_cap >> 0) & 0xff;
1248
		max_freq *= (IS_GEN9_BC(dev_priv) ||
1249
			     INTEL_GEN(dev_priv) >= 10 ? GEN9_FREQ_SCALER : 1);
1250
		seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
1251
			   intel_gpu_freq(dev_priv, max_freq));
1252
		seq_printf(m, "Max overclocked frequency: %dMHz\n",
1253
			   intel_gpu_freq(dev_priv, rps->max_freq));
1254

1255
		seq_printf(m, "Current freq: %d MHz\n",
1256
			   intel_gpu_freq(dev_priv, rps->cur_freq));
1257
		seq_printf(m, "Actual freq: %d MHz\n", cagf);
1258
		seq_printf(m, "Idle freq: %d MHz\n",
1259
			   intel_gpu_freq(dev_priv, rps->idle_freq));
1260
		seq_printf(m, "Min freq: %d MHz\n",
1261
			   intel_gpu_freq(dev_priv, rps->min_freq));
1262
		seq_printf(m, "Boost freq: %d MHz\n",
1263
			   intel_gpu_freq(dev_priv, rps->boost_freq));
1264
		seq_printf(m, "Max freq: %d MHz\n",
1265
			   intel_gpu_freq(dev_priv, rps->max_freq));
1266 1267
		seq_printf(m,
			   "efficient (RPe) frequency: %d MHz\n",
1268
			   intel_gpu_freq(dev_priv, rps->efficient_freq));
1269
	} else {
1270
		seq_puts(m, "no P-state info available\n");
1271
	}
1272

1273
	seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk.hw.cdclk);
1274 1275 1276
	seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq);
	seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq);

1277 1278
	intel_runtime_pm_put(dev_priv);
	return ret;
1279 1280
}

1281 1282 1283 1284
static void i915_instdone_info(struct drm_i915_private *dev_priv,
			       struct seq_file *m,
			       struct intel_instdone *instdone)
{
1285 1286 1287
	int slice;
	int subslice;

1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299
	seq_printf(m, "\t\tINSTDONE: 0x%08x\n",
		   instdone->instdone);

	if (INTEL_GEN(dev_priv) <= 3)
		return;

	seq_printf(m, "\t\tSC_INSTDONE: 0x%08x\n",
		   instdone->slice_common);

	if (INTEL_GEN(dev_priv) <= 6)
		return;

1300 1301 1302 1303 1304 1305 1306
	for_each_instdone_slice_subslice(dev_priv, slice, subslice)
		seq_printf(m, "\t\tSAMPLER_INSTDONE[%d][%d]: 0x%08x\n",
			   slice, subslice, instdone->sampler[slice][subslice]);

	for_each_instdone_slice_subslice(dev_priv, slice, subslice)
		seq_printf(m, "\t\tROW_INSTDONE[%d][%d]: 0x%08x\n",
			   slice, subslice, instdone->row[slice][subslice]);
1307 1308
}

1309 1310
static int i915_hangcheck_info(struct seq_file *m, void *unused)
{
1311
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
1312
	struct intel_engine_cs *engine;
1313 1314
	u64 acthd[I915_NUM_ENGINES];
	u32 seqno[I915_NUM_ENGINES];
1315
	struct intel_instdone instdone;
1316
	enum intel_engine_id id;
1317

1318
	if (test_bit(I915_WEDGED, &dev_priv->gpu_error.flags))
1319 1320 1321 1322 1323
		seq_puts(m, "Wedged\n");
	if (test_bit(I915_RESET_BACKOFF, &dev_priv->gpu_error.flags))
		seq_puts(m, "Reset in progress: struct_mutex backoff\n");
	if (test_bit(I915_RESET_HANDOFF, &dev_priv->gpu_error.flags))
		seq_puts(m, "Reset in progress: reset handoff to waiter\n");
1324
	if (waitqueue_active(&dev_priv->gpu_error.wait_queue))
1325
		seq_puts(m, "Waiter holding struct mutex\n");
1326
	if (waitqueue_active(&dev_priv->gpu_error.reset_queue))
1327
		seq_puts(m, "struct_mutex blocked for reset\n");
1328

1329
	if (!i915_modparams.enable_hangcheck) {
1330
		seq_puts(m, "Hangcheck disabled\n");
1331 1332 1333
		return 0;
	}

1334 1335
	intel_runtime_pm_get(dev_priv);

1336
	for_each_engine(engine, dev_priv, id) {
1337
		acthd[id] = intel_engine_get_active_head(engine);
1338
		seqno[id] = intel_engine_get_seqno(engine);
1339 1340
	}

1341
	intel_engine_get_instdone(dev_priv->engine[RCS], &instdone);
1342

1343 1344
	intel_runtime_pm_put(dev_priv);

1345 1346
	if (timer_pending(&dev_priv->gpu_error.hangcheck_work.timer))
		seq_printf(m, "Hangcheck active, timer fires in %dms\n",
1347 1348
			   jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
					    jiffies));
1349 1350 1351 1352
	else if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work))
		seq_puts(m, "Hangcheck active, work pending\n");
	else
		seq_puts(m, "Hangcheck inactive\n");
1353

1354 1355
	seq_printf(m, "GT active? %s\n", yesno(dev_priv->gt.awake));

1356
	for_each_engine(engine, dev_priv, id) {
1357 1358 1359
		struct intel_breadcrumbs *b = &engine->breadcrumbs;
		struct rb_node *rb;

1360
		seq_printf(m, "%s:\n", engine->name);
1361
		seq_printf(m, "\tseqno = %x [current %x, last %x]\n",
1362
			   engine->hangcheck.seqno, seqno[id],
1363
			   intel_engine_last_submit(engine));
1364
		seq_printf(m, "\twaiters? %s, fake irq active? %s, stalled? %s, wedged? %s\n",
1365 1366
			   yesno(intel_engine_has_waiter(engine)),
			   yesno(test_bit(engine->id,
1367
					  &dev_priv->gpu_error.missed_irq_rings)),
1368 1369
			   yesno(engine->hangcheck.stalled),
			   yesno(engine->hangcheck.wedged));
1370

1371
		spin_lock_irq(&b->rb_lock);
1372
		for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
1373
			struct intel_wait *w = rb_entry(rb, typeof(*w), node);
1374 1375 1376 1377

			seq_printf(m, "\t%s [%d] waiting for %x\n",
				   w->tsk->comm, w->tsk->pid, w->seqno);
		}
1378
		spin_unlock_irq(&b->rb_lock);
1379

1380
		seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1381
			   (long long)engine->hangcheck.acthd,
1382
			   (long long)acthd[id]);
1383 1384 1385 1386 1387
		seq_printf(m, "\taction = %s(%d) %d ms ago\n",
			   hangcheck_action_to_str(engine->hangcheck.action),
			   engine->hangcheck.action,
			   jiffies_to_msecs(jiffies -
					    engine->hangcheck.action_timestamp));
1388

1389
		if (engine->id == RCS) {
1390
			seq_puts(m, "\tinstdone read =\n");
1391

1392
			i915_instdone_info(dev_priv, m, &instdone);
1393

1394
			seq_puts(m, "\tinstdone accu =\n");
1395

1396 1397
			i915_instdone_info(dev_priv, m,
					   &engine->hangcheck.instdone);
1398
		}
1399 1400 1401 1402 1403
	}

	return 0;
}

1404 1405 1406 1407 1408 1409 1410 1411 1412 1413 1414 1415 1416 1417 1418 1419 1420
static int i915_reset_info(struct seq_file *m, void *unused)
{
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
	struct i915_gpu_error *error = &dev_priv->gpu_error;
	struct intel_engine_cs *engine;
	enum intel_engine_id id;

	seq_printf(m, "full gpu reset = %u\n", i915_reset_count(error));

	for_each_engine(engine, dev_priv, id) {
		seq_printf(m, "%s = %u\n", engine->name,
			   i915_reset_engine_count(error, engine));
	}

	return 0;
}

1421
static int ironlake_drpc_info(struct seq_file *m)
1422
{
1423
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
1424 1425 1426 1427 1428 1429 1430
	u32 rgvmodectl, rstdbyctl;
	u16 crstandvid;

	rgvmodectl = I915_READ(MEMMODECTL);
	rstdbyctl = I915_READ(RSTDBYCTL);
	crstandvid = I915_READ16(CRSTANDVID);

1431
	seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN));
1432 1433 1434 1435
	seq_printf(m, "Boost freq: %d\n",
		   (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
		   MEMMODE_BOOST_FREQ_SHIFT);
	seq_printf(m, "HW control enabled: %s\n",
1436
		   yesno(rgvmodectl & MEMMODE_HWIDLE_EN));
1437
	seq_printf(m, "SW control enabled: %s\n",
1438
		   yesno(rgvmodectl & MEMMODE_SWMODE_EN));
1439
	seq_printf(m, "Gated voltage change: %s\n",
1440
		   yesno(rgvmodectl & MEMMODE_RCLK_GATE));
1441 1442
	seq_printf(m, "Starting frequency: P%d\n",
		   (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1443
	seq_printf(m, "Max P-state: P%d\n",
1444
		   (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1445 1446 1447 1448
	seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
	seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
	seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
	seq_printf(m, "Render standby enabled: %s\n",
1449
		   yesno(!(rstdbyctl & RCX_SW_EXIT)));
1450
	seq_puts(m, "Current RS state: ");
1451 1452
	switch (rstdbyctl & RSX_STATUS_MASK) {
	case RSX_STATUS_ON:
1453
		seq_puts(m, "on\n");
1454 1455
		break;
	case RSX_STATUS_RC1:
1456
		seq_puts(m, "RC1\n");
1457 1458
		break;
	case RSX_STATUS_RC1E:
1459
		seq_puts(m, "RC1E\n");
1460 1461
		break;
	case RSX_STATUS_RS1:
1462
		seq_puts(m, "RS1\n");
1463 1464
		break;
	case RSX_STATUS_RS2:
1465
		seq_puts(m, "RS2 (RC6)\n");
1466 1467
		break;
	case RSX_STATUS_RS3:
1468
		seq_puts(m, "RC3 (RC6+)\n");
1469 1470
		break;
	default:
1471
		seq_puts(m, "unknown\n");
1472 1473
		break;
	}
1474 1475 1476 1477

	return 0;
}

1478
static int i915_forcewake_domains(struct seq_file *m, void *data)
1479
{
1480
	struct drm_i915_private *i915 = node_to_i915(m->private);
1481
	struct intel_uncore_forcewake_domain *fw_domain;
1482
	unsigned int tmp;
1483

1484 1485 1486
	seq_printf(m, "user.bypass_count = %u\n",
		   i915->uncore.user_forcewake.count);

1487
	for_each_fw_domain(fw_domain, i915, tmp)
1488
		seq_printf(m, "%s.wake_count = %u\n",
1489
			   intel_uncore_forcewake_domain_to_str(fw_domain->id),
1490
			   READ_ONCE(fw_domain->wake_count));
1491

1492 1493 1494
	return 0;
}

1495 1496 1497 1498 1499 1500 1501 1502 1503 1504 1505
static void print_rc6_res(struct seq_file *m,
			  const char *title,
			  const i915_reg_t reg)
{
	struct drm_i915_private *dev_priv = node_to_i915(m->private);

	seq_printf(m, "%s %u (%llu us)\n",
		   title, I915_READ(reg),
		   intel_rc6_residency_us(dev_priv, reg));
}

1506 1507
static int vlv_drpc_info(struct seq_file *m)
{
1508
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
1509
	u32 rcctl1, pw_status;
1510

1511
	pw_status = I915_READ(VLV_GTLC_PW_STATUS);
1512 1513 1514 1515 1516 1517
	rcctl1 = I915_READ(GEN6_RC_CONTROL);

	seq_printf(m, "RC6 Enabled: %s\n",
		   yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
					GEN6_RC_CTL_EI_MODE(1))));
	seq_printf(m, "Render Power Well: %s\n",
1518
		   (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
1519
	seq_printf(m, "Media Power Well: %s\n",
1520
		   (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
1521

1522 1523
	print_rc6_res(m, "Render RC6 residency since boot:", VLV_GT_RENDER_RC6);
	print_rc6_res(m, "Media RC6 residency since boot:", VLV_GT_MEDIA_RC6);
1524

1525
	return i915_forcewake_domains(m, NULL);
1526 1527
}

1528 1529
static int gen6_drpc_info(struct seq_file *m)
{
1530
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
1531
	u32 gt_core_status, rcctl1, rc6vids = 0;
1532
	u32 gen9_powergate_enable = 0, gen9_powergate_status = 0;
1533

1534
	gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS);
1535
	trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
1536 1537

	rcctl1 = I915_READ(GEN6_RC_CONTROL);
1538
	if (INTEL_GEN(dev_priv) >= 9) {
1539 1540 1541
		gen9_powergate_enable = I915_READ(GEN9_PG_ENABLE);
		gen9_powergate_status = I915_READ(GEN9_PWRGT_DOMAIN_STATUS);
	}
1542

1543 1544 1545 1546 1547 1548
	if (INTEL_GEN(dev_priv) <= 7) {
		mutex_lock(&dev_priv->pcu_lock);
		sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS,
				       &rc6vids);
		mutex_unlock(&dev_priv->pcu_lock);
	}
1549

1550
	seq_printf(m, "RC1e Enabled: %s\n",
1551 1552 1553
		   yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
	seq_printf(m, "RC6 Enabled: %s\n",
		   yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1554
	if (INTEL_GEN(dev_priv) >= 9) {
1555 1556 1557 1558 1559
		seq_printf(m, "Render Well Gating Enabled: %s\n",
			yesno(gen9_powergate_enable & GEN9_RENDER_PG_ENABLE));
		seq_printf(m, "Media Well Gating Enabled: %s\n",
			yesno(gen9_powergate_enable & GEN9_MEDIA_PG_ENABLE));
	}
1560 1561 1562 1563
	seq_printf(m, "Deep RC6 Enabled: %s\n",
		   yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
	seq_printf(m, "Deepest RC6 Enabled: %s\n",
		   yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1564
	seq_puts(m, "Current RC state: ");
1565 1566 1567
	switch (gt_core_status & GEN6_RCn_MASK) {
	case GEN6_RC0:
		if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1568
			seq_puts(m, "Core Power Down\n");
1569
		else
1570
			seq_puts(m, "on\n");
1571 1572
		break;
	case GEN6_RC3:
1573
		seq_puts(m, "RC3\n");
1574 1575
		break;
	case GEN6_RC6:
1576
		seq_puts(m, "RC6\n");
1577 1578
		break;
	case GEN6_RC7:
1579
		seq_puts(m, "RC7\n");
1580 1581
		break;
	default:
1582
		seq_puts(m, "Unknown\n");
1583 1584 1585 1586 1587
		break;
	}

	seq_printf(m, "Core Power Down: %s\n",
		   yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1588
	if (INTEL_GEN(dev_priv) >= 9) {
1589 1590 1591 1592 1593 1594 1595
		seq_printf(m, "Render Power Well: %s\n",
			(gen9_powergate_status &
			 GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down");
		seq_printf(m, "Media Power Well: %s\n",
			(gen9_powergate_status &
			 GEN9_PWRGT_MEDIA_STATUS_MASK) ? "Up" : "Down");
	}
1596 1597

	/* Not exactly sure what this is */
1598 1599 1600 1601 1602
	print_rc6_res(m, "RC6 \"Locked to RPn\" residency since boot:",
		      GEN6_GT_GFX_RC6_LOCKED);
	print_rc6_res(m, "RC6 residency since boot:", GEN6_GT_GFX_RC6);
	print_rc6_res(m, "RC6+ residency since boot:", GEN6_GT_GFX_RC6p);
	print_rc6_res(m, "RC6++ residency since boot:", GEN6_GT_GFX_RC6pp);
1603

1604 1605 1606 1607 1608 1609 1610 1611 1612
	if (INTEL_GEN(dev_priv) <= 7) {
		seq_printf(m, "RC6   voltage: %dmV\n",
			   GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
		seq_printf(m, "RC6+  voltage: %dmV\n",
			   GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
		seq_printf(m, "RC6++ voltage: %dmV\n",
			   GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
	}

1613
	return i915_forcewake_domains(m, NULL);
1614 1615 1616 1617
}

static int i915_drpc_info(struct seq_file *m, void *unused)
{
1618
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
1619 1620 1621
	int err;

	intel_runtime_pm_get(dev_priv);
1622

1623
	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1624
		err = vlv_drpc_info(m);
1625
	else if (INTEL_GEN(dev_priv) >= 6)
1626
		err = gen6_drpc_info(m);
1627
	else
1628 1629 1630 1631 1632
		err = ironlake_drpc_info(m);

	intel_runtime_pm_put(dev_priv);

	return err;
1633 1634
}

1635 1636
static int i915_frontbuffer_tracking(struct seq_file *m, void *unused)
{
1637
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
1638 1639 1640 1641 1642 1643 1644 1645 1646 1647

	seq_printf(m, "FB tracking busy bits: 0x%08x\n",
		   dev_priv->fb_tracking.busy_bits);

	seq_printf(m, "FB tracking flip bits: 0x%08x\n",
		   dev_priv->fb_tracking.flip_bits);

	return 0;
}

1648 1649
static int i915_fbc_status(struct seq_file *m, void *unused)
{
1650
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
1651
	struct intel_fbc *fbc = &dev_priv->fbc;
1652

1653 1654
	if (!HAS_FBC(dev_priv))
		return -ENODEV;
1655

1656
	intel_runtime_pm_get(dev_priv);
1657
	mutex_lock(&fbc->lock);
1658

1659
	if (intel_fbc_is_active(dev_priv))
1660
		seq_puts(m, "FBC enabled\n");
1661
	else
1662 1663
		seq_printf(m, "FBC disabled: %s\n", fbc->no_fbc_reason);

1664 1665 1666 1667 1668 1669 1670 1671 1672 1673 1674 1675 1676 1677 1678 1679
	if (intel_fbc_is_active(dev_priv)) {
		u32 mask;

		if (INTEL_GEN(dev_priv) >= 8)
			mask = I915_READ(IVB_FBC_STATUS2) & BDW_FBC_COMP_SEG_MASK;
		else if (INTEL_GEN(dev_priv) >= 7)
			mask = I915_READ(IVB_FBC_STATUS2) & IVB_FBC_COMP_SEG_MASK;
		else if (INTEL_GEN(dev_priv) >= 5)
			mask = I915_READ(ILK_DPFC_STATUS) & ILK_DPFC_COMP_SEG_MASK;
		else if (IS_G4X(dev_priv))
			mask = I915_READ(DPFC_STATUS) & DPFC_COMP_SEG_MASK;
		else
			mask = I915_READ(FBC_STATUS) & (FBC_STAT_COMPRESSING |
							FBC_STAT_COMPRESSED);

		seq_printf(m, "Compressing: %s\n", yesno(mask));
1680
	}
1681

1682
	mutex_unlock(&fbc->lock);
1683 1684
	intel_runtime_pm_put(dev_priv);

1685 1686 1687
	return 0;
}

1688
static int i915_fbc_false_color_get(void *data, u64 *val)
1689
{
1690
	struct drm_i915_private *dev_priv = data;
1691

1692
	if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv))
1693 1694 1695 1696 1697 1698 1699
		return -ENODEV;

	*val = dev_priv->fbc.false_color;

	return 0;
}

1700
static int i915_fbc_false_color_set(void *data, u64 val)
1701
{
1702
	struct drm_i915_private *dev_priv = data;
1703 1704
	u32 reg;

1705
	if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv))
1706 1707
		return -ENODEV;

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1708
	mutex_lock(&dev_priv->fbc.lock);
1709 1710 1711 1712 1713 1714 1715 1716

	reg = I915_READ(ILK_DPFC_CONTROL);
	dev_priv->fbc.false_color = val;

	I915_WRITE(ILK_DPFC_CONTROL, val ?
		   (reg | FBC_CTL_FALSE_COLOR) :
		   (reg & ~FBC_CTL_FALSE_COLOR));

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1717
	mutex_unlock(&dev_priv->fbc.lock);
1718 1719 1720
	return 0;
}

1721 1722
DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_false_color_fops,
			i915_fbc_false_color_get, i915_fbc_false_color_set,
1723 1724
			"%llu\n");

1725 1726
static int i915_ips_status(struct seq_file *m, void *unused)
{
1727
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
1728

1729 1730
	if (!HAS_IPS(dev_priv))
		return -ENODEV;
1731

1732 1733
	intel_runtime_pm_get(dev_priv);

1734
	seq_printf(m, "Enabled by kernel parameter: %s\n",
1735
		   yesno(i915_modparams.enable_ips));
1736

1737
	if (INTEL_GEN(dev_priv) >= 8) {
1738 1739 1740 1741 1742 1743 1744
		seq_puts(m, "Currently: unknown\n");
	} else {
		if (I915_READ(IPS_CTL) & IPS_ENABLE)
			seq_puts(m, "Currently: enabled\n");
		else
			seq_puts(m, "Currently: disabled\n");
	}
1745

1746 1747
	intel_runtime_pm_put(dev_priv);

1748 1749 1750
	return 0;
}

1751 1752
static int i915_sr_status(struct seq_file *m, void *unused)
{
1753
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
1754 1755
	bool sr_enabled = false;

1756
	intel_runtime_pm_get(dev_priv);
1757
	intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
1758

1759 1760 1761
	if (INTEL_GEN(dev_priv) >= 9)
		/* no global SR status; inspect per-plane WM */;
	else if (HAS_PCH_SPLIT(dev_priv))
1762
		sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1763
	else if (IS_I965GM(dev_priv) || IS_G4X(dev_priv) ||
1764
		 IS_I945G(dev_priv) || IS_I945GM(dev_priv))
1765
		sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1766
	else if (IS_I915GM(dev_priv))
1767
		sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1768
	else if (IS_PINEVIEW(dev_priv))
1769
		sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1770
	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1771
		sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
1772

1773
	intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
1774 1775
	intel_runtime_pm_put(dev_priv);

1776
	seq_printf(m, "self-refresh: %s\n", enableddisabled(sr_enabled));
1777 1778 1779 1780

	return 0;
}

1781 1782
static int i915_emon_status(struct seq_file *m, void *unused)
{
1783 1784
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
	struct drm_device *dev = &dev_priv->drm;
1785
	unsigned long temp, chipset, gfx;
1786 1787
	int ret;

1788
	if (!IS_GEN5(dev_priv))
1789 1790
		return -ENODEV;

1791 1792 1793
	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;
1794 1795 1796 1797

	temp = i915_mch_val(dev_priv);
	chipset = i915_chipset_val(dev_priv);
	gfx = i915_gfx_val(dev_priv);
1798
	mutex_unlock(&dev->struct_mutex);
1799 1800 1801 1802 1803 1804 1805 1806 1807

	seq_printf(m, "GMCH temp: %ld\n", temp);
	seq_printf(m, "Chipset power: %ld\n", chipset);
	seq_printf(m, "GFX power: %ld\n", gfx);
	seq_printf(m, "Total power: %ld\n", chipset + gfx);

	return 0;
}

1808 1809
static int i915_ring_freq_table(struct seq_file *m, void *unused)
{
1810
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
1811
	struct intel_rps *rps = &dev_priv->gt_pm.rps;
1812
	unsigned int max_gpu_freq, min_gpu_freq;
1813 1814
	int gpu_freq, ia_freq;
	int ret;
1815

1816 1817
	if (!HAS_LLC(dev_priv))
		return -ENODEV;
1818

1819 1820
	intel_runtime_pm_get(dev_priv);

1821
	ret = mutex_lock_interruptible(&dev_priv->pcu_lock);
1822
	if (ret)
1823
		goto out;
1824

1825 1826
	min_gpu_freq = rps->min_freq;
	max_gpu_freq = rps->max_freq;
1827
	if (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
1828
		/* Convert GT frequency to 50 HZ units */
1829 1830
		min_gpu_freq /= GEN9_FREQ_SCALER;
		max_gpu_freq /= GEN9_FREQ_SCALER;
1831 1832
	}

1833
	seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1834

1835
	for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
1836 1837 1838 1839
		ia_freq = gpu_freq;
		sandybridge_pcode_read(dev_priv,
				       GEN6_PCODE_READ_MIN_FREQ_TABLE,
				       &ia_freq);
1840
		seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1841
			   intel_gpu_freq(dev_priv, (gpu_freq *
1842
						     (IS_GEN9_BC(dev_priv) ||
1843
						      INTEL_GEN(dev_priv) >= 10 ?
1844
						      GEN9_FREQ_SCALER : 1))),
1845 1846
			   ((ia_freq >> 0) & 0xff) * 100,
			   ((ia_freq >> 8) & 0xff) * 100);
1847 1848
	}

1849
	mutex_unlock(&dev_priv->pcu_lock);
1850

1851 1852 1853
out:
	intel_runtime_pm_put(dev_priv);
	return ret;
1854 1855
}

1856 1857
static int i915_opregion(struct seq_file *m, void *unused)
{
1858 1859
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
	struct drm_device *dev = &dev_priv->drm;
1860 1861 1862 1863 1864
	struct intel_opregion *opregion = &dev_priv->opregion;
	int ret;

	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
1865
		goto out;
1866

1867 1868
	if (opregion->header)
		seq_write(m, opregion->header, OPREGION_SIZE);
1869 1870 1871

	mutex_unlock(&dev->struct_mutex);

1872
out:
1873 1874 1875
	return 0;
}

1876 1877
static int i915_vbt(struct seq_file *m, void *unused)
{
1878
	struct intel_opregion *opregion = &node_to_i915(m->private)->opregion;
1879 1880 1881 1882 1883 1884 1885

	if (opregion->vbt)
		seq_write(m, opregion->vbt, opregion->vbt_size);

	return 0;
}

1886 1887
static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
{
1888 1889
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
	struct drm_device *dev = &dev_priv->drm;
1890
	struct intel_framebuffer *fbdev_fb = NULL;
1891
	struct drm_framebuffer *drm_fb;
1892 1893 1894 1895 1896
	int ret;

	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;
1897

1898
#ifdef CONFIG_DRM_FBDEV_EMULATION
1899
	if (dev_priv->fbdev && dev_priv->fbdev->helper.fb) {
1900
		fbdev_fb = to_intel_framebuffer(dev_priv->fbdev->helper.fb);
1901 1902 1903 1904

		seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
			   fbdev_fb->base.width,
			   fbdev_fb->base.height,
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1905
			   fbdev_fb->base.format->depth,
1906
			   fbdev_fb->base.format->cpp[0] * 8,
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1907
			   fbdev_fb->base.modifier,
1908
			   drm_framebuffer_read_refcount(&fbdev_fb->base));
1909
		describe_obj(m, intel_fb_obj(&fbdev_fb->base));
1910 1911
		seq_putc(m, '\n');
	}
1912
#endif
1913

1914
	mutex_lock(&dev->mode_config.fb_lock);
1915
	drm_for_each_fb(drm_fb, dev) {
1916 1917
		struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb);
		if (fb == fbdev_fb)
1918 1919
			continue;

1920
		seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1921 1922
			   fb->base.width,
			   fb->base.height,
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1923
			   fb->base.format->depth,
1924
			   fb->base.format->cpp[0] * 8,
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1925
			   fb->base.modifier,
1926
			   drm_framebuffer_read_refcount(&fb->base));
1927
		describe_obj(m, intel_fb_obj(&fb->base));
1928
		seq_putc(m, '\n');
1929
	}
1930
	mutex_unlock(&dev->mode_config.fb_lock);
1931
	mutex_unlock(&dev->struct_mutex);
1932 1933 1934 1935

	return 0;
}

1936
static void describe_ctx_ring(struct seq_file *m, struct intel_ring *ring)
1937
{
1938 1939
	seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, emit: %u)",
		   ring->space, ring->head, ring->tail, ring->emit);
1940 1941
}

1942 1943
static int i915_context_status(struct seq_file *m, void *unused)
{
1944 1945
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
	struct drm_device *dev = &dev_priv->drm;
1946
	struct intel_engine_cs *engine;
1947
	struct i915_gem_context *ctx;
1948
	enum intel_engine_id id;
1949
	int ret;
1950

1951
	ret = mutex_lock_interruptible(&dev->struct_mutex);
1952 1953 1954
	if (ret)
		return ret;

1955
	list_for_each_entry(ctx, &dev_priv->contexts.list, link) {
1956
		seq_printf(m, "HW context %u ", ctx->hw_id);
1957
		if (ctx->pid) {
1958 1959
			struct task_struct *task;

1960
			task = get_pid_task(ctx->pid, PIDTYPE_PID);
1961 1962 1963 1964 1965
			if (task) {
				seq_printf(m, "(%s [%d]) ",
					   task->comm, task->pid);
				put_task_struct(task);
			}
1966 1967
		} else if (IS_ERR(ctx->file_priv)) {
			seq_puts(m, "(deleted) ");
1968 1969 1970 1971
		} else {
			seq_puts(m, "(kernel) ");
		}

1972 1973
		seq_putc(m, ctx->remap_slice ? 'R' : 'r');
		seq_putc(m, '\n');
1974

1975
		for_each_engine(engine, dev_priv, id) {
1976 1977
			struct intel_context *ce =
				to_intel_context(ctx, engine);
1978 1979 1980

			seq_printf(m, "%s: ", engine->name);
			if (ce->state)
1981
				describe_obj(m, ce->state->obj);
1982
			if (ce->ring)
1983
				describe_ctx_ring(m, ce->ring);
1984 1985
			seq_putc(m, '\n');
		}
1986 1987

		seq_putc(m, '\n');
1988 1989
	}

1990
	mutex_unlock(&dev->struct_mutex);
1991 1992 1993 1994

	return 0;
}

1995 1996
static const char *swizzle_string(unsigned swizzle)
{
1997
	switch (swizzle) {
1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012
	case I915_BIT_6_SWIZZLE_NONE:
		return "none";
	case I915_BIT_6_SWIZZLE_9:
		return "bit9";
	case I915_BIT_6_SWIZZLE_9_10:
		return "bit9/bit10";
	case I915_BIT_6_SWIZZLE_9_11:
		return "bit9/bit11";
	case I915_BIT_6_SWIZZLE_9_10_11:
		return "bit9/bit10/bit11";
	case I915_BIT_6_SWIZZLE_9_17:
		return "bit9/bit17";
	case I915_BIT_6_SWIZZLE_9_10_17:
		return "bit9/bit10/bit17";
	case I915_BIT_6_SWIZZLE_UNKNOWN:
2013
		return "unknown";
2014 2015 2016 2017 2018 2019 2020
	}

	return "bug";
}

static int i915_swizzle_info(struct seq_file *m, void *data)
{
2021
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
2022

2023
	intel_runtime_pm_get(dev_priv);
2024 2025 2026 2027 2028 2029

	seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
		   swizzle_string(dev_priv->mm.bit_6_swizzle_x));
	seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
		   swizzle_string(dev_priv->mm.bit_6_swizzle_y));

2030
	if (IS_GEN3(dev_priv) || IS_GEN4(dev_priv)) {
2031 2032
		seq_printf(m, "DDC = 0x%08x\n",
			   I915_READ(DCC));
2033 2034
		seq_printf(m, "DDC2 = 0x%08x\n",
			   I915_READ(DCC2));
2035 2036 2037 2038
		seq_printf(m, "C0DRB3 = 0x%04x\n",
			   I915_READ16(C0DRB3));
		seq_printf(m, "C1DRB3 = 0x%04x\n",
			   I915_READ16(C1DRB3));
2039
	} else if (INTEL_GEN(dev_priv) >= 6) {
2040 2041 2042 2043 2044 2045 2046 2047
		seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
			   I915_READ(MAD_DIMM_C0));
		seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
			   I915_READ(MAD_DIMM_C1));
		seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
			   I915_READ(MAD_DIMM_C2));
		seq_printf(m, "TILECTL = 0x%08x\n",
			   I915_READ(TILECTL));
2048
		if (INTEL_GEN(dev_priv) >= 8)
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2049 2050 2051 2052 2053
			seq_printf(m, "GAMTARBMODE = 0x%08x\n",
				   I915_READ(GAMTARBMODE));
		else
			seq_printf(m, "ARB_MODE = 0x%08x\n",
				   I915_READ(ARB_MODE));
2054 2055
		seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
			   I915_READ(DISP_ARB_CTL));
2056
	}
2057 2058 2059 2060

	if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
		seq_puts(m, "L-shaped memory detected\n");

2061
	intel_runtime_pm_put(dev_priv);
2062 2063 2064 2065

	return 0;
}

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2066 2067
static int per_file_ctx(int id, void *ptr, void *data)
{
2068
	struct i915_gem_context *ctx = ptr;
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2069
	struct seq_file *m = data;
2070 2071 2072 2073 2074 2075 2076
	struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;

	if (!ppgtt) {
		seq_printf(m, "  no ppgtt for context %d\n",
			   ctx->user_handle);
		return 0;
	}
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2077

2078 2079 2080
	if (i915_gem_context_is_default(ctx))
		seq_puts(m, "  default context:\n");
	else
2081
		seq_printf(m, "  context %d:\n", ctx->user_handle);
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2082 2083 2084 2085 2086
	ppgtt->debug_dump(ppgtt, m);

	return 0;
}

2087 2088
static void gen8_ppgtt_info(struct seq_file *m,
			    struct drm_i915_private *dev_priv)
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2089
{
2090
	struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2091 2092
	struct intel_engine_cs *engine;
	enum intel_engine_id id;
2093
	int i;
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2094

2095 2096 2097
	if (!ppgtt)
		return;

2098
	for_each_engine(engine, dev_priv, id) {
2099
		seq_printf(m, "%s\n", engine->name);
2100
		for (i = 0; i < 4; i++) {
2101
			u64 pdp = I915_READ(GEN8_RING_PDP_UDW(engine, i));
2102
			pdp <<= 32;
2103
			pdp |= I915_READ(GEN8_RING_PDP_LDW(engine, i));
2104
			seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
2105 2106 2107 2108
		}
	}
}

2109 2110
static void gen6_ppgtt_info(struct seq_file *m,
			    struct drm_i915_private *dev_priv)
2111
{
2112
	struct intel_engine_cs *engine;
2113
	enum intel_engine_id id;
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2114

2115
	if (IS_GEN6(dev_priv))
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2116 2117
		seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));

2118
	for_each_engine(engine, dev_priv, id) {
2119
		seq_printf(m, "%s\n", engine->name);
2120
		if (IS_GEN7(dev_priv))
2121 2122 2123 2124 2125 2126 2127 2128
			seq_printf(m, "GFX_MODE: 0x%08x\n",
				   I915_READ(RING_MODE_GEN7(engine)));
		seq_printf(m, "PP_DIR_BASE: 0x%08x\n",
			   I915_READ(RING_PP_DIR_BASE(engine)));
		seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n",
			   I915_READ(RING_PP_DIR_BASE_READ(engine)));
		seq_printf(m, "PP_DIR_DCLV: 0x%08x\n",
			   I915_READ(RING_PP_DIR_DCLV(engine)));
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2129 2130 2131 2132
	}
	if (dev_priv->mm.aliasing_ppgtt) {
		struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;

2133
		seq_puts(m, "aliasing PPGTT:\n");
2134
		seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset);
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2135

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2136
		ppgtt->debug_dump(ppgtt, m);
2137
	}
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2138

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2139
	seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
2140 2141 2142 2143
}

static int i915_ppgtt_info(struct seq_file *m, void *data)
{
2144 2145
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
	struct drm_device *dev = &dev_priv->drm;
2146
	struct drm_file *file;
2147
	int ret;
2148

2149 2150
	mutex_lock(&dev->filelist_mutex);
	ret = mutex_lock_interruptible(&dev->struct_mutex);
2151
	if (ret)
2152 2153
		goto out_unlock;

2154
	intel_runtime_pm_get(dev_priv);
2155

2156 2157 2158 2159
	if (INTEL_GEN(dev_priv) >= 8)
		gen8_ppgtt_info(m, dev_priv);
	else if (INTEL_GEN(dev_priv) >= 6)
		gen6_ppgtt_info(m, dev_priv);
2160

2161 2162
	list_for_each_entry_reverse(file, &dev->filelist, lhead) {
		struct drm_i915_file_private *file_priv = file->driver_priv;
2163
		struct task_struct *task;
2164

2165
		task = get_pid_task(file->pid, PIDTYPE_PID);
2166 2167
		if (!task) {
			ret = -ESRCH;
2168
			goto out_rpm;
2169
		}
2170 2171
		seq_printf(m, "\nproc: %s\n", task->comm);
		put_task_struct(task);
2172 2173 2174 2175
		idr_for_each(&file_priv->context_idr, per_file_ctx,
			     (void *)(unsigned long)m);
	}

2176
out_rpm:
2177
	intel_runtime_pm_put(dev_priv);
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2178
	mutex_unlock(&dev->struct_mutex);
2179 2180
out_unlock:
	mutex_unlock(&dev->filelist_mutex);
2181
	return ret;
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2182 2183
}

2184 2185
static int count_irq_waiters(struct drm_i915_private *i915)
{
2186
	struct intel_engine_cs *engine;
2187
	enum intel_engine_id id;
2188 2189
	int count = 0;

2190
	for_each_engine(engine, i915, id)
2191
		count += intel_engine_has_waiter(engine);
2192 2193 2194 2195

	return count;
}

2196 2197 2198 2199 2200 2201 2202 2203 2204 2205 2206 2207 2208 2209
static const char *rps_power_to_str(unsigned int power)
{
	static const char * const strings[] = {
		[LOW_POWER] = "low power",
		[BETWEEN] = "mixed",
		[HIGH_POWER] = "high power",
	};

	if (power >= ARRAY_SIZE(strings) || !strings[power])
		return "unknown";

	return strings[power];
}

2210 2211
static int i915_rps_boost_info(struct seq_file *m, void *data)
{
2212 2213
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
	struct drm_device *dev = &dev_priv->drm;
2214
	struct intel_rps *rps = &dev_priv->gt_pm.rps;
2215 2216
	struct drm_file *file;

2217
	seq_printf(m, "RPS enabled? %d\n", rps->enabled);
2218 2219
	seq_printf(m, "GPU busy? %s [%d requests]\n",
		   yesno(dev_priv->gt.awake), dev_priv->gt.active_requests);
2220
	seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv));
2221
	seq_printf(m, "Boosts outstanding? %d\n",
2222
		   atomic_read(&rps->num_waiters));
2223
	seq_printf(m, "Interactive? %d\n", READ_ONCE(rps->power.interactive));
2224
	seq_printf(m, "Frequency requested %d\n",
2225
		   intel_gpu_freq(dev_priv, rps->cur_freq));
2226
	seq_printf(m, "  min hard:%d, soft:%d; max soft:%d, hard:%d\n",
2227 2228 2229 2230
		   intel_gpu_freq(dev_priv, rps->min_freq),
		   intel_gpu_freq(dev_priv, rps->min_freq_softlimit),
		   intel_gpu_freq(dev_priv, rps->max_freq_softlimit),
		   intel_gpu_freq(dev_priv, rps->max_freq));
2231
	seq_printf(m, "  idle:%d, efficient:%d, boost:%d\n",
2232 2233 2234
		   intel_gpu_freq(dev_priv, rps->idle_freq),
		   intel_gpu_freq(dev_priv, rps->efficient_freq),
		   intel_gpu_freq(dev_priv, rps->boost_freq));
2235 2236

	mutex_lock(&dev->filelist_mutex);
2237 2238 2239 2240 2241 2242
	list_for_each_entry_reverse(file, &dev->filelist, lhead) {
		struct drm_i915_file_private *file_priv = file->driver_priv;
		struct task_struct *task;

		rcu_read_lock();
		task = pid_task(file->pid, PIDTYPE_PID);
2243
		seq_printf(m, "%s [%d]: %d boosts\n",
2244 2245
			   task ? task->comm : "<unknown>",
			   task ? task->pid : -1,
2246
			   atomic_read(&file_priv->rps_client.boosts));
2247 2248
		rcu_read_unlock();
	}
2249
	seq_printf(m, "Kernel (anonymous) boosts: %d\n",
2250
		   atomic_read(&rps->boosts));
2251
	mutex_unlock(&dev->filelist_mutex);
2252

2253
	if (INTEL_GEN(dev_priv) >= 6 &&
2254
	    rps->enabled &&
2255
	    dev_priv->gt.active_requests) {
2256 2257 2258 2259 2260 2261 2262 2263 2264 2265 2266
		u32 rpup, rpupei;
		u32 rpdown, rpdownei;

		intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
		rpup = I915_READ_FW(GEN6_RP_CUR_UP) & GEN6_RP_EI_MASK;
		rpupei = I915_READ_FW(GEN6_RP_CUR_UP_EI) & GEN6_RP_EI_MASK;
		rpdown = I915_READ_FW(GEN6_RP_CUR_DOWN) & GEN6_RP_EI_MASK;
		rpdownei = I915_READ_FW(GEN6_RP_CUR_DOWN_EI) & GEN6_RP_EI_MASK;
		intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);

		seq_printf(m, "\nRPS Autotuning (current \"%s\" window):\n",
2267
			   rps_power_to_str(rps->power.mode));
2268
		seq_printf(m, "  Avg. up: %d%% [above threshold? %d%%]\n",
2269
			   rpup && rpupei ? 100 * rpup / rpupei : 0,
2270
			   rps->power.up_threshold);
2271
		seq_printf(m, "  Avg. down: %d%% [below threshold? %d%%]\n",
2272
			   rpdown && rpdownei ? 100 * rpdown / rpdownei : 0,
2273
			   rps->power.down_threshold);
2274 2275 2276 2277
	} else {
		seq_puts(m, "\nRPS Autotuning inactive\n");
	}

2278
	return 0;
2279 2280
}

2281 2282
static int i915_llc(struct seq_file *m, void *data)
{
2283
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
2284
	const bool edram = INTEL_GEN(dev_priv) > 8;
2285

2286
	seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev_priv)));
2287 2288
	seq_printf(m, "%s: %lluMB\n", edram ? "eDRAM" : "eLLC",
		   intel_uncore_edram_size(dev_priv)/1024/1024);
2289 2290 2291 2292

	return 0;
}

2293 2294 2295
static int i915_huc_load_status_info(struct seq_file *m, void *data)
{
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
2296
	struct drm_printer p;
2297

2298 2299
	if (!HAS_HUC(dev_priv))
		return -ENODEV;
2300

2301 2302
	p = drm_seq_file_printer(m);
	intel_uc_fw_dump(&dev_priv->huc.fw, &p);
2303

2304
	intel_runtime_pm_get(dev_priv);
2305
	seq_printf(m, "\nHuC status 0x%08x:\n", I915_READ(HUC_STATUS2));
2306
	intel_runtime_pm_put(dev_priv);
2307 2308 2309 2310

	return 0;
}

2311 2312
static int i915_guc_load_status_info(struct seq_file *m, void *data)
{
2313
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
2314
	struct drm_printer p;
2315 2316
	u32 tmp, i;

2317 2318
	if (!HAS_GUC(dev_priv))
		return -ENODEV;
2319

2320 2321
	p = drm_seq_file_printer(m);
	intel_uc_fw_dump(&dev_priv->guc.fw, &p);
2322

2323 2324
	intel_runtime_pm_get(dev_priv);

2325 2326 2327 2328 2329 2330 2331 2332 2333 2334 2335 2336 2337
	tmp = I915_READ(GUC_STATUS);

	seq_printf(m, "\nGuC status 0x%08x:\n", tmp);
	seq_printf(m, "\tBootrom status = 0x%x\n",
		(tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT);
	seq_printf(m, "\tuKernel status = 0x%x\n",
		(tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT);
	seq_printf(m, "\tMIA Core status = 0x%x\n",
		(tmp & GS_MIA_MASK) >> GS_MIA_SHIFT);
	seq_puts(m, "\nScratch registers:\n");
	for (i = 0; i < 16; i++)
		seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i)));

2338 2339
	intel_runtime_pm_put(dev_priv);

2340 2341 2342
	return 0;
}

2343 2344 2345 2346 2347 2348 2349 2350 2351 2352 2353 2354 2355 2356 2357 2358 2359
static const char *
stringify_guc_log_type(enum guc_log_buffer_type type)
{
	switch (type) {
	case GUC_ISR_LOG_BUFFER:
		return "ISR";
	case GUC_DPC_LOG_BUFFER:
		return "DPC";
	case GUC_CRASH_DUMP_LOG_BUFFER:
		return "CRASH";
	default:
		MISSING_CASE(type);
	}

	return "";
}

2360 2361 2362
static void i915_guc_log_info(struct seq_file *m,
			      struct drm_i915_private *dev_priv)
{
2363 2364
	struct intel_guc_log *log = &dev_priv->guc.log;
	enum guc_log_buffer_type type;
2365

2366 2367 2368 2369
	if (!intel_guc_log_relay_enabled(log)) {
		seq_puts(m, "GuC log relay disabled\n");
		return;
	}
2370

2371
	seq_puts(m, "GuC logging stats:\n");
2372

2373
	seq_printf(m, "\tRelay full count: %u\n",
2374 2375 2376 2377 2378 2379 2380 2381
		   log->relay.full_count);

	for (type = GUC_ISR_LOG_BUFFER; type < GUC_MAX_LOG_BUFFER; type++) {
		seq_printf(m, "\t%s:\tflush count %10u, overflow count %10u\n",
			   stringify_guc_log_type(type),
			   log->stats[type].flush,
			   log->stats[type].sampled_overflow);
	}
2382 2383
}

2384 2385
static void i915_guc_client_info(struct seq_file *m,
				 struct drm_i915_private *dev_priv,
2386
				 struct intel_guc_client *client)
2387
{
2388
	struct intel_engine_cs *engine;
2389
	enum intel_engine_id id;
2390 2391
	uint64_t tot = 0;

2392 2393
	seq_printf(m, "\tPriority %d, GuC stage index: %u, PD offset 0x%x\n",
		client->priority, client->stage_id, client->proc_desc_offset);
2394 2395
	seq_printf(m, "\tDoorbell id %d, offset: 0x%lx\n",
		client->doorbell_id, client->doorbell_offset);
2396

2397
	for_each_engine(engine, dev_priv, id) {
2398 2399
		u64 submissions = client->submissions[id];
		tot += submissions;
2400
		seq_printf(m, "\tSubmissions: %llu %s\n",
2401
				submissions, engine->name);
2402 2403 2404 2405
	}
	seq_printf(m, "\tTotal: %llu\n", tot);
}

2406 2407 2408 2409 2410
static int i915_guc_info(struct seq_file *m, void *data)
{
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
	const struct intel_guc *guc = &dev_priv->guc;

2411
	if (!USES_GUC(dev_priv))
2412 2413
		return -ENODEV;

2414 2415 2416 2417 2418
	i915_guc_log_info(m, dev_priv);

	if (!USES_GUC_SUBMISSION(dev_priv))
		return 0;

2419
	GEM_BUG_ON(!guc->execbuf_client);
2420

2421
	seq_printf(m, "\nDoorbell map:\n");
2422
	seq_printf(m, "\t%*pb\n", GUC_NUM_DOORBELLS, guc->doorbell_bitmap);
2423
	seq_printf(m, "Doorbell next cacheline: 0x%x\n", guc->db_cacheline);
2424

2425 2426
	seq_printf(m, "\nGuC execbuf client @ %p:\n", guc->execbuf_client);
	i915_guc_client_info(m, dev_priv, guc->execbuf_client);
2427 2428 2429 2430 2431
	if (guc->preempt_client) {
		seq_printf(m, "\nGuC preempt client @ %p:\n",
			   guc->preempt_client);
		i915_guc_client_info(m, dev_priv, guc->preempt_client);
	}
2432 2433 2434 2435 2436 2437

	/* Add more as required ... */

	return 0;
}

2438
static int i915_guc_stage_pool(struct seq_file *m, void *data)
2439
{
2440
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
2441 2442
	const struct intel_guc *guc = &dev_priv->guc;
	struct guc_stage_desc *desc = guc->stage_desc_pool_vaddr;
2443
	struct intel_guc_client *client = guc->execbuf_client;
2444 2445
	unsigned int tmp;
	int index;
2446

2447 2448
	if (!USES_GUC_SUBMISSION(dev_priv))
		return -ENODEV;
2449

2450 2451 2452 2453 2454 2455 2456 2457 2458 2459 2460 2461 2462 2463 2464 2465 2466 2467 2468
	for (index = 0; index < GUC_MAX_STAGE_DESCRIPTORS; index++, desc++) {
		struct intel_engine_cs *engine;

		if (!(desc->attribute & GUC_STAGE_DESC_ATTR_ACTIVE))
			continue;

		seq_printf(m, "GuC stage descriptor %u:\n", index);
		seq_printf(m, "\tIndex: %u\n", desc->stage_id);
		seq_printf(m, "\tAttribute: 0x%x\n", desc->attribute);
		seq_printf(m, "\tPriority: %d\n", desc->priority);
		seq_printf(m, "\tDoorbell id: %d\n", desc->db_id);
		seq_printf(m, "\tEngines used: 0x%x\n",
			   desc->engines_used);
		seq_printf(m, "\tDoorbell trigger phy: 0x%llx, cpu: 0x%llx, uK: 0x%x\n",
			   desc->db_trigger_phy,
			   desc->db_trigger_cpu,
			   desc->db_trigger_uk);
		seq_printf(m, "\tProcess descriptor: 0x%x\n",
			   desc->process_desc);
2469
		seq_printf(m, "\tWorkqueue address: 0x%x, size: 0x%x\n",
2470 2471 2472 2473 2474 2475 2476 2477 2478 2479 2480 2481 2482 2483 2484 2485 2486 2487 2488 2489 2490 2491
			   desc->wq_addr, desc->wq_size);
		seq_putc(m, '\n');

		for_each_engine_masked(engine, dev_priv, client->engines, tmp) {
			u32 guc_engine_id = engine->guc_id;
			struct guc_execlist_context *lrc =
						&desc->lrc[guc_engine_id];

			seq_printf(m, "\t%s LRC:\n", engine->name);
			seq_printf(m, "\t\tContext desc: 0x%x\n",
				   lrc->context_desc);
			seq_printf(m, "\t\tContext id: 0x%x\n", lrc->context_id);
			seq_printf(m, "\t\tLRCA: 0x%x\n", lrc->ring_lrca);
			seq_printf(m, "\t\tRing begin: 0x%x\n", lrc->ring_begin);
			seq_printf(m, "\t\tRing end: 0x%x\n", lrc->ring_end);
			seq_putc(m, '\n');
		}
	}

	return 0;
}

2492 2493
static int i915_guc_log_dump(struct seq_file *m, void *data)
{
2494 2495 2496 2497 2498 2499
	struct drm_info_node *node = m->private;
	struct drm_i915_private *dev_priv = node_to_i915(node);
	bool dump_load_err = !!node->info_ent->data;
	struct drm_i915_gem_object *obj = NULL;
	u32 *log;
	int i = 0;
2500

2501 2502 2503
	if (!HAS_GUC(dev_priv))
		return -ENODEV;

2504 2505 2506 2507
	if (dump_load_err)
		obj = dev_priv->guc.load_err_log;
	else if (dev_priv->guc.log.vma)
		obj = dev_priv->guc.log.vma->obj;
2508

2509 2510
	if (!obj)
		return 0;
2511

2512 2513 2514 2515 2516
	log = i915_gem_object_pin_map(obj, I915_MAP_WC);
	if (IS_ERR(log)) {
		DRM_DEBUG("Failed to pin object\n");
		seq_puts(m, "(log data unaccessible)\n");
		return PTR_ERR(log);
2517 2518
	}

2519 2520 2521 2522 2523
	for (i = 0; i < obj->base.size / sizeof(u32); i += 4)
		seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n",
			   *(log + i), *(log + i + 1),
			   *(log + i + 2), *(log + i + 3));

2524 2525
	seq_putc(m, '\n');

2526 2527
	i915_gem_object_unpin_map(obj);

2528 2529 2530
	return 0;
}

2531
static int i915_guc_log_level_get(void *data, u64 *val)
2532
{
2533
	struct drm_i915_private *dev_priv = data;
2534

2535
	if (!USES_GUC(dev_priv))
2536 2537
		return -ENODEV;

2538
	*val = intel_guc_log_get_level(&dev_priv->guc.log);
2539 2540 2541 2542

	return 0;
}

2543
static int i915_guc_log_level_set(void *data, u64 val)
2544
{
2545
	struct drm_i915_private *dev_priv = data;
2546

2547
	if (!USES_GUC(dev_priv))
2548 2549
		return -ENODEV;

2550
	return intel_guc_log_set_level(&dev_priv->guc.log, val);
2551 2552
}

2553 2554
DEFINE_SIMPLE_ATTRIBUTE(i915_guc_log_level_fops,
			i915_guc_log_level_get, i915_guc_log_level_set,
2555 2556
			"%lld\n");

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static int i915_guc_log_relay_open(struct inode *inode, struct file *file)
{
	struct drm_i915_private *dev_priv = inode->i_private;

	if (!USES_GUC(dev_priv))
		return -ENODEV;

	file->private_data = &dev_priv->guc.log;

	return intel_guc_log_relay_open(&dev_priv->guc.log);
}

static ssize_t
i915_guc_log_relay_write(struct file *filp,
			 const char __user *ubuf,
			 size_t cnt,
			 loff_t *ppos)
{
	struct intel_guc_log *log = filp->private_data;

	intel_guc_log_relay_flush(log);

	return cnt;
}

static int i915_guc_log_relay_release(struct inode *inode, struct file *file)
{
	struct drm_i915_private *dev_priv = inode->i_private;

	intel_guc_log_relay_close(&dev_priv->guc.log);

	return 0;
}

static const struct file_operations i915_guc_log_relay_fops = {
	.owner = THIS_MODULE,
	.open = i915_guc_log_relay_open,
	.write = i915_guc_log_relay_write,
	.release = i915_guc_log_relay_release,
};

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static int i915_psr_sink_status_show(struct seq_file *m, void *data)
{
	u8 val;
	static const char * const sink_status[] = {
		"inactive",
		"transition to active, capture and display",
		"active, display from RFB",
		"active, capture and display on sink device timings",
		"transition to inactive, capture and display, timing re-sync",
		"reserved",
		"reserved",
		"sink internal error",
	};
	struct drm_connector *connector = m->private;
2612
	struct drm_i915_private *dev_priv = to_i915(connector->dev);
2613 2614
	struct intel_dp *intel_dp =
		enc_to_intel_dp(&intel_attached_encoder(connector)->base);
2615 2616 2617 2618 2619 2620
	int ret;

	if (!CAN_PSR(dev_priv)) {
		seq_puts(m, "PSR Unsupported\n");
		return -ENODEV;
	}
2621 2622 2623 2624

	if (connector->status != connector_status_connected)
		return -ENODEV;

2625 2626 2627
	ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_STATUS, &val);

	if (ret == 1) {
2628 2629 2630 2631 2632 2633 2634
		const char *str = "unknown";

		val &= DP_PSR_SINK_STATE_MASK;
		if (val < ARRAY_SIZE(sink_status))
			str = sink_status[val];
		seq_printf(m, "Sink PSR status: 0x%x [%s]\n", val, str);
	} else {
2635
		return ret;
2636 2637 2638 2639 2640 2641
	}

	return 0;
}
DEFINE_SHOW_ATTRIBUTE(i915_psr_sink_status);

2642 2643 2644 2645
static void
psr_source_status(struct drm_i915_private *dev_priv, struct seq_file *m)
{
	u32 val, psr_status;
2646

2647 2648 2649 2650 2651 2652 2653 2654 2655 2656 2657 2658 2659 2660 2661 2662 2663 2664 2665 2666 2667 2668 2669 2670 2671 2672 2673 2674 2675 2676 2677 2678 2679 2680 2681 2682 2683 2684 2685 2686 2687 2688
	if (dev_priv->psr.psr2_enabled) {
		static const char * const live_status[] = {
			"IDLE",
			"CAPTURE",
			"CAPTURE_FS",
			"SLEEP",
			"BUFON_FW",
			"ML_UP",
			"SU_STANDBY",
			"FAST_SLEEP",
			"DEEP_SLEEP",
			"BUF_ON",
			"TG_ON"
		};
		psr_status = I915_READ(EDP_PSR2_STATUS);
		val = (psr_status & EDP_PSR2_STATUS_STATE_MASK) >>
			EDP_PSR2_STATUS_STATE_SHIFT;
		if (val < ARRAY_SIZE(live_status)) {
			seq_printf(m, "Source PSR status: 0x%x [%s]\n",
				   psr_status, live_status[val]);
			return;
		}
	} else {
		static const char * const live_status[] = {
			"IDLE",
			"SRDONACK",
			"SRDENT",
			"BUFOFF",
			"BUFON",
			"AUXACK",
			"SRDOFFACK",
			"SRDENT_ON",
		};
		psr_status = I915_READ(EDP_PSR_STATUS);
		val = (psr_status & EDP_PSR_STATUS_STATE_MASK) >>
			EDP_PSR_STATUS_STATE_SHIFT;
		if (val < ARRAY_SIZE(live_status)) {
			seq_printf(m, "Source PSR status: 0x%x [%s]\n",
				   psr_status, live_status[val]);
			return;
		}
	}
2689

2690
	seq_printf(m, "Source PSR status: 0x%x [%s]\n", psr_status, "unknown");
2691 2692
}

2693 2694
static int i915_edp_psr_status(struct seq_file *m, void *data)
{
2695
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
2696 2697
	u32 psrperf = 0;
	bool enabled = false;
2698
	bool sink_support;
2699

2700 2701
	if (!HAS_PSR(dev_priv))
		return -ENODEV;
2702

2703 2704 2705 2706 2707
	sink_support = dev_priv->psr.sink_support;
	seq_printf(m, "Sink_Support: %s\n", yesno(sink_support));
	if (!sink_support)
		return 0;

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	intel_runtime_pm_get(dev_priv);

2710
	mutex_lock(&dev_priv->psr.lock);
2711
	seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
2712 2713
	seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
		   dev_priv->psr.busy_frontbuffer_bits);
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2715 2716 2717 2718
	if (dev_priv->psr.psr2_enabled)
		enabled = I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE;
	else
		enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
2719 2720 2721 2722

	seq_printf(m, "Main link in standby mode: %s\n",
		   yesno(dev_priv->psr.link_standby));

2723
	seq_printf(m, "HW Enabled & Active bit: %s\n", yesno(enabled));
2724

2725 2726 2727
	/*
	 * SKL+ Perf counter is reset to 0 everytime DC state is entered
	 */
2728
	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2729
		psrperf = I915_READ(EDP_PSR_PERF_CNT) &
2730
			EDP_PSR_PERF_CNT_MASK;
2731 2732 2733

		seq_printf(m, "Performance_Counter: %u\n", psrperf);
	}
2734

2735
	psr_source_status(dev_priv, m);
2736
	mutex_unlock(&dev_priv->psr.lock);
2737

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	if (READ_ONCE(dev_priv->psr.debug)) {
		seq_printf(m, "Last attempted entry at: %lld\n",
			   dev_priv->psr.last_entry_attempt);
		seq_printf(m, "Last exit at: %lld\n",
			   dev_priv->psr.last_exit);
	}

2745
	intel_runtime_pm_put(dev_priv);
2746 2747 2748
	return 0;
}

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static int
i915_edp_psr_debug_set(void *data, u64 val)
{
	struct drm_i915_private *dev_priv = data;

	if (!CAN_PSR(dev_priv))
		return -ENODEV;

	DRM_DEBUG_KMS("PSR debug %s\n", enableddisabled(val));

	intel_runtime_pm_get(dev_priv);
	intel_psr_irq_control(dev_priv, !!val);
	intel_runtime_pm_put(dev_priv);

	return 0;
}

static int
i915_edp_psr_debug_get(void *data, u64 *val)
{
	struct drm_i915_private *dev_priv = data;

	if (!CAN_PSR(dev_priv))
		return -ENODEV;

	*val = READ_ONCE(dev_priv->psr.debug);
	return 0;
}

DEFINE_SIMPLE_ATTRIBUTE(i915_edp_psr_debug_fops,
			i915_edp_psr_debug_get, i915_edp_psr_debug_set,
			"%llu\n");

2782 2783
static int i915_energy_uJ(struct seq_file *m, void *data)
{
2784
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
2785
	unsigned long long power;
2786 2787
	u32 units;

2788
	if (INTEL_GEN(dev_priv) < 6)
2789 2790
		return -ENODEV;

2791 2792
	intel_runtime_pm_get(dev_priv);

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	if (rdmsrl_safe(MSR_RAPL_POWER_UNIT, &power)) {
		intel_runtime_pm_put(dev_priv);
		return -ENODEV;
	}

	units = (power & 0x1f00) >> 8;
2799
	power = I915_READ(MCH_SECP_NRG_STTS);
2800
	power = (1000000 * power) >> units; /* convert to uJ */
2801

2802 2803
	intel_runtime_pm_put(dev_priv);

2804
	seq_printf(m, "%llu", power);
2805 2806 2807 2808

	return 0;
}

2809
static int i915_runtime_pm_status(struct seq_file *m, void *unused)
2810
{
2811
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
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David Weinehall committed
2812
	struct pci_dev *pdev = dev_priv->drm.pdev;
2813

2814 2815
	if (!HAS_RUNTIME_PM(dev_priv))
		seq_puts(m, "Runtime power management not supported\n");
2816

2817 2818
	seq_printf(m, "GPU idle: %s (epoch %u)\n",
		   yesno(!dev_priv->gt.awake), dev_priv->gt.epoch);
2819
	seq_printf(m, "IRQs disabled: %s\n",
2820
		   yesno(!intel_irqs_enabled(dev_priv)));
2821
#ifdef CONFIG_PM
2822
	seq_printf(m, "Usage count: %d\n",
2823
		   atomic_read(&dev_priv->drm.dev->power.usage_count));
2824 2825 2826
#else
	seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n");
#endif
2827
	seq_printf(m, "PCI device power state: %s [%d]\n",
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2828 2829
		   pci_power_name(pdev->current_state),
		   pdev->current_state);
2830

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	return 0;
}

2834 2835
static int i915_power_domain_info(struct seq_file *m, void *unused)
{
2836
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
2837 2838 2839 2840 2841 2842 2843 2844 2845 2846 2847 2848 2849 2850
	struct i915_power_domains *power_domains = &dev_priv->power_domains;
	int i;

	mutex_lock(&power_domains->lock);

	seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
	for (i = 0; i < power_domains->power_well_count; i++) {
		struct i915_power_well *power_well;
		enum intel_display_power_domain power_domain;

		power_well = &power_domains->power_wells[i];
		seq_printf(m, "%-25s %d\n", power_well->name,
			   power_well->count);

2851
		for_each_power_domain(power_domain, power_well->domains)
2852
			seq_printf(m, "  %-23s %d\n",
2853
				 intel_display_power_domain_str(power_domain),
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				 power_domains->domain_use_count[power_domain]);
	}

	mutex_unlock(&power_domains->lock);

	return 0;
}

2862 2863
static int i915_dmc_info(struct seq_file *m, void *unused)
{
2864
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
2865 2866
	struct intel_csr *csr;

2867 2868
	if (!HAS_CSR(dev_priv))
		return -ENODEV;
2869 2870 2871

	csr = &dev_priv->csr;

2872 2873
	intel_runtime_pm_get(dev_priv);

2874 2875 2876 2877
	seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL));
	seq_printf(m, "path: %s\n", csr->fw_path);

	if (!csr->dmc_payload)
2878
		goto out;
2879 2880 2881 2882

	seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
		   CSR_VERSION_MINOR(csr->version));

2883 2884
	if (IS_KABYLAKE(dev_priv) ||
	    (IS_SKYLAKE(dev_priv) && csr->version >= CSR_VERSION(1, 6))) {
2885 2886 2887 2888
		seq_printf(m, "DC3 -> DC5 count: %d\n",
			   I915_READ(SKL_CSR_DC3_DC5_COUNT));
		seq_printf(m, "DC5 -> DC6 count: %d\n",
			   I915_READ(SKL_CSR_DC5_DC6_COUNT));
2889
	} else if (IS_BROXTON(dev_priv) && csr->version >= CSR_VERSION(1, 4)) {
2890 2891
		seq_printf(m, "DC3 -> DC5 count: %d\n",
			   I915_READ(BXT_CSR_DC3_DC5_COUNT));
2892 2893
	}

2894 2895 2896 2897 2898
out:
	seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));
	seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE));
	seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL));

2899 2900
	intel_runtime_pm_put(dev_priv);

2901 2902 2903
	return 0;
}

2904 2905 2906 2907 2908 2909 2910 2911 2912 2913 2914 2915 2916 2917 2918 2919 2920 2921 2922 2923 2924 2925
static void intel_seq_print_mode(struct seq_file *m, int tabs,
				 struct drm_display_mode *mode)
{
	int i;

	for (i = 0; i < tabs; i++)
		seq_putc(m, '\t');

	seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
		   mode->base.id, mode->name,
		   mode->vrefresh, mode->clock,
		   mode->hdisplay, mode->hsync_start,
		   mode->hsync_end, mode->htotal,
		   mode->vdisplay, mode->vsync_start,
		   mode->vsync_end, mode->vtotal,
		   mode->type, mode->flags);
}

static void intel_encoder_info(struct seq_file *m,
			       struct intel_crtc *intel_crtc,
			       struct intel_encoder *intel_encoder)
{
2926 2927
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
	struct drm_device *dev = &dev_priv->drm;
2928 2929 2930 2931 2932 2933
	struct drm_crtc *crtc = &intel_crtc->base;
	struct intel_connector *intel_connector;
	struct drm_encoder *encoder;

	encoder = &intel_encoder->base;
	seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
2934
		   encoder->base.id, encoder->name);
2935 2936 2937 2938
	for_each_connector_on_encoder(dev, encoder, intel_connector) {
		struct drm_connector *connector = &intel_connector->base;
		seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
			   connector->base.id,
2939
			   connector->name,
2940 2941 2942 2943 2944 2945 2946 2947 2948 2949 2950 2951 2952
			   drm_get_connector_status_name(connector->status));
		if (connector->status == connector_status_connected) {
			struct drm_display_mode *mode = &crtc->mode;
			seq_printf(m, ", mode:\n");
			intel_seq_print_mode(m, 2, mode);
		} else {
			seq_putc(m, '\n');
		}
	}
}

static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
{
2953 2954
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
	struct drm_device *dev = &dev_priv->drm;
2955 2956
	struct drm_crtc *crtc = &intel_crtc->base;
	struct intel_encoder *intel_encoder;
2957 2958
	struct drm_plane_state *plane_state = crtc->primary->state;
	struct drm_framebuffer *fb = plane_state->fb;
2959

2960
	if (fb)
2961
		seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2962 2963
			   fb->base.id, plane_state->src_x >> 16,
			   plane_state->src_y >> 16, fb->width, fb->height);
2964 2965
	else
		seq_puts(m, "\tprimary plane disabled\n");
2966 2967 2968 2969 2970 2971 2972 2973 2974 2975 2976 2977 2978 2979 2980 2981 2982 2983 2984
	for_each_encoder_on_crtc(dev, crtc, intel_encoder)
		intel_encoder_info(m, intel_crtc, intel_encoder);
}

static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
{
	struct drm_display_mode *mode = panel->fixed_mode;

	seq_printf(m, "\tfixed mode:\n");
	intel_seq_print_mode(m, 2, mode);
}

static void intel_dp_info(struct seq_file *m,
			  struct intel_connector *intel_connector)
{
	struct intel_encoder *intel_encoder = intel_connector->encoder;
	struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);

	seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2985
	seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio));
2986
	if (intel_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)
2987
		intel_panel_info(m, &intel_connector->panel);
2988 2989 2990

	drm_dp_downstream_debug(m, intel_dp->dpcd, intel_dp->downstream_ports,
				&intel_dp->aux);
2991 2992
}

2993 2994 2995 2996 2997 2998 2999 3000 3001 3002 3003 3004 3005 3006
static void intel_dp_mst_info(struct seq_file *m,
			  struct intel_connector *intel_connector)
{
	struct intel_encoder *intel_encoder = intel_connector->encoder;
	struct intel_dp_mst_encoder *intel_mst =
		enc_to_mst(&intel_encoder->base);
	struct intel_digital_port *intel_dig_port = intel_mst->primary;
	struct intel_dp *intel_dp = &intel_dig_port->dp;
	bool has_audio = drm_dp_mst_port_has_audio(&intel_dp->mst_mgr,
					intel_connector->port);

	seq_printf(m, "\taudio support: %s\n", yesno(has_audio));
}

3007 3008 3009 3010 3011 3012
static void intel_hdmi_info(struct seq_file *m,
			    struct intel_connector *intel_connector)
{
	struct intel_encoder *intel_encoder = intel_connector->encoder;
	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);

3013
	seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio));
3014 3015 3016 3017 3018 3019 3020 3021 3022 3023 3024 3025 3026
}

static void intel_lvds_info(struct seq_file *m,
			    struct intel_connector *intel_connector)
{
	intel_panel_info(m, &intel_connector->panel);
}

static void intel_connector_info(struct seq_file *m,
				 struct drm_connector *connector)
{
	struct intel_connector *intel_connector = to_intel_connector(connector);
	struct intel_encoder *intel_encoder = intel_connector->encoder;
3027
	struct drm_display_mode *mode;
3028 3029

	seq_printf(m, "connector %d: type %s, status: %s\n",
3030
		   connector->base.id, connector->name,
3031 3032 3033 3034 3035 3036 3037 3038 3039 3040 3041
		   drm_get_connector_status_name(connector->status));
	if (connector->status == connector_status_connected) {
		seq_printf(m, "\tname: %s\n", connector->display_info.name);
		seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
			   connector->display_info.width_mm,
			   connector->display_info.height_mm);
		seq_printf(m, "\tsubpixel order: %s\n",
			   drm_get_subpixel_order_name(connector->display_info.subpixel_order));
		seq_printf(m, "\tCEA rev: %d\n",
			   connector->display_info.cea_rev);
	}
3042

3043
	if (!intel_encoder)
3044 3045 3046 3047 3048
		return;

	switch (connector->connector_type) {
	case DRM_MODE_CONNECTOR_DisplayPort:
	case DRM_MODE_CONNECTOR_eDP:
3049 3050 3051 3052
		if (intel_encoder->type == INTEL_OUTPUT_DP_MST)
			intel_dp_mst_info(m, intel_connector);
		else
			intel_dp_info(m, intel_connector);
3053 3054 3055
		break;
	case DRM_MODE_CONNECTOR_LVDS:
		if (intel_encoder->type == INTEL_OUTPUT_LVDS)
3056
			intel_lvds_info(m, intel_connector);
3057 3058 3059
		break;
	case DRM_MODE_CONNECTOR_HDMIA:
		if (intel_encoder->type == INTEL_OUTPUT_HDMI ||
3060
		    intel_encoder->type == INTEL_OUTPUT_DDI)
3061 3062 3063 3064
			intel_hdmi_info(m, intel_connector);
		break;
	default:
		break;
3065
	}
3066

3067 3068 3069
	seq_printf(m, "\tmodes:\n");
	list_for_each_entry(mode, &connector->modes, head)
		intel_seq_print_mode(m, 2, mode);
3070 3071
}

3072 3073 3074 3075 3076 3077 3078 3079 3080 3081 3082 3083 3084 3085 3086 3087 3088 3089 3090 3091 3092 3093
static const char *plane_type(enum drm_plane_type type)
{
	switch (type) {
	case DRM_PLANE_TYPE_OVERLAY:
		return "OVL";
	case DRM_PLANE_TYPE_PRIMARY:
		return "PRI";
	case DRM_PLANE_TYPE_CURSOR:
		return "CUR";
	/*
	 * Deliberately omitting default: to generate compiler warnings
	 * when a new drm_plane_type gets added.
	 */
	}

	return "unknown";
}

static const char *plane_rotation(unsigned int rotation)
{
	static char buf[48];
	/*
3094
	 * According to doc only one DRM_MODE_ROTATE_ is allowed but this
3095 3096 3097 3098
	 * will print them all to visualize if the values are misused
	 */
	snprintf(buf, sizeof(buf),
		 "%s%s%s%s%s%s(0x%08x)",
3099 3100 3101 3102 3103 3104
		 (rotation & DRM_MODE_ROTATE_0) ? "0 " : "",
		 (rotation & DRM_MODE_ROTATE_90) ? "90 " : "",
		 (rotation & DRM_MODE_ROTATE_180) ? "180 " : "",
		 (rotation & DRM_MODE_ROTATE_270) ? "270 " : "",
		 (rotation & DRM_MODE_REFLECT_X) ? "FLIPX " : "",
		 (rotation & DRM_MODE_REFLECT_Y) ? "FLIPY " : "",
3105 3106 3107 3108 3109 3110 3111
		 rotation);

	return buf;
}

static void intel_plane_info(struct seq_file *m, struct intel_crtc *intel_crtc)
{
3112 3113
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
	struct drm_device *dev = &dev_priv->drm;
3114 3115 3116 3117 3118
	struct intel_plane *intel_plane;

	for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
		struct drm_plane_state *state;
		struct drm_plane *plane = &intel_plane->base;
3119
		struct drm_format_name_buf format_name;
3120 3121 3122 3123 3124 3125 3126 3127

		if (!plane->state) {
			seq_puts(m, "plane->state is NULL!\n");
			continue;
		}

		state = plane->state;

3128
		if (state->fb) {
3129 3130
			drm_get_format_name(state->fb->format->format,
					    &format_name);
3131
		} else {
3132
			sprintf(format_name.str, "N/A");
3133 3134
		}

3135 3136 3137 3138 3139 3140 3141 3142 3143 3144 3145 3146 3147
		seq_printf(m, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n",
			   plane->base.id,
			   plane_type(intel_plane->base.type),
			   state->crtc_x, state->crtc_y,
			   state->crtc_w, state->crtc_h,
			   (state->src_x >> 16),
			   ((state->src_x & 0xffff) * 15625) >> 10,
			   (state->src_y >> 16),
			   ((state->src_y & 0xffff) * 15625) >> 10,
			   (state->src_w >> 16),
			   ((state->src_w & 0xffff) * 15625) >> 10,
			   (state->src_h >> 16),
			   ((state->src_h & 0xffff) * 15625) >> 10,
3148
			   format_name.str,
3149 3150 3151 3152 3153 3154 3155 3156 3157 3158 3159 3160 3161 3162 3163 3164 3165 3166 3167
			   plane_rotation(state->rotation));
	}
}

static void intel_scaler_info(struct seq_file *m, struct intel_crtc *intel_crtc)
{
	struct intel_crtc_state *pipe_config;
	int num_scalers = intel_crtc->num_scalers;
	int i;

	pipe_config = to_intel_crtc_state(intel_crtc->base.state);

	/* Not all platformas have a scaler */
	if (num_scalers) {
		seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d",
			   num_scalers,
			   pipe_config->scaler_state.scaler_users,
			   pipe_config->scaler_state.scaler_id);

3168
		for (i = 0; i < num_scalers; i++) {
3169 3170 3171 3172 3173 3174 3175 3176 3177 3178 3179 3180
			struct intel_scaler *sc =
					&pipe_config->scaler_state.scalers[i];

			seq_printf(m, ", scalers[%d]: use=%s, mode=%x",
				   i, yesno(sc->in_use), sc->mode);
		}
		seq_puts(m, "\n");
	} else {
		seq_puts(m, "\tNo scalers available on this platform\n");
	}
}

3181 3182
static int i915_display_info(struct seq_file *m, void *unused)
{
3183 3184
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
	struct drm_device *dev = &dev_priv->drm;
3185
	struct intel_crtc *crtc;
3186
	struct drm_connector *connector;
3187
	struct drm_connector_list_iter conn_iter;
3188

3189
	intel_runtime_pm_get(dev_priv);
3190 3191
	seq_printf(m, "CRTC info\n");
	seq_printf(m, "---------\n");
3192
	for_each_intel_crtc(dev, crtc) {
3193
		struct intel_crtc_state *pipe_config;
3194

3195
		drm_modeset_lock(&crtc->base.mutex, NULL);
3196 3197
		pipe_config = to_intel_crtc_state(crtc->base.state);

3198
		seq_printf(m, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n",
3199
			   crtc->base.base.id, pipe_name(crtc->pipe),
3200
			   yesno(pipe_config->base.active),
3201 3202 3203
			   pipe_config->pipe_src_w, pipe_config->pipe_src_h,
			   yesno(pipe_config->dither), pipe_config->pipe_bpp);

3204
		if (pipe_config->base.active) {
3205 3206 3207
			struct intel_plane *cursor =
				to_intel_plane(crtc->base.cursor);

3208 3209
			intel_crtc_info(m, crtc);

3210 3211 3212 3213 3214 3215 3216
			seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x\n",
				   yesno(cursor->base.state->visible),
				   cursor->base.state->crtc_x,
				   cursor->base.state->crtc_y,
				   cursor->base.state->crtc_w,
				   cursor->base.state->crtc_h,
				   cursor->cursor.base);
3217 3218
			intel_scaler_info(m, crtc);
			intel_plane_info(m, crtc);
3219
		}
3220 3221 3222 3223

		seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
			   yesno(!crtc->cpu_fifo_underrun_disabled),
			   yesno(!crtc->pch_fifo_underrun_disabled));
3224
		drm_modeset_unlock(&crtc->base.mutex);
3225 3226 3227 3228 3229
	}

	seq_printf(m, "\n");
	seq_printf(m, "Connector info\n");
	seq_printf(m, "--------------\n");
3230 3231 3232
	mutex_lock(&dev->mode_config.mutex);
	drm_connector_list_iter_begin(dev, &conn_iter);
	drm_for_each_connector_iter(connector, &conn_iter)
3233
		intel_connector_info(m, connector);
3234 3235 3236
	drm_connector_list_iter_end(&conn_iter);
	mutex_unlock(&dev->mode_config.mutex);

3237
	intel_runtime_pm_put(dev_priv);
3238 3239 3240 3241

	return 0;
}

3242 3243 3244 3245
static int i915_engine_info(struct seq_file *m, void *unused)
{
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
	struct intel_engine_cs *engine;
3246
	enum intel_engine_id id;
3247
	struct drm_printer p;
3248

3249 3250
	intel_runtime_pm_get(dev_priv);

3251 3252
	seq_printf(m, "GT awake? %s (epoch %u)\n",
		   yesno(dev_priv->gt.awake), dev_priv->gt.epoch);
3253 3254
	seq_printf(m, "Global active requests: %d\n",
		   dev_priv->gt.active_requests);
3255 3256
	seq_printf(m, "CS timestamp frequency: %u kHz\n",
		   dev_priv->info.cs_timestamp_frequency_khz);
3257

3258 3259
	p = drm_seq_file_printer(m);
	for_each_engine(engine, dev_priv, id)
3260
		intel_engine_dump(engine, &p, "%s\n", engine->name);
3261

3262 3263
	intel_runtime_pm_put(dev_priv);

3264 3265 3266
	return 0;
}

3267 3268 3269 3270 3271 3272 3273 3274 3275 3276
static int i915_rcs_topology(struct seq_file *m, void *unused)
{
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
	struct drm_printer p = drm_seq_file_printer(m);

	intel_device_info_dump_topology(&INTEL_INFO(dev_priv)->sseu, &p);

	return 0;
}

3277 3278 3279 3280 3281 3282 3283 3284 3285 3286
static int i915_shrinker_info(struct seq_file *m, void *unused)
{
	struct drm_i915_private *i915 = node_to_i915(m->private);

	seq_printf(m, "seeks = %d\n", i915->mm.shrinker.seeks);
	seq_printf(m, "batch = %lu\n", i915->mm.shrinker.batch);

	return 0;
}

3287 3288
static int i915_shared_dplls_info(struct seq_file *m, void *unused)
{
3289 3290
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
	struct drm_device *dev = &dev_priv->drm;
3291 3292 3293 3294 3295 3296
	int i;

	drm_modeset_lock_all(dev);
	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
		struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];

3297
		seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->info->name,
3298
			   pll->info->id);
3299
		seq_printf(m, " crtc_mask: 0x%08x, active: 0x%x, on: %s\n",
3300
			   pll->state.crtc_mask, pll->active_mask, yesno(pll->on));
3301
		seq_printf(m, " tracked hardware state:\n");
3302
		seq_printf(m, " dpll:    0x%08x\n", pll->state.hw_state.dpll);
3303
		seq_printf(m, " dpll_md: 0x%08x\n",
3304 3305 3306 3307
			   pll->state.hw_state.dpll_md);
		seq_printf(m, " fp0:     0x%08x\n", pll->state.hw_state.fp0);
		seq_printf(m, " fp1:     0x%08x\n", pll->state.hw_state.fp1);
		seq_printf(m, " wrpll:   0x%08x\n", pll->state.hw_state.wrpll);
3308 3309 3310 3311 3312 3313 3314 3315 3316 3317 3318 3319 3320 3321 3322 3323 3324 3325 3326 3327 3328 3329
		seq_printf(m, " cfgcr0:  0x%08x\n", pll->state.hw_state.cfgcr0);
		seq_printf(m, " cfgcr1:  0x%08x\n", pll->state.hw_state.cfgcr1);
		seq_printf(m, " mg_refclkin_ctl:        0x%08x\n",
			   pll->state.hw_state.mg_refclkin_ctl);
		seq_printf(m, " mg_clktop2_coreclkctl1: 0x%08x\n",
			   pll->state.hw_state.mg_clktop2_coreclkctl1);
		seq_printf(m, " mg_clktop2_hsclkctl:    0x%08x\n",
			   pll->state.hw_state.mg_clktop2_hsclkctl);
		seq_printf(m, " mg_pll_div0:  0x%08x\n",
			   pll->state.hw_state.mg_pll_div0);
		seq_printf(m, " mg_pll_div1:  0x%08x\n",
			   pll->state.hw_state.mg_pll_div1);
		seq_printf(m, " mg_pll_lf:    0x%08x\n",
			   pll->state.hw_state.mg_pll_lf);
		seq_printf(m, " mg_pll_frac_lock: 0x%08x\n",
			   pll->state.hw_state.mg_pll_frac_lock);
		seq_printf(m, " mg_pll_ssc:   0x%08x\n",
			   pll->state.hw_state.mg_pll_ssc);
		seq_printf(m, " mg_pll_bias:  0x%08x\n",
			   pll->state.hw_state.mg_pll_bias);
		seq_printf(m, " mg_pll_tdc_coldst_bias: 0x%08x\n",
			   pll->state.hw_state.mg_pll_tdc_coldst_bias);
3330 3331 3332 3333 3334 3335
	}
	drm_modeset_unlock_all(dev);

	return 0;
}

3336
static int i915_wa_registers(struct seq_file *m, void *unused)
3337
{
3338
	struct i915_workarounds *wa = &node_to_i915(m->private)->workarounds;
3339
	int i;
3340

3341 3342 3343 3344
	seq_printf(m, "Workarounds applied: %d\n", wa->count);
	for (i = 0; i < wa->count; ++i)
		seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X\n",
			   wa->reg[i].addr, wa->reg[i].value, wa->reg[i].mask);
3345 3346 3347 3348

	return 0;
}

3349 3350 3351 3352 3353 3354 3355 3356 3357 3358 3359 3360 3361 3362 3363 3364 3365 3366 3367 3368 3369 3370 3371 3372 3373 3374 3375 3376 3377 3378 3379 3380 3381 3382 3383 3384 3385 3386 3387 3388 3389 3390 3391 3392 3393 3394 3395 3396 3397 3398 3399
static int i915_ipc_status_show(struct seq_file *m, void *data)
{
	struct drm_i915_private *dev_priv = m->private;

	seq_printf(m, "Isochronous Priority Control: %s\n",
			yesno(dev_priv->ipc_enabled));
	return 0;
}

static int i915_ipc_status_open(struct inode *inode, struct file *file)
{
	struct drm_i915_private *dev_priv = inode->i_private;

	if (!HAS_IPC(dev_priv))
		return -ENODEV;

	return single_open(file, i915_ipc_status_show, dev_priv);
}

static ssize_t i915_ipc_status_write(struct file *file, const char __user *ubuf,
				     size_t len, loff_t *offp)
{
	struct seq_file *m = file->private_data;
	struct drm_i915_private *dev_priv = m->private;
	int ret;
	bool enable;

	ret = kstrtobool_from_user(ubuf, len, &enable);
	if (ret < 0)
		return ret;

	intel_runtime_pm_get(dev_priv);
	if (!dev_priv->ipc_enabled && enable)
		DRM_INFO("Enabling IPC: WM will be proper only after next commit\n");
	dev_priv->wm.distrust_bios_wm = true;
	dev_priv->ipc_enabled = enable;
	intel_enable_ipc(dev_priv);
	intel_runtime_pm_put(dev_priv);

	return len;
}

static const struct file_operations i915_ipc_status_fops = {
	.owner = THIS_MODULE,
	.open = i915_ipc_status_open,
	.read = seq_read,
	.llseek = seq_lseek,
	.release = single_release,
	.write = i915_ipc_status_write
};

3400 3401
static int i915_ddb_info(struct seq_file *m, void *unused)
{
3402 3403
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
	struct drm_device *dev = &dev_priv->drm;
3404 3405 3406 3407 3408
	struct skl_ddb_allocation *ddb;
	struct skl_ddb_entry *entry;
	enum pipe pipe;
	int plane;

3409
	if (INTEL_GEN(dev_priv) < 9)
3410
		return -ENODEV;
3411

3412 3413 3414 3415 3416 3417 3418 3419 3420
	drm_modeset_lock_all(dev);

	ddb = &dev_priv->wm.skl_hw.ddb;

	seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");

	for_each_pipe(dev_priv, pipe) {
		seq_printf(m, "Pipe %c\n", pipe_name(pipe));

3421
		for_each_universal_plane(dev_priv, pipe, plane) {
3422 3423 3424 3425 3426 3427
			entry = &ddb->plane[pipe][plane];
			seq_printf(m, "  Plane%-8d%8u%8u%8u\n", plane + 1,
				   entry->start, entry->end,
				   skl_ddb_entry_size(entry));
		}

3428
		entry = &ddb->plane[pipe][PLANE_CURSOR];
3429 3430 3431 3432 3433 3434 3435 3436 3437
		seq_printf(m, "  %-13s%8u%8u%8u\n", "Cursor", entry->start,
			   entry->end, skl_ddb_entry_size(entry));
	}

	drm_modeset_unlock_all(dev);

	return 0;
}

3438
static void drrs_status_per_crtc(struct seq_file *m,
3439 3440
				 struct drm_device *dev,
				 struct intel_crtc *intel_crtc)
3441
{
3442
	struct drm_i915_private *dev_priv = to_i915(dev);
3443 3444
	struct i915_drrs *drrs = &dev_priv->drrs;
	int vrefresh = 0;
3445
	struct drm_connector *connector;
3446
	struct drm_connector_list_iter conn_iter;
3447

3448 3449
	drm_connector_list_iter_begin(dev, &conn_iter);
	drm_for_each_connector_iter(connector, &conn_iter) {
3450 3451 3452 3453
		if (connector->state->crtc != &intel_crtc->base)
			continue;

		seq_printf(m, "%s:\n", connector->name);
3454
	}
3455
	drm_connector_list_iter_end(&conn_iter);
3456 3457 3458 3459 3460 3461 3462 3463 3464 3465 3466 3467

	if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT)
		seq_puts(m, "\tVBT: DRRS_type: Static");
	else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT)
		seq_puts(m, "\tVBT: DRRS_type: Seamless");
	else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED)
		seq_puts(m, "\tVBT: DRRS_type: None");
	else
		seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value");

	seq_puts(m, "\n\n");

3468
	if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) {
3469 3470 3471 3472 3473 3474 3475 3476
		struct intel_panel *panel;

		mutex_lock(&drrs->mutex);
		/* DRRS Supported */
		seq_puts(m, "\tDRRS Supported: Yes\n");

		/* disable_drrs() will make drrs->dp NULL */
		if (!drrs->dp) {
3477 3478 3479 3480
			seq_puts(m, "Idleness DRRS: Disabled\n");
			if (dev_priv->psr.enabled)
				seq_puts(m,
				"\tAs PSR is enabled, DRRS is not enabled\n");
3481 3482 3483 3484 3485 3486 3487 3488 3489 3490 3491 3492 3493 3494 3495 3496 3497 3498 3499 3500 3501 3502 3503 3504 3505 3506 3507 3508 3509 3510 3511 3512 3513 3514
			mutex_unlock(&drrs->mutex);
			return;
		}

		panel = &drrs->dp->attached_connector->panel;
		seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X",
					drrs->busy_frontbuffer_bits);

		seq_puts(m, "\n\t\t");
		if (drrs->refresh_rate_type == DRRS_HIGH_RR) {
			seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n");
			vrefresh = panel->fixed_mode->vrefresh;
		} else if (drrs->refresh_rate_type == DRRS_LOW_RR) {
			seq_puts(m, "DRRS_State: DRRS_LOW_RR\n");
			vrefresh = panel->downclock_mode->vrefresh;
		} else {
			seq_printf(m, "DRRS_State: Unknown(%d)\n",
						drrs->refresh_rate_type);
			mutex_unlock(&drrs->mutex);
			return;
		}
		seq_printf(m, "\t\tVrefresh: %d", vrefresh);

		seq_puts(m, "\n\t\t");
		mutex_unlock(&drrs->mutex);
	} else {
		/* DRRS not supported. Print the VBT parameter*/
		seq_puts(m, "\tDRRS Supported : No");
	}
	seq_puts(m, "\n");
}

static int i915_drrs_status(struct seq_file *m, void *unused)
{
3515 3516
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
	struct drm_device *dev = &dev_priv->drm;
3517 3518 3519
	struct intel_crtc *intel_crtc;
	int active_crtc_cnt = 0;

3520
	drm_modeset_lock_all(dev);
3521
	for_each_intel_crtc(dev, intel_crtc) {
3522
		if (intel_crtc->base.state->active) {
3523 3524 3525 3526 3527 3528
			active_crtc_cnt++;
			seq_printf(m, "\nCRTC %d:  ", active_crtc_cnt);

			drrs_status_per_crtc(m, dev, intel_crtc);
		}
	}
3529
	drm_modeset_unlock_all(dev);
3530 3531 3532 3533 3534 3535 3536

	if (!active_crtc_cnt)
		seq_puts(m, "No active crtc found\n");

	return 0;
}

3537 3538
static int i915_dp_mst_info(struct seq_file *m, void *unused)
{
3539 3540
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
	struct drm_device *dev = &dev_priv->drm;
3541 3542
	struct intel_encoder *intel_encoder;
	struct intel_digital_port *intel_dig_port;
3543
	struct drm_connector *connector;
3544
	struct drm_connector_list_iter conn_iter;
3545

3546 3547
	drm_connector_list_iter_begin(dev, &conn_iter);
	drm_for_each_connector_iter(connector, &conn_iter) {
3548
		if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
3549
			continue;
3550 3551 3552 3553 3554 3555

		intel_encoder = intel_attached_encoder(connector);
		if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST)
			continue;

		intel_dig_port = enc_to_dig_port(&intel_encoder->base);
3556 3557
		if (!intel_dig_port->dp.can_mst)
			continue;
3558

3559
		seq_printf(m, "MST Source Port %c\n",
3560
			   port_name(intel_dig_port->base.port));
3561 3562
		drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
	}
3563 3564
	drm_connector_list_iter_end(&conn_iter);

3565 3566 3567
	return 0;
}

3568
static ssize_t i915_displayport_test_active_write(struct file *file,
3569 3570
						  const char __user *ubuf,
						  size_t len, loff_t *offp)
3571 3572 3573 3574 3575
{
	char *input_buffer;
	int status = 0;
	struct drm_device *dev;
	struct drm_connector *connector;
3576
	struct drm_connector_list_iter conn_iter;
3577 3578 3579
	struct intel_dp *intel_dp;
	int val = 0;

3580
	dev = ((struct seq_file *)file->private_data)->private;
3581 3582 3583 3584

	if (len == 0)
		return 0;

3585 3586 3587
	input_buffer = memdup_user_nul(ubuf, len);
	if (IS_ERR(input_buffer))
		return PTR_ERR(input_buffer);
3588 3589 3590

	DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len);

3591 3592
	drm_connector_list_iter_begin(dev, &conn_iter);
	drm_for_each_connector_iter(connector, &conn_iter) {
3593 3594
		struct intel_encoder *encoder;

3595 3596 3597 3598
		if (connector->connector_type !=
		    DRM_MODE_CONNECTOR_DisplayPort)
			continue;

3599 3600 3601 3602 3603 3604
		encoder = to_intel_encoder(connector->encoder);
		if (encoder && encoder->type == INTEL_OUTPUT_DP_MST)
			continue;

		if (encoder && connector->status == connector_status_connected) {
			intel_dp = enc_to_intel_dp(&encoder->base);
3605 3606
			status = kstrtoint(input_buffer, 10, &val);
			if (status < 0)
3607
				break;
3608 3609 3610 3611 3612
			DRM_DEBUG_DRIVER("Got %d for test active\n", val);
			/* To prevent erroneous activation of the compliance
			 * testing code, only accept an actual value of 1 here
			 */
			if (val == 1)
3613
				intel_dp->compliance.test_active = 1;
3614
			else
3615
				intel_dp->compliance.test_active = 0;
3616 3617
		}
	}
3618
	drm_connector_list_iter_end(&conn_iter);
3619 3620 3621 3622 3623 3624 3625 3626 3627 3628
	kfree(input_buffer);
	if (status < 0)
		return status;

	*offp += len;
	return len;
}

static int i915_displayport_test_active_show(struct seq_file *m, void *data)
{
3629 3630
	struct drm_i915_private *dev_priv = m->private;
	struct drm_device *dev = &dev_priv->drm;
3631
	struct drm_connector *connector;
3632
	struct drm_connector_list_iter conn_iter;
3633 3634
	struct intel_dp *intel_dp;

3635 3636
	drm_connector_list_iter_begin(dev, &conn_iter);
	drm_for_each_connector_iter(connector, &conn_iter) {
3637 3638
		struct intel_encoder *encoder;

3639 3640 3641 3642
		if (connector->connector_type !=
		    DRM_MODE_CONNECTOR_DisplayPort)
			continue;

3643 3644 3645 3646 3647 3648
		encoder = to_intel_encoder(connector->encoder);
		if (encoder && encoder->type == INTEL_OUTPUT_DP_MST)
			continue;

		if (encoder && connector->status == connector_status_connected) {
			intel_dp = enc_to_intel_dp(&encoder->base);
3649
			if (intel_dp->compliance.test_active)
3650 3651 3652 3653 3654 3655
				seq_puts(m, "1");
			else
				seq_puts(m, "0");
		} else
			seq_puts(m, "0");
	}
3656
	drm_connector_list_iter_end(&conn_iter);
3657 3658 3659 3660 3661

	return 0;
}

static int i915_displayport_test_active_open(struct inode *inode,
3662
					     struct file *file)
3663
{
3664
	return single_open(file, i915_displayport_test_active_show,
3665
			   inode->i_private);
3666 3667 3668 3669 3670 3671 3672 3673 3674 3675 3676 3677 3678
}

static const struct file_operations i915_displayport_test_active_fops = {
	.owner = THIS_MODULE,
	.open = i915_displayport_test_active_open,
	.read = seq_read,
	.llseek = seq_lseek,
	.release = single_release,
	.write = i915_displayport_test_active_write
};

static int i915_displayport_test_data_show(struct seq_file *m, void *data)
{
3679 3680
	struct drm_i915_private *dev_priv = m->private;
	struct drm_device *dev = &dev_priv->drm;
3681
	struct drm_connector *connector;
3682
	struct drm_connector_list_iter conn_iter;
3683 3684
	struct intel_dp *intel_dp;

3685 3686
	drm_connector_list_iter_begin(dev, &conn_iter);
	drm_for_each_connector_iter(connector, &conn_iter) {
3687 3688
		struct intel_encoder *encoder;

3689 3690 3691 3692
		if (connector->connector_type !=
		    DRM_MODE_CONNECTOR_DisplayPort)
			continue;

3693 3694 3695 3696 3697 3698
		encoder = to_intel_encoder(connector->encoder);
		if (encoder && encoder->type == INTEL_OUTPUT_DP_MST)
			continue;

		if (encoder && connector->status == connector_status_connected) {
			intel_dp = enc_to_intel_dp(&encoder->base);
3699 3700 3701 3702
			if (intel_dp->compliance.test_type ==
			    DP_TEST_LINK_EDID_READ)
				seq_printf(m, "%lx",
					   intel_dp->compliance.test_data.edid);
3703 3704 3705 3706 3707 3708 3709 3710 3711
			else if (intel_dp->compliance.test_type ==
				 DP_TEST_LINK_VIDEO_PATTERN) {
				seq_printf(m, "hdisplay: %d\n",
					   intel_dp->compliance.test_data.hdisplay);
				seq_printf(m, "vdisplay: %d\n",
					   intel_dp->compliance.test_data.vdisplay);
				seq_printf(m, "bpc: %u\n",
					   intel_dp->compliance.test_data.bpc);
			}
3712 3713 3714
		} else
			seq_puts(m, "0");
	}
3715
	drm_connector_list_iter_end(&conn_iter);
3716 3717 3718

	return 0;
}
3719
DEFINE_SHOW_ATTRIBUTE(i915_displayport_test_data);
3720 3721 3722

static int i915_displayport_test_type_show(struct seq_file *m, void *data)
{
3723 3724
	struct drm_i915_private *dev_priv = m->private;
	struct drm_device *dev = &dev_priv->drm;
3725
	struct drm_connector *connector;
3726
	struct drm_connector_list_iter conn_iter;
3727 3728
	struct intel_dp *intel_dp;

3729 3730
	drm_connector_list_iter_begin(dev, &conn_iter);
	drm_for_each_connector_iter(connector, &conn_iter) {
3731 3732
		struct intel_encoder *encoder;

3733 3734 3735 3736
		if (connector->connector_type !=
		    DRM_MODE_CONNECTOR_DisplayPort)
			continue;

3737 3738 3739 3740 3741 3742
		encoder = to_intel_encoder(connector->encoder);
		if (encoder && encoder->type == INTEL_OUTPUT_DP_MST)
			continue;

		if (encoder && connector->status == connector_status_connected) {
			intel_dp = enc_to_intel_dp(&encoder->base);
3743
			seq_printf(m, "%02lx", intel_dp->compliance.test_type);
3744 3745 3746
		} else
			seq_puts(m, "0");
	}
3747
	drm_connector_list_iter_end(&conn_iter);
3748 3749 3750

	return 0;
}
3751
DEFINE_SHOW_ATTRIBUTE(i915_displayport_test_type);
3752

3753
static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
3754
{
3755 3756
	struct drm_i915_private *dev_priv = m->private;
	struct drm_device *dev = &dev_priv->drm;
3757
	int level;
3758 3759
	int num_levels;

3760
	if (IS_CHERRYVIEW(dev_priv))
3761
		num_levels = 3;
3762
	else if (IS_VALLEYVIEW(dev_priv))
3763
		num_levels = 1;
3764 3765
	else if (IS_G4X(dev_priv))
		num_levels = 3;
3766
	else
3767
		num_levels = ilk_wm_max_level(dev_priv) + 1;
3768 3769 3770 3771 3772 3773

	drm_modeset_lock_all(dev);

	for (level = 0; level < num_levels; level++) {
		unsigned int latency = wm[level];

3774 3775
		/*
		 * - WM1+ latency values in 0.5us units
3776
		 * - latencies are in us on gen9/vlv/chv
3777
		 */
3778 3779 3780 3781
		if (INTEL_GEN(dev_priv) >= 9 ||
		    IS_VALLEYVIEW(dev_priv) ||
		    IS_CHERRYVIEW(dev_priv) ||
		    IS_G4X(dev_priv))
3782 3783
			latency *= 10;
		else if (level > 0)
3784 3785 3786
			latency *= 5;

		seq_printf(m, "WM%d %u (%u.%u usec)\n",
3787
			   level, wm[level], latency / 10, latency % 10);
3788 3789 3790 3791 3792 3793 3794
	}

	drm_modeset_unlock_all(dev);
}

static int pri_wm_latency_show(struct seq_file *m, void *data)
{
3795
	struct drm_i915_private *dev_priv = m->private;
3796 3797
	const uint16_t *latencies;

3798
	if (INTEL_GEN(dev_priv) >= 9)
3799 3800
		latencies = dev_priv->wm.skl_latency;
	else
3801
		latencies = dev_priv->wm.pri_latency;
3802

3803
	wm_latency_show(m, latencies);
3804 3805 3806 3807 3808 3809

	return 0;
}

static int spr_wm_latency_show(struct seq_file *m, void *data)
{
3810
	struct drm_i915_private *dev_priv = m->private;
3811 3812
	const uint16_t *latencies;

3813
	if (INTEL_GEN(dev_priv) >= 9)
3814 3815
		latencies = dev_priv->wm.skl_latency;
	else
3816
		latencies = dev_priv->wm.spr_latency;
3817

3818
	wm_latency_show(m, latencies);
3819 3820 3821 3822 3823 3824

	return 0;
}

static int cur_wm_latency_show(struct seq_file *m, void *data)
{
3825
	struct drm_i915_private *dev_priv = m->private;
3826 3827
	const uint16_t *latencies;

3828
	if (INTEL_GEN(dev_priv) >= 9)
3829 3830
		latencies = dev_priv->wm.skl_latency;
	else
3831
		latencies = dev_priv->wm.cur_latency;
3832

3833
	wm_latency_show(m, latencies);
3834 3835 3836 3837 3838 3839

	return 0;
}

static int pri_wm_latency_open(struct inode *inode, struct file *file)
{
3840
	struct drm_i915_private *dev_priv = inode->i_private;
3841

3842
	if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
3843 3844
		return -ENODEV;

3845
	return single_open(file, pri_wm_latency_show, dev_priv);
3846 3847 3848 3849
}

static int spr_wm_latency_open(struct inode *inode, struct file *file)
{
3850
	struct drm_i915_private *dev_priv = inode->i_private;
3851

3852
	if (HAS_GMCH_DISPLAY(dev_priv))
3853 3854
		return -ENODEV;

3855
	return single_open(file, spr_wm_latency_show, dev_priv);
3856 3857 3858 3859
}

static int cur_wm_latency_open(struct inode *inode, struct file *file)
{
3860
	struct drm_i915_private *dev_priv = inode->i_private;
3861

3862
	if (HAS_GMCH_DISPLAY(dev_priv))
3863 3864
		return -ENODEV;

3865
	return single_open(file, cur_wm_latency_show, dev_priv);
3866 3867 3868
}

static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
3869
				size_t len, loff_t *offp, uint16_t wm[8])
3870 3871
{
	struct seq_file *m = file->private_data;
3872 3873
	struct drm_i915_private *dev_priv = m->private;
	struct drm_device *dev = &dev_priv->drm;
3874
	uint16_t new[8] = { 0 };
3875
	int num_levels;
3876 3877 3878 3879
	int level;
	int ret;
	char tmp[32];

3880
	if (IS_CHERRYVIEW(dev_priv))
3881
		num_levels = 3;
3882
	else if (IS_VALLEYVIEW(dev_priv))
3883
		num_levels = 1;
3884 3885
	else if (IS_G4X(dev_priv))
		num_levels = 3;
3886
	else
3887
		num_levels = ilk_wm_max_level(dev_priv) + 1;
3888

3889 3890 3891 3892 3893 3894 3895 3896
	if (len >= sizeof(tmp))
		return -EINVAL;

	if (copy_from_user(tmp, ubuf, len))
		return -EFAULT;

	tmp[len] = '\0';

3897 3898 3899
	ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
		     &new[0], &new[1], &new[2], &new[3],
		     &new[4], &new[5], &new[6], &new[7]);
3900 3901 3902 3903 3904 3905 3906 3907 3908 3909 3910 3911 3912 3913 3914 3915 3916 3917
	if (ret != num_levels)
		return -EINVAL;

	drm_modeset_lock_all(dev);

	for (level = 0; level < num_levels; level++)
		wm[level] = new[level];

	drm_modeset_unlock_all(dev);

	return len;
}


static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
				    size_t len, loff_t *offp)
{
	struct seq_file *m = file->private_data;
3918
	struct drm_i915_private *dev_priv = m->private;
3919
	uint16_t *latencies;
3920

3921
	if (INTEL_GEN(dev_priv) >= 9)
3922 3923
		latencies = dev_priv->wm.skl_latency;
	else
3924
		latencies = dev_priv->wm.pri_latency;
3925 3926

	return wm_latency_write(file, ubuf, len, offp, latencies);
3927 3928 3929 3930 3931 3932
}

static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
				    size_t len, loff_t *offp)
{
	struct seq_file *m = file->private_data;
3933
	struct drm_i915_private *dev_priv = m->private;
3934
	uint16_t *latencies;
3935

3936
	if (INTEL_GEN(dev_priv) >= 9)
3937 3938
		latencies = dev_priv->wm.skl_latency;
	else
3939
		latencies = dev_priv->wm.spr_latency;
3940 3941

	return wm_latency_write(file, ubuf, len, offp, latencies);
3942 3943 3944 3945 3946 3947
}

static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
				    size_t len, loff_t *offp)
{
	struct seq_file *m = file->private_data;
3948
	struct drm_i915_private *dev_priv = m->private;
3949 3950
	uint16_t *latencies;

3951
	if (INTEL_GEN(dev_priv) >= 9)
3952 3953
		latencies = dev_priv->wm.skl_latency;
	else
3954
		latencies = dev_priv->wm.cur_latency;
3955

3956
	return wm_latency_write(file, ubuf, len, offp, latencies);
3957 3958 3959 3960 3961 3962 3963 3964 3965 3966 3967 3968 3969 3970 3971 3972 3973 3974 3975 3976 3977 3978 3979 3980 3981 3982 3983 3984 3985
}

static const struct file_operations i915_pri_wm_latency_fops = {
	.owner = THIS_MODULE,
	.open = pri_wm_latency_open,
	.read = seq_read,
	.llseek = seq_lseek,
	.release = single_release,
	.write = pri_wm_latency_write
};

static const struct file_operations i915_spr_wm_latency_fops = {
	.owner = THIS_MODULE,
	.open = spr_wm_latency_open,
	.read = seq_read,
	.llseek = seq_lseek,
	.release = single_release,
	.write = spr_wm_latency_write
};

static const struct file_operations i915_cur_wm_latency_fops = {
	.owner = THIS_MODULE,
	.open = cur_wm_latency_open,
	.read = seq_read,
	.llseek = seq_lseek,
	.release = single_release,
	.write = cur_wm_latency_write
};

3986 3987
static int
i915_wedged_get(void *data, u64 *val)
3988
{
3989
	struct drm_i915_private *dev_priv = data;
3990

3991
	*val = i915_terminally_wedged(&dev_priv->gpu_error);
3992

3993
	return 0;
3994 3995
}

3996 3997
static int
i915_wedged_set(void *data, u64 val)
3998
{
3999 4000 4001
	struct drm_i915_private *i915 = data;
	struct intel_engine_cs *engine;
	unsigned int tmp;
4002

4003 4004 4005 4006 4007 4008 4009 4010
	/*
	 * There is no safeguard against this debugfs entry colliding
	 * with the hangcheck calling same i915_handle_error() in
	 * parallel, causing an explosion. For now we assume that the
	 * test harness is responsible enough not to inject gpu hangs
	 * while it is writing to 'i915_wedged'
	 */

4011
	if (i915_reset_backoff(&i915->gpu_error))
4012 4013
		return -EAGAIN;

4014 4015 4016 4017 4018
	for_each_engine_masked(engine, i915, val, tmp) {
		engine->hangcheck.seqno = intel_engine_get_seqno(engine);
		engine->hangcheck.stalled = true;
	}

4019 4020
	i915_handle_error(i915, val, I915_ERROR_CAPTURE,
			  "Manually set wedged engine mask = %llx", val);
4021

4022
	wait_on_bit(&i915->gpu_error.flags,
4023 4024 4025
		    I915_RESET_HANDOFF,
		    TASK_UNINTERRUPTIBLE);

4026
	return 0;
4027 4028
}

4029 4030
DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
			i915_wedged_get, i915_wedged_set,
4031
			"%llu\n");
4032

4033 4034 4035 4036 4037 4038 4039 4040 4041 4042 4043 4044 4045
static int
fault_irq_set(struct drm_i915_private *i915,
	      unsigned long *irq,
	      unsigned long val)
{
	int err;

	err = mutex_lock_interruptible(&i915->drm.struct_mutex);
	if (err)
		return err;

	err = i915_gem_wait_for_idle(i915,
				     I915_WAIT_LOCKED |
4046 4047
				     I915_WAIT_INTERRUPTIBLE,
				     MAX_SCHEDULE_TIMEOUT);
4048 4049 4050 4051 4052 4053 4054
	if (err)
		goto err_unlock;

	*irq = val;
	mutex_unlock(&i915->drm.struct_mutex);

	/* Flush idle worker to disarm irq */
4055
	drain_delayed_work(&i915->gt.idle_work);
4056 4057 4058 4059 4060 4061 4062 4063

	return 0;

err_unlock:
	mutex_unlock(&i915->drm.struct_mutex);
	return err;
}

4064 4065 4066
static int
i915_ring_missed_irq_get(void *data, u64 *val)
{
4067
	struct drm_i915_private *dev_priv = data;
4068 4069 4070 4071 4072 4073 4074 4075

	*val = dev_priv->gpu_error.missed_irq_rings;
	return 0;
}

static int
i915_ring_missed_irq_set(void *data, u64 val)
{
4076
	struct drm_i915_private *i915 = data;
4077

4078
	return fault_irq_set(i915, &i915->gpu_error.missed_irq_rings, val);
4079 4080 4081 4082 4083 4084 4085 4086 4087
}

DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
			i915_ring_missed_irq_get, i915_ring_missed_irq_set,
			"0x%08llx\n");

static int
i915_ring_test_irq_get(void *data, u64 *val)
{
4088
	struct drm_i915_private *dev_priv = data;
4089 4090 4091 4092 4093 4094 4095 4096 4097

	*val = dev_priv->gpu_error.test_irq_rings;

	return 0;
}

static int
i915_ring_test_irq_set(void *data, u64 val)
{
4098
	struct drm_i915_private *i915 = data;
4099

4100
	val &= INTEL_INFO(i915)->ring_mask;
4101 4102
	DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);

4103
	return fault_irq_set(i915, &i915->gpu_error.test_irq_rings, val);
4104 4105 4106 4107 4108 4109
}

DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
			i915_ring_test_irq_get, i915_ring_test_irq_set,
			"0x%08llx\n");

4110 4111 4112 4113 4114 4115 4116
#define DROP_UNBOUND	BIT(0)
#define DROP_BOUND	BIT(1)
#define DROP_RETIRE	BIT(2)
#define DROP_ACTIVE	BIT(3)
#define DROP_FREED	BIT(4)
#define DROP_SHRINK_ALL	BIT(5)
#define DROP_IDLE	BIT(6)
4117 4118 4119 4120
#define DROP_ALL (DROP_UNBOUND	| \
		  DROP_BOUND	| \
		  DROP_RETIRE	| \
		  DROP_ACTIVE	| \
4121
		  DROP_FREED	| \
4122 4123
		  DROP_SHRINK_ALL |\
		  DROP_IDLE)
4124 4125
static int
i915_drop_caches_get(void *data, u64 *val)
4126
{
4127
	*val = DROP_ALL;
4128

4129
	return 0;
4130 4131
}

4132 4133
static int
i915_drop_caches_set(void *data, u64 val)
4134
{
4135 4136
	struct drm_i915_private *dev_priv = data;
	struct drm_device *dev = &dev_priv->drm;
4137
	int ret = 0;
4138

4139 4140
	DRM_DEBUG("Dropping caches: 0x%08llx [0x%08llx]\n",
		  val, val & DROP_ALL);
4141 4142 4143

	/* No need to check and wait for gpu resets, only libdrm auto-restarts
	 * on ioctls on -EAGAIN. */
4144 4145
	if (val & (DROP_ACTIVE | DROP_RETIRE)) {
		ret = mutex_lock_interruptible(&dev->struct_mutex);
4146
		if (ret)
4147
			return ret;
4148

4149 4150 4151
		if (val & DROP_ACTIVE)
			ret = i915_gem_wait_for_idle(dev_priv,
						     I915_WAIT_INTERRUPTIBLE |
4152 4153
						     I915_WAIT_LOCKED,
						     MAX_SCHEDULE_TIMEOUT);
4154 4155

		if (val & DROP_RETIRE)
4156
			i915_retire_requests(dev_priv);
4157 4158 4159

		mutex_unlock(&dev->struct_mutex);
	}
4160

4161
	fs_reclaim_acquire(GFP_KERNEL);
4162
	if (val & DROP_BOUND)
4163
		i915_gem_shrink(dev_priv, LONG_MAX, NULL, I915_SHRINK_BOUND);
4164

4165
	if (val & DROP_UNBOUND)
4166
		i915_gem_shrink(dev_priv, LONG_MAX, NULL, I915_SHRINK_UNBOUND);
4167

4168 4169
	if (val & DROP_SHRINK_ALL)
		i915_gem_shrink_all(dev_priv);
4170
	fs_reclaim_release(GFP_KERNEL);
4171

4172 4173 4174 4175 4176 4177 4178
	if (val & DROP_IDLE) {
		do {
			if (READ_ONCE(dev_priv->gt.active_requests))
				flush_delayed_work(&dev_priv->gt.retire_work);
			drain_delayed_work(&dev_priv->gt.idle_work);
		} while (READ_ONCE(dev_priv->gt.awake));
	}
4179

4180
	if (val & DROP_FREED)
4181
		i915_gem_drain_freed_objects(dev_priv);
4182

4183
	return ret;
4184 4185
}

4186 4187 4188
DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
			i915_drop_caches_get, i915_drop_caches_set,
			"0x%08llx\n");
4189

4190 4191
static int
i915_cache_sharing_get(void *data, u64 *val)
4192
{
4193
	struct drm_i915_private *dev_priv = data;
4194 4195
	u32 snpcr;

4196
	if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv)))
4197 4198
		return -ENODEV;

4199
	intel_runtime_pm_get(dev_priv);
4200

4201
	snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4202 4203

	intel_runtime_pm_put(dev_priv);
4204

4205
	*val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
4206

4207
	return 0;
4208 4209
}

4210 4211
static int
i915_cache_sharing_set(void *data, u64 val)
4212
{
4213
	struct drm_i915_private *dev_priv = data;
4214 4215
	u32 snpcr;

4216
	if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv)))
4217 4218
		return -ENODEV;

4219
	if (val > 3)
4220 4221
		return -EINVAL;

4222
	intel_runtime_pm_get(dev_priv);
4223
	DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
4224 4225 4226 4227 4228 4229 4230

	/* Update the cache sharing policy here as well */
	snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
	snpcr &= ~GEN6_MBC_SNPCR_MASK;
	snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
	I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);

4231
	intel_runtime_pm_put(dev_priv);
4232
	return 0;
4233 4234
}

4235 4236 4237
DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
			i915_cache_sharing_get, i915_cache_sharing_set,
			"%llu\n");
4238

4239
static void cherryview_sseu_device_status(struct drm_i915_private *dev_priv,
4240
					  struct sseu_dev_info *sseu)
4241
{
4242 4243 4244
#define SS_MAX 2
	const int ss_max = SS_MAX;
	u32 sig1[SS_MAX], sig2[SS_MAX];
4245 4246 4247 4248 4249 4250 4251 4252 4253 4254 4255 4256 4257 4258
	int ss;

	sig1[0] = I915_READ(CHV_POWER_SS0_SIG1);
	sig1[1] = I915_READ(CHV_POWER_SS1_SIG1);
	sig2[0] = I915_READ(CHV_POWER_SS0_SIG2);
	sig2[1] = I915_READ(CHV_POWER_SS1_SIG2);

	for (ss = 0; ss < ss_max; ss++) {
		unsigned int eu_cnt;

		if (sig1[ss] & CHV_SS_PG_ENABLE)
			/* skip disabled subslice */
			continue;

4259
		sseu->slice_mask = BIT(0);
4260
		sseu->subslice_mask[0] |= BIT(ss);
4261 4262 4263 4264
		eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
			 ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
			 ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
			 ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2);
4265 4266 4267
		sseu->eu_total += eu_cnt;
		sseu->eu_per_subslice = max_t(unsigned int,
					      sseu->eu_per_subslice, eu_cnt);
4268
	}
4269
#undef SS_MAX
4270 4271
}

4272 4273 4274
static void gen10_sseu_device_status(struct drm_i915_private *dev_priv,
				     struct sseu_dev_info *sseu)
{
4275
#define SS_MAX 6
4276
	const struct intel_device_info *info = INTEL_INFO(dev_priv);
4277
	u32 s_reg[SS_MAX], eu_reg[2 * SS_MAX], eu_mask[2];
4278 4279
	int s, ss;

4280
	for (s = 0; s < info->sseu.max_slices; s++) {
4281 4282 4283 4284 4285 4286 4287 4288 4289 4290 4291 4292 4293 4294 4295 4296 4297 4298 4299 4300 4301
		/*
		 * FIXME: Valid SS Mask respects the spec and read
		 * only valid bits for those registers, excluding reserverd
		 * although this seems wrong because it would leave many
		 * subslices without ACK.
		 */
		s_reg[s] = I915_READ(GEN10_SLICE_PGCTL_ACK(s)) &
			GEN10_PGCTL_VALID_SS_MASK(s);
		eu_reg[2 * s] = I915_READ(GEN10_SS01_EU_PGCTL_ACK(s));
		eu_reg[2 * s + 1] = I915_READ(GEN10_SS23_EU_PGCTL_ACK(s));
	}

	eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
		     GEN9_PGCTL_SSA_EU19_ACK |
		     GEN9_PGCTL_SSA_EU210_ACK |
		     GEN9_PGCTL_SSA_EU311_ACK;
	eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
		     GEN9_PGCTL_SSB_EU19_ACK |
		     GEN9_PGCTL_SSB_EU210_ACK |
		     GEN9_PGCTL_SSB_EU311_ACK;

4302
	for (s = 0; s < info->sseu.max_slices; s++) {
4303 4304 4305 4306 4307
		if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
			/* skip disabled slice */
			continue;

		sseu->slice_mask |= BIT(s);
4308
		sseu->subslice_mask[s] = info->sseu.subslice_mask[s];
4309

4310
		for (ss = 0; ss < info->sseu.max_subslices; ss++) {
4311 4312 4313 4314 4315 4316 4317 4318 4319 4320 4321 4322 4323 4324
			unsigned int eu_cnt;

			if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
				/* skip disabled subslice */
				continue;

			eu_cnt = 2 * hweight32(eu_reg[2 * s + ss / 2] &
					       eu_mask[ss % 2]);
			sseu->eu_total += eu_cnt;
			sseu->eu_per_subslice = max_t(unsigned int,
						      sseu->eu_per_subslice,
						      eu_cnt);
		}
	}
4325
#undef SS_MAX
4326 4327
}

4328
static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
4329
				    struct sseu_dev_info *sseu)
4330
{
4331
#define SS_MAX 3
4332
	const struct intel_device_info *info = INTEL_INFO(dev_priv);
4333
	u32 s_reg[SS_MAX], eu_reg[2 * SS_MAX], eu_mask[2];
4334
	int s, ss;
4335

4336
	for (s = 0; s < info->sseu.max_slices; s++) {
4337 4338 4339 4340 4341
		s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s));
		eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s));
		eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s));
	}

4342 4343 4344 4345 4346 4347 4348 4349 4350
	eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
		     GEN9_PGCTL_SSA_EU19_ACK |
		     GEN9_PGCTL_SSA_EU210_ACK |
		     GEN9_PGCTL_SSA_EU311_ACK;
	eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
		     GEN9_PGCTL_SSB_EU19_ACK |
		     GEN9_PGCTL_SSB_EU210_ACK |
		     GEN9_PGCTL_SSB_EU311_ACK;

4351
	for (s = 0; s < info->sseu.max_slices; s++) {
4352 4353 4354 4355
		if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
			/* skip disabled slice */
			continue;

4356
		sseu->slice_mask |= BIT(s);
4357

4358
		if (IS_GEN9_BC(dev_priv))
4359 4360
			sseu->subslice_mask[s] =
				INTEL_INFO(dev_priv)->sseu.subslice_mask[s];
4361

4362
		for (ss = 0; ss < info->sseu.max_subslices; ss++) {
4363 4364
			unsigned int eu_cnt;

4365
			if (IS_GEN9_LP(dev_priv)) {
4366 4367 4368
				if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
					/* skip disabled subslice */
					continue;
4369

4370
				sseu->subslice_mask[s] |= BIT(ss);
4371
			}
4372

4373 4374
			eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
					       eu_mask[ss%2]);
4375 4376 4377 4378
			sseu->eu_total += eu_cnt;
			sseu->eu_per_subslice = max_t(unsigned int,
						      sseu->eu_per_subslice,
						      eu_cnt);
4379 4380
		}
	}
4381
#undef SS_MAX
4382 4383
}

4384
static void broadwell_sseu_device_status(struct drm_i915_private *dev_priv,
4385
					 struct sseu_dev_info *sseu)
4386 4387
{
	u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO);
4388
	int s;
4389

4390
	sseu->slice_mask = slice_info & GEN8_LSLICESTAT_MASK;
4391

4392
	if (sseu->slice_mask) {
4393 4394
		sseu->eu_per_subslice =
				INTEL_INFO(dev_priv)->sseu.eu_per_subslice;
4395 4396 4397 4398
		for (s = 0; s < fls(sseu->slice_mask); s++) {
			sseu->subslice_mask[s] =
				INTEL_INFO(dev_priv)->sseu.subslice_mask[s];
		}
4399 4400
		sseu->eu_total = sseu->eu_per_subslice *
				 sseu_subslice_total(sseu);
4401 4402

		/* subtract fused off EU(s) from enabled slice(s) */
4403
		for (s = 0; s < fls(sseu->slice_mask); s++) {
4404 4405
			u8 subslice_7eu =
				INTEL_INFO(dev_priv)->sseu.subslice_7eu[s];
4406

4407
			sseu->eu_total -= hweight8(subslice_7eu);
4408 4409 4410 4411
		}
	}
}

4412 4413 4414 4415 4416
static void i915_print_sseu_info(struct seq_file *m, bool is_available_info,
				 const struct sseu_dev_info *sseu)
{
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
	const char *type = is_available_info ? "Available" : "Enabled";
4417
	int s;
4418

4419 4420
	seq_printf(m, "  %s Slice Mask: %04x\n", type,
		   sseu->slice_mask);
4421
	seq_printf(m, "  %s Slice Total: %u\n", type,
4422
		   hweight8(sseu->slice_mask));
4423
	seq_printf(m, "  %s Subslice Total: %u\n", type,
4424
		   sseu_subslice_total(sseu));
4425 4426 4427 4428
	for (s = 0; s < fls(sseu->slice_mask); s++) {
		seq_printf(m, "  %s Slice%i subslices: %u\n", type,
			   s, hweight8(sseu->subslice_mask[s]));
	}
4429 4430 4431 4432 4433 4434 4435 4436 4437 4438 4439 4440 4441 4442 4443 4444 4445 4446 4447 4448
	seq_printf(m, "  %s EU Total: %u\n", type,
		   sseu->eu_total);
	seq_printf(m, "  %s EU Per Subslice: %u\n", type,
		   sseu->eu_per_subslice);

	if (!is_available_info)
		return;

	seq_printf(m, "  Has Pooled EU: %s\n", yesno(HAS_POOLED_EU(dev_priv)));
	if (HAS_POOLED_EU(dev_priv))
		seq_printf(m, "  Min EU in pool: %u\n", sseu->min_eu_in_pool);

	seq_printf(m, "  Has Slice Power Gating: %s\n",
		   yesno(sseu->has_slice_pg));
	seq_printf(m, "  Has Subslice Power Gating: %s\n",
		   yesno(sseu->has_subslice_pg));
	seq_printf(m, "  Has EU Power Gating: %s\n",
		   yesno(sseu->has_eu_pg));
}

4449 4450
static int i915_sseu_status(struct seq_file *m, void *unused)
{
4451
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
4452
	struct sseu_dev_info sseu;
4453

4454
	if (INTEL_GEN(dev_priv) < 8)
4455 4456 4457
		return -ENODEV;

	seq_puts(m, "SSEU Device Info\n");
4458
	i915_print_sseu_info(m, true, &INTEL_INFO(dev_priv)->sseu);
4459

4460
	seq_puts(m, "SSEU Device Status\n");
4461
	memset(&sseu, 0, sizeof(sseu));
4462 4463 4464 4465
	sseu.max_slices = INTEL_INFO(dev_priv)->sseu.max_slices;
	sseu.max_subslices = INTEL_INFO(dev_priv)->sseu.max_subslices;
	sseu.max_eus_per_subslice =
		INTEL_INFO(dev_priv)->sseu.max_eus_per_subslice;
4466 4467 4468

	intel_runtime_pm_get(dev_priv);

4469
	if (IS_CHERRYVIEW(dev_priv)) {
4470
		cherryview_sseu_device_status(dev_priv, &sseu);
4471
	} else if (IS_BROADWELL(dev_priv)) {
4472
		broadwell_sseu_device_status(dev_priv, &sseu);
4473
	} else if (IS_GEN9(dev_priv)) {
4474
		gen9_sseu_device_status(dev_priv, &sseu);
4475 4476
	} else if (INTEL_GEN(dev_priv) >= 10) {
		gen10_sseu_device_status(dev_priv, &sseu);
4477
	}
4478 4479 4480

	intel_runtime_pm_put(dev_priv);

4481
	i915_print_sseu_info(m, false, &sseu);
4482

4483 4484 4485
	return 0;
}

4486 4487
static int i915_forcewake_open(struct inode *inode, struct file *file)
{
4488
	struct drm_i915_private *i915 = inode->i_private;
4489

4490
	if (INTEL_GEN(i915) < 6)
4491 4492
		return 0;

4493 4494
	intel_runtime_pm_get(i915);
	intel_uncore_forcewake_user_get(i915);
4495 4496 4497 4498

	return 0;
}

4499
static int i915_forcewake_release(struct inode *inode, struct file *file)
4500
{
4501
	struct drm_i915_private *i915 = inode->i_private;
4502

4503
	if (INTEL_GEN(i915) < 6)
4504 4505
		return 0;

4506 4507
	intel_uncore_forcewake_user_put(i915);
	intel_runtime_pm_put(i915);
4508 4509 4510 4511 4512 4513 4514 4515 4516 4517

	return 0;
}

static const struct file_operations i915_forcewake_fops = {
	.owner = THIS_MODULE,
	.open = i915_forcewake_open,
	.release = i915_forcewake_release,
};

4518 4519 4520 4521 4522 4523 4524 4525 4526 4527 4528 4529 4530 4531 4532 4533 4534 4535 4536 4537 4538 4539 4540 4541 4542 4543 4544 4545 4546 4547 4548 4549 4550 4551 4552 4553 4554 4555 4556 4557 4558 4559 4560 4561 4562 4563 4564 4565 4566 4567 4568 4569 4570 4571 4572 4573 4574 4575 4576 4577 4578 4579 4580 4581 4582 4583 4584 4585 4586 4587 4588 4589 4590 4591 4592
static int i915_hpd_storm_ctl_show(struct seq_file *m, void *data)
{
	struct drm_i915_private *dev_priv = m->private;
	struct i915_hotplug *hotplug = &dev_priv->hotplug;

	seq_printf(m, "Threshold: %d\n", hotplug->hpd_storm_threshold);
	seq_printf(m, "Detected: %s\n",
		   yesno(delayed_work_pending(&hotplug->reenable_work)));

	return 0;
}

static ssize_t i915_hpd_storm_ctl_write(struct file *file,
					const char __user *ubuf, size_t len,
					loff_t *offp)
{
	struct seq_file *m = file->private_data;
	struct drm_i915_private *dev_priv = m->private;
	struct i915_hotplug *hotplug = &dev_priv->hotplug;
	unsigned int new_threshold;
	int i;
	char *newline;
	char tmp[16];

	if (len >= sizeof(tmp))
		return -EINVAL;

	if (copy_from_user(tmp, ubuf, len))
		return -EFAULT;

	tmp[len] = '\0';

	/* Strip newline, if any */
	newline = strchr(tmp, '\n');
	if (newline)
		*newline = '\0';

	if (strcmp(tmp, "reset") == 0)
		new_threshold = HPD_STORM_DEFAULT_THRESHOLD;
	else if (kstrtouint(tmp, 10, &new_threshold) != 0)
		return -EINVAL;

	if (new_threshold > 0)
		DRM_DEBUG_KMS("Setting HPD storm detection threshold to %d\n",
			      new_threshold);
	else
		DRM_DEBUG_KMS("Disabling HPD storm detection\n");

	spin_lock_irq(&dev_priv->irq_lock);
	hotplug->hpd_storm_threshold = new_threshold;
	/* Reset the HPD storm stats so we don't accidentally trigger a storm */
	for_each_hpd_pin(i)
		hotplug->stats[i].count = 0;
	spin_unlock_irq(&dev_priv->irq_lock);

	/* Re-enable hpd immediately if we were in an irq storm */
	flush_delayed_work(&dev_priv->hotplug.reenable_work);

	return len;
}

static int i915_hpd_storm_ctl_open(struct inode *inode, struct file *file)
{
	return single_open(file, i915_hpd_storm_ctl_show, inode->i_private);
}

static const struct file_operations i915_hpd_storm_ctl_fops = {
	.owner = THIS_MODULE,
	.open = i915_hpd_storm_ctl_open,
	.read = seq_read,
	.llseek = seq_lseek,
	.release = single_release,
	.write = i915_hpd_storm_ctl_write
};

4593 4594 4595 4596 4597 4598 4599 4600 4601 4602 4603 4604 4605 4606 4607 4608 4609 4610 4611 4612 4613 4614 4615 4616 4617 4618 4619 4620 4621 4622 4623 4624 4625 4626 4627 4628 4629 4630 4631 4632
static int i915_drrs_ctl_set(void *data, u64 val)
{
	struct drm_i915_private *dev_priv = data;
	struct drm_device *dev = &dev_priv->drm;
	struct intel_crtc *intel_crtc;
	struct intel_encoder *encoder;
	struct intel_dp *intel_dp;

	if (INTEL_GEN(dev_priv) < 7)
		return -ENODEV;

	drm_modeset_lock_all(dev);
	for_each_intel_crtc(dev, intel_crtc) {
		if (!intel_crtc->base.state->active ||
					!intel_crtc->config->has_drrs)
			continue;

		for_each_encoder_on_crtc(dev, &intel_crtc->base, encoder) {
			if (encoder->type != INTEL_OUTPUT_EDP)
				continue;

			DRM_DEBUG_DRIVER("Manually %sabling DRRS. %llu\n",
						val ? "en" : "dis", val);

			intel_dp = enc_to_intel_dp(&encoder->base);
			if (val)
				intel_edp_drrs_enable(intel_dp,
							intel_crtc->config);
			else
				intel_edp_drrs_disable(intel_dp,
							intel_crtc->config);
		}
	}
	drm_modeset_unlock_all(dev);

	return 0;
}

DEFINE_SIMPLE_ATTRIBUTE(i915_drrs_ctl_fops, NULL, i915_drrs_ctl_set, "%llu\n");

4633 4634 4635 4636 4637 4638 4639 4640 4641 4642 4643 4644 4645 4646 4647 4648 4649 4650 4651 4652 4653 4654 4655 4656 4657 4658 4659 4660 4661 4662 4663 4664 4665 4666 4667 4668 4669 4670 4671 4672 4673 4674 4675 4676 4677 4678 4679 4680 4681 4682 4683 4684 4685 4686 4687 4688 4689 4690 4691 4692 4693
static ssize_t
i915_fifo_underrun_reset_write(struct file *filp,
			       const char __user *ubuf,
			       size_t cnt, loff_t *ppos)
{
	struct drm_i915_private *dev_priv = filp->private_data;
	struct intel_crtc *intel_crtc;
	struct drm_device *dev = &dev_priv->drm;
	int ret;
	bool reset;

	ret = kstrtobool_from_user(ubuf, cnt, &reset);
	if (ret)
		return ret;

	if (!reset)
		return cnt;

	for_each_intel_crtc(dev, intel_crtc) {
		struct drm_crtc_commit *commit;
		struct intel_crtc_state *crtc_state;

		ret = drm_modeset_lock_single_interruptible(&intel_crtc->base.mutex);
		if (ret)
			return ret;

		crtc_state = to_intel_crtc_state(intel_crtc->base.state);
		commit = crtc_state->base.commit;
		if (commit) {
			ret = wait_for_completion_interruptible(&commit->hw_done);
			if (!ret)
				ret = wait_for_completion_interruptible(&commit->flip_done);
		}

		if (!ret && crtc_state->base.active) {
			DRM_DEBUG_KMS("Re-arming FIFO underruns on pipe %c\n",
				      pipe_name(intel_crtc->pipe));

			intel_crtc_arm_fifo_underrun(intel_crtc, crtc_state);
		}

		drm_modeset_unlock(&intel_crtc->base.mutex);

		if (ret)
			return ret;
	}

	ret = intel_fbc_reset_underrun(dev_priv);
	if (ret)
		return ret;

	return cnt;
}

static const struct file_operations i915_fifo_underrun_reset_ops = {
	.owner = THIS_MODULE,
	.open = simple_open,
	.write = i915_fifo_underrun_reset_write,
	.llseek = default_llseek,
};

4694
static const struct drm_info_list i915_debugfs_list[] = {
4695
	{"i915_capabilities", i915_capabilities, 0},
4696
	{"i915_gem_objects", i915_gem_object_info, 0},
4697
	{"i915_gem_gtt", i915_gem_gtt_info, 0},
4698
	{"i915_gem_stolen", i915_gem_stolen_list_info },
4699
	{"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
4700
	{"i915_gem_interrupt", i915_interrupt_info, 0},
4701
	{"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},
4702
	{"i915_guc_info", i915_guc_info, 0},
4703
	{"i915_guc_load_status", i915_guc_load_status_info, 0},
4704
	{"i915_guc_log_dump", i915_guc_log_dump, 0},
4705
	{"i915_guc_load_err_log_dump", i915_guc_log_dump, 0, (void *)1},
4706
	{"i915_guc_stage_pool", i915_guc_stage_pool, 0},
4707
	{"i915_huc_load_status", i915_huc_load_status_info, 0},
4708
	{"i915_frequency_info", i915_frequency_info, 0},
4709
	{"i915_hangcheck_info", i915_hangcheck_info, 0},
4710
	{"i915_reset_info", i915_reset_info, 0},
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	{"i915_drpc_info", i915_drpc_info, 0},
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	{"i915_emon_status", i915_emon_status, 0},
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	{"i915_ring_freq_table", i915_ring_freq_table, 0},
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	{"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0},
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	{"i915_fbc_status", i915_fbc_status, 0},
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	{"i915_ips_status", i915_ips_status, 0},
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	{"i915_sr_status", i915_sr_status, 0},
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	{"i915_opregion", i915_opregion, 0},
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	{"i915_vbt", i915_vbt, 0},
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	{"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
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	{"i915_context_status", i915_context_status, 0},
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	{"i915_forcewake_domains", i915_forcewake_domains, 0},
4723
	{"i915_swizzle_info", i915_swizzle_info, 0},
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Daniel Vetter committed
4724
	{"i915_ppgtt_info", i915_ppgtt_info, 0},
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	{"i915_llc", i915_llc, 0},
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	{"i915_edp_psr_status", i915_edp_psr_status, 0},
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	{"i915_energy_uJ", i915_energy_uJ, 0},
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	{"i915_runtime_pm_status", i915_runtime_pm_status, 0},
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	{"i915_power_domain_info", i915_power_domain_info, 0},
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	{"i915_dmc_info", i915_dmc_info, 0},
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	{"i915_display_info", i915_display_info, 0},
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	{"i915_engine_info", i915_engine_info, 0},
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	{"i915_rcs_topology", i915_rcs_topology, 0},
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	{"i915_shrinker_info", i915_shrinker_info, 0},
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	{"i915_shared_dplls_info", i915_shared_dplls_info, 0},
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	{"i915_dp_mst_info", i915_dp_mst_info, 0},
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	{"i915_wa_registers", i915_wa_registers, 0},
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	{"i915_ddb_info", i915_ddb_info, 0},
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	{"i915_sseu_status", i915_sseu_status, 0},
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	{"i915_drrs_status", i915_drrs_status, 0},
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	{"i915_rps_boost_info", i915_rps_boost_info, 0},
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};
4743
#define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
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4745
static const struct i915_debugfs_files {
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	const char *name;
	const struct file_operations *fops;
} i915_debugfs_files[] = {
	{"i915_wedged", &i915_wedged_fops},
	{"i915_cache_sharing", &i915_cache_sharing_fops},
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	{"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
	{"i915_ring_test_irq", &i915_ring_test_irq_fops},
4753
	{"i915_gem_drop_caches", &i915_drop_caches_fops},
4754
#if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
4755
	{"i915_error_state", &i915_error_state_fops},
4756
	{"i915_gpu_info", &i915_gpu_info_fops},
4757
#endif
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	{"i915_fifo_underrun_reset", &i915_fifo_underrun_reset_ops},
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	{"i915_next_seqno", &i915_next_seqno_fops},
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	{"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
	{"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
	{"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
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	{"i915_fbc_false_color", &i915_fbc_false_color_fops},
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	{"i915_dp_test_data", &i915_displayport_test_data_fops},
	{"i915_dp_test_type", &i915_displayport_test_type_fops},
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	{"i915_dp_test_active", &i915_displayport_test_active_fops},
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	{"i915_guc_log_level", &i915_guc_log_level_fops},
	{"i915_guc_log_relay", &i915_guc_log_relay_fops},
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	{"i915_hpd_storm_ctl", &i915_hpd_storm_ctl_fops},
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	{"i915_ipc_status", &i915_ipc_status_fops},
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	{"i915_drrs_ctl", &i915_drrs_ctl_fops},
	{"i915_edp_psr_debug", &i915_edp_psr_debug_fops}
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};

4775
int i915_debugfs_register(struct drm_i915_private *dev_priv)
4776
{
4777
	struct drm_minor *minor = dev_priv->drm.primary;
4778
	struct dentry *ent;
4779
	int i;
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	ent = debugfs_create_file("i915_forcewake_user", S_IRUSR,
				  minor->debugfs_root, to_i915(minor->dev),
				  &i915_forcewake_fops);
	if (!ent)
		return -ENOMEM;
4786

4787
	for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
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		ent = debugfs_create_file(i915_debugfs_files[i].name,
					  S_IRUGO | S_IWUSR,
					  minor->debugfs_root,
					  to_i915(minor->dev),
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					  i915_debugfs_files[i].fops);
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		if (!ent)
			return -ENOMEM;
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	}
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	return drm_debugfs_create_files(i915_debugfs_list,
					I915_DEBUGFS_ENTRIES,
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					minor->debugfs_root, minor);
}

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struct dpcd_block {
	/* DPCD dump start address. */
	unsigned int offset;
	/* DPCD dump end address, inclusive. If unset, .size will be used. */
	unsigned int end;
	/* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */
	size_t size;
	/* Only valid for eDP. */
	bool edp;
};

static const struct dpcd_block i915_dpcd_debug[] = {
	{ .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE },
	{ .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS },
	{ .offset = DP_DOWNSTREAM_PORT_0, .size = 16 },
	{ .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET },
	{ .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 },
	{ .offset = DP_SET_POWER },
	{ .offset = DP_EDP_DPCD_REV },
	{ .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 },
	{ .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB },
	{ .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET },
};

static int i915_dpcd_show(struct seq_file *m, void *data)
{
	struct drm_connector *connector = m->private;
	struct intel_dp *intel_dp =
		enc_to_intel_dp(&intel_attached_encoder(connector)->base);
	uint8_t buf[16];
	ssize_t err;
	int i;

4835 4836 4837
	if (connector->status != connector_status_connected)
		return -ENODEV;

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	for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) {
		const struct dpcd_block *b = &i915_dpcd_debug[i];
		size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1);

		if (b->edp &&
		    connector->connector_type != DRM_MODE_CONNECTOR_eDP)
			continue;

		/* low tech for now */
		if (WARN_ON(size > sizeof(buf)))
			continue;

		err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size);
		if (err <= 0) {
			DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n",
				  size, b->offset, err);
			continue;
		}

		seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf);
4858
	}
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	return 0;
}
4862
DEFINE_SHOW_ATTRIBUTE(i915_dpcd);
4863

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static int i915_panel_show(struct seq_file *m, void *data)
{
	struct drm_connector *connector = m->private;
	struct intel_dp *intel_dp =
		enc_to_intel_dp(&intel_attached_encoder(connector)->base);

	if (connector->status != connector_status_connected)
		return -ENODEV;

	seq_printf(m, "Panel power up delay: %d\n",
		   intel_dp->panel_power_up_delay);
	seq_printf(m, "Panel power down delay: %d\n",
		   intel_dp->panel_power_down_delay);
	seq_printf(m, "Backlight on delay: %d\n",
		   intel_dp->backlight_on_delay);
	seq_printf(m, "Backlight off delay: %d\n",
		   intel_dp->backlight_off_delay);

	return 0;
}
4884
DEFINE_SHOW_ATTRIBUTE(i915_panel);
4885

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/**
 * i915_debugfs_connector_add - add i915 specific connector debugfs files
 * @connector: pointer to a registered drm_connector
 *
 * Cleanup will be done by drm_connector_unregister() through a call to
 * drm_debugfs_connector_remove().
 *
 * Returns 0 on success, negative error codes on error.
 */
int i915_debugfs_connector_add(struct drm_connector *connector)
{
	struct dentry *root = connector->debugfs_entry;

	/* The connector must have been registered beforehands. */
	if (!root)
		return -ENODEV;

	if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
	    connector->connector_type == DRM_MODE_CONNECTOR_eDP)
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		debugfs_create_file("i915_dpcd", S_IRUGO, root,
				    connector, &i915_dpcd_fops);

4908
	if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
4909 4910
		debugfs_create_file("i915_panel_timings", S_IRUGO, root,
				    connector, &i915_panel_fops);
4911 4912 4913
		debugfs_create_file("i915_psr_sink_status", S_IRUGO, root,
				    connector, &i915_psr_sink_status_fops);
	}
4914 4915 4916

	return 0;
}