phy_n.c 192 KB
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/*

  Broadcom B43 wireless driver
  IEEE 802.11n PHY support

Michael Büsch's avatar
Michael Büsch committed
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  Copyright (c) 2008 Michael Buesch <m@bues.ch>
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  Copyright (c) 2010-2011 Rafał Miłecki <zajec5@gmail.com>
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  This program is free software; you can redistribute it and/or modify
  it under the terms of the GNU General Public License as published by
  the Free Software Foundation; either version 2 of the License, or
  (at your option) any later version.

  This program is distributed in the hope that it will be useful,
  but WITHOUT ANY WARRANTY; without even the implied warranty of
  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  GNU General Public License for more details.

  You should have received a copy of the GNU General Public License
  along with this program; see the file COPYING.  If not, write to
  the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  Boston, MA 02110-1301, USA.

*/

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#include <linux/delay.h>
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#include <linux/slab.h>
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#include <linux/types.h>

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#include "b43.h"
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#include "phy_n.h"
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#include "tables_nphy.h"
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#include "radio_2055.h"
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#include "radio_2056.h"
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#include "radio_2057.h"
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#include "main.h"
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struct nphy_txgains {
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	u16 tx_lpf[2];
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	u16 txgm[2];
	u16 pga[2];
	u16 pad[2];
	u16 ipa[2];
};

struct nphy_iqcal_params {
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	u16 tx_lpf;
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	u16 txgm;
	u16 pga;
	u16 pad;
	u16 ipa;
	u16 cal_gain;
	u16 ncorr[5];
};

struct nphy_iq_est {
	s32 iq0_prod;
	u32 i0_pwr;
	u32 q0_pwr;
	s32 iq1_prod;
	u32 i1_pwr;
	u32 q1_pwr;
};
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enum b43_nphy_rf_sequence {
	B43_RFSEQ_RX2TX,
	B43_RFSEQ_TX2RX,
	B43_RFSEQ_RESET2RX,
	B43_RFSEQ_UPDATE_GAINH,
	B43_RFSEQ_UPDATE_GAINL,
	B43_RFSEQ_UPDATE_GAINU,
};

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enum n_rf_ctl_over_cmd {
	N_RF_CTL_OVER_CMD_RXRF_PU = 0,
	N_RF_CTL_OVER_CMD_RX_PU = 1,
	N_RF_CTL_OVER_CMD_TX_PU = 2,
	N_RF_CTL_OVER_CMD_RX_GAIN = 3,
	N_RF_CTL_OVER_CMD_TX_GAIN = 4,
};

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enum n_intc_override {
	N_INTC_OVERRIDE_OFF = 0,
	N_INTC_OVERRIDE_TRSW = 1,
	N_INTC_OVERRIDE_PA = 2,
	N_INTC_OVERRIDE_EXT_LNA_PU = 3,
	N_INTC_OVERRIDE_EXT_LNA_GAIN = 4,
};

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enum n_rssi_type {
	N_RSSI_W1 = 0,
	N_RSSI_W2,
	N_RSSI_NB,
	N_RSSI_IQ,
	N_RSSI_TSSI_2G,
	N_RSSI_TSSI_5G,
	N_RSSI_TBD,
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};

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enum n_rail_type {
	N_RAIL_I = 0,
	N_RAIL_Q = 1,
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};

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static inline bool b43_nphy_ipa(struct b43_wldev *dev)
{
	enum ieee80211_band band = b43_current_band(dev->wl);
	return ((dev->phy.n->ipa2g_on && band == IEEE80211_BAND_2GHZ) ||
		(dev->phy.n->ipa5g_on && band == IEEE80211_BAND_5GHZ));
}

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/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCoreGetState */
static u8 b43_nphy_get_rx_core_state(struct b43_wldev *dev)
{
	return (b43_phy_read(dev, B43_NPHY_RFSEQCA) & B43_NPHY_RFSEQCA_RXEN) >>
		B43_NPHY_RFSEQCA_RXEN_SHIFT;
}

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/**************************************************
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 * RF (just without b43_nphy_rf_ctl_intc_override)
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 **************************************************/
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/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ForceRFSeq */
static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
				       enum b43_nphy_rf_sequence seq)
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{
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	static const u16 trigger[] = {
		[B43_RFSEQ_RX2TX]		= B43_NPHY_RFSEQTR_RX2TX,
		[B43_RFSEQ_TX2RX]		= B43_NPHY_RFSEQTR_TX2RX,
		[B43_RFSEQ_RESET2RX]		= B43_NPHY_RFSEQTR_RST2RX,
		[B43_RFSEQ_UPDATE_GAINH]	= B43_NPHY_RFSEQTR_UPGH,
		[B43_RFSEQ_UPDATE_GAINL]	= B43_NPHY_RFSEQTR_UPGL,
		[B43_RFSEQ_UPDATE_GAINU]	= B43_NPHY_RFSEQTR_UPGU,
	};
	int i;
	u16 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
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	B43_WARN_ON(seq >= ARRAY_SIZE(trigger));
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	b43_phy_set(dev, B43_NPHY_RFSEQMODE,
		    B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER);
	b43_phy_set(dev, B43_NPHY_RFSEQTR, trigger[seq]);
	for (i = 0; i < 200; i++) {
		if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & trigger[seq]))
			goto ok;
		msleep(1);
	}
	b43err(dev->wl, "RF sequence status timeout\n");
ok:
	b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
}
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static void b43_nphy_rf_ctl_override_rev19(struct b43_wldev *dev, u16 field,
					   u16 value, u8 core, bool off,
					   u8 override_id)
{
	/* TODO */
}

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/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverrideRev7 */
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static void b43_nphy_rf_ctl_override_rev7(struct b43_wldev *dev, u16 field,
					  u16 value, u8 core, bool off,
					  u8 override)
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{
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	struct b43_phy *phy = &dev->phy;
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	const struct nphy_rf_control_override_rev7 *e;
	u16 en_addrs[3][2] = {
		{ 0x0E7, 0x0EC }, { 0x342, 0x343 }, { 0x346, 0x347 }
	};
	u16 en_addr;
	u16 en_mask = field;
	u16 val_addr;
	u8 i;

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	if (phy->rev >= 19 || phy->rev < 3) {
		B43_WARN_ON(1);
		return;
	}

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	/* Remember: we can get NULL! */
	e = b43_nphy_get_rf_ctl_over_rev7(dev, field, override);

	for (i = 0; i < 2; i++) {
		if (override >= ARRAY_SIZE(en_addrs)) {
			b43err(dev->wl, "Invalid override value %d\n", override);
			return;
		}
		en_addr = en_addrs[override][i];

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		if (e)
			val_addr = (i == 0) ? e->val_addr_core0 : e->val_addr_core1;
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		if (off) {
			b43_phy_mask(dev, en_addr, ~en_mask);
			if (e) /* Do it safer, better than wl */
				b43_phy_mask(dev, val_addr, ~e->val_mask);
		} else {
			if (!core || (core & (1 << i))) {
				b43_phy_set(dev, en_addr, en_mask);
				if (e)
					b43_phy_maskset(dev, val_addr, ~e->val_mask, (value << e->val_shift));
			}
		}
	}
}

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/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverideOneToMany */
static void b43_nphy_rf_ctl_override_one_to_many(struct b43_wldev *dev,
						 enum n_rf_ctl_over_cmd cmd,
						 u16 value, u8 core, bool off)
{
	struct b43_phy *phy = &dev->phy;
	u16 tmp;

	B43_WARN_ON(phy->rev < 7);

	switch (cmd) {
	case N_RF_CTL_OVER_CMD_RXRF_PU:
		b43_nphy_rf_ctl_override_rev7(dev, 0x20, value, core, off, 1);
		b43_nphy_rf_ctl_override_rev7(dev, 0x10, value, core, off, 1);
		b43_nphy_rf_ctl_override_rev7(dev, 0x08, value, core, off, 1);
		break;
	case N_RF_CTL_OVER_CMD_RX_PU:
		b43_nphy_rf_ctl_override_rev7(dev, 0x4, value, core, off, 1);
		b43_nphy_rf_ctl_override_rev7(dev, 0x2, value, core, off, 1);
		b43_nphy_rf_ctl_override_rev7(dev, 0x1, value, core, off, 1);
		b43_nphy_rf_ctl_override_rev7(dev, 0x2, value, core, off, 2);
		b43_nphy_rf_ctl_override_rev7(dev, 0x0800, value, core, off, 1);
		break;
	case N_RF_CTL_OVER_CMD_TX_PU:
		b43_nphy_rf_ctl_override_rev7(dev, 0x4, value, core, off, 0);
		b43_nphy_rf_ctl_override_rev7(dev, 0x2, value, core, off, 1);
		b43_nphy_rf_ctl_override_rev7(dev, 0x1, value, core, off, 2);
		b43_nphy_rf_ctl_override_rev7(dev, 0x0800, value, core, off, 1);
		break;
	case N_RF_CTL_OVER_CMD_RX_GAIN:
		tmp = value & 0xFF;
		b43_nphy_rf_ctl_override_rev7(dev, 0x0800, tmp, core, off, 0);
		tmp = value >> 8;
		b43_nphy_rf_ctl_override_rev7(dev, 0x6000, tmp, core, off, 0);
		break;
	case N_RF_CTL_OVER_CMD_TX_GAIN:
		tmp = value & 0x7FFF;
		b43_nphy_rf_ctl_override_rev7(dev, 0x1000, tmp, core, off, 0);
		tmp = value >> 14;
		b43_nphy_rf_ctl_override_rev7(dev, 0x4000, tmp, core, off, 0);
		break;
	}
}

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/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverride */
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static void b43_nphy_rf_ctl_override(struct b43_wldev *dev, u16 field,
				     u16 value, u8 core, bool off)
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{
	int i;
	u8 index = fls(field);
	u8 addr, en_addr, val_addr;
	/* we expect only one bit set */
	B43_WARN_ON(field & (~(1 << (index - 1))));
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	if (dev->phy.rev >= 3) {
		const struct nphy_rf_control_override_rev3 *rf_ctrl;
		for (i = 0; i < 2; i++) {
			if (index == 0 || index == 16) {
				b43err(dev->wl,
					"Unsupported RF Ctrl Override call\n");
				return;
			}
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			rf_ctrl = &tbl_rf_control_override_rev3[index - 1];
			en_addr = B43_PHY_N((i == 0) ?
				rf_ctrl->en_addr0 : rf_ctrl->en_addr1);
			val_addr = B43_PHY_N((i == 0) ?
				rf_ctrl->val_addr0 : rf_ctrl->val_addr1);
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			if (off) {
				b43_phy_mask(dev, en_addr, ~(field));
				b43_phy_mask(dev, val_addr,
						~(rf_ctrl->val_mask));
			} else {
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				if (core == 0 || ((1 << i) & core)) {
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					b43_phy_set(dev, en_addr, field);
					b43_phy_maskset(dev, val_addr,
						~(rf_ctrl->val_mask),
						(value << rf_ctrl->val_shift));
				}
			}
		}
	} else {
		const struct nphy_rf_control_override_rev2 *rf_ctrl;
		if (off) {
			b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~(field));
			value = 0;
		} else {
			b43_phy_set(dev, B43_NPHY_RFCTL_OVER, field);
		}
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		for (i = 0; i < 2; i++) {
			if (index <= 1 || index == 16) {
				b43err(dev->wl,
					"Unsupported RF Ctrl Override call\n");
				return;
			}
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			if (index == 2 || index == 10 ||
			    (index >= 13 && index <= 15)) {
				core = 1;
			}
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			rf_ctrl = &tbl_rf_control_override_rev2[index - 2];
			addr = B43_PHY_N((i == 0) ?
				rf_ctrl->addr0 : rf_ctrl->addr1);
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			if ((1 << i) & core)
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				b43_phy_maskset(dev, addr, ~(rf_ctrl->bmask),
						(value << rf_ctrl->shift));

			b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1);
			b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
					B43_NPHY_RFCTL_CMD_START);
			udelay(1);
			b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, 0xFFFE);
		}
	}
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}

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static void b43_nphy_rf_ctl_intc_override_rev7(struct b43_wldev *dev,
					       enum n_intc_override intc_override,
					       u16 value, u8 core_sel)
{
	u16 reg, tmp, tmp2, val;
	int core;

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	/* TODO: What about rev19+? Revs 3+ and 7+ are a bit similar */

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	for (core = 0; core < 2; core++) {
		if ((core_sel == 1 && core != 0) ||
		    (core_sel == 2 && core != 1))
			continue;

		reg = (core == 0) ? B43_NPHY_RFCTL_INTC1 : B43_NPHY_RFCTL_INTC2;

		switch (intc_override) {
		case N_INTC_OVERRIDE_OFF:
			b43_phy_write(dev, reg, 0);
			b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
			break;
		case N_INTC_OVERRIDE_TRSW:
			b43_phy_maskset(dev, reg, ~0xC0, value << 6);
			b43_phy_set(dev, reg, 0x400);

			b43_phy_mask(dev, 0x2ff, ~0xC000 & 0xFFFF);
			b43_phy_set(dev, 0x2ff, 0x2000);
			b43_phy_set(dev, 0x2ff, 0x0001);
			break;
		case N_INTC_OVERRIDE_PA:
			tmp = 0x0030;
			if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
				val = value << 5;
			else
				val = value << 4;
			b43_phy_maskset(dev, reg, ~tmp, val);
			b43_phy_set(dev, reg, 0x1000);
			break;
		case N_INTC_OVERRIDE_EXT_LNA_PU:
			if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
				tmp = 0x0001;
				tmp2 = 0x0004;
				val = value;
			} else {
				tmp = 0x0004;
				tmp2 = 0x0001;
				val = value << 2;
			}
			b43_phy_maskset(dev, reg, ~tmp, val);
			b43_phy_mask(dev, reg, ~tmp2);
			break;
		case N_INTC_OVERRIDE_EXT_LNA_GAIN:
			if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
				tmp = 0x0002;
				tmp2 = 0x0008;
				val = value << 1;
			} else {
				tmp = 0x0008;
				tmp2 = 0x0002;
				val = value << 3;
			}
			b43_phy_maskset(dev, reg, ~tmp, val);
			b43_phy_mask(dev, reg, ~tmp2);
			break;
		}
	}
}

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/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlIntcOverride */
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static void b43_nphy_rf_ctl_intc_override(struct b43_wldev *dev,
					  enum n_intc_override intc_override,
					  u16 value, u8 core)
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{
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	u8 i, j;
	u16 reg, tmp, val;
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	if (dev->phy.rev >= 7) {
		b43_nphy_rf_ctl_intc_override_rev7(dev, intc_override, value,
						   core);
		return;
	}

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	B43_WARN_ON(dev->phy.rev < 3);

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	for (i = 0; i < 2; i++) {
		if ((core == 1 && i == 1) || (core == 2 && !i))
			continue;
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		reg = (i == 0) ?
			B43_NPHY_RFCTL_INTC1 : B43_NPHY_RFCTL_INTC2;
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		b43_phy_set(dev, reg, 0x400);
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		switch (intc_override) {
		case N_INTC_OVERRIDE_OFF:
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			b43_phy_write(dev, reg, 0);
			b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
			break;
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		case N_INTC_OVERRIDE_TRSW:
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			if (!i) {
				b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC1,
						0xFC3F, (value << 6));
				b43_phy_maskset(dev, B43_NPHY_TXF_40CO_B1S1,
						0xFFFE, 1);
				b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
						B43_NPHY_RFCTL_CMD_START);
				for (j = 0; j < 100; j++) {
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					if (!(b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_START)) {
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						j = 0;
						break;
					}
					udelay(10);
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				}
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				if (j)
					b43err(dev->wl,
						"intc override timeout\n");
				b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1,
						0xFFFE);
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			} else {
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				b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC2,
						0xFC3F, (value << 6));
				b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
						0xFFFE, 1);
				b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
						B43_NPHY_RFCTL_CMD_RXTX);
				for (j = 0; j < 100; j++) {
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					if (!(b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_RXTX)) {
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						j = 0;
						break;
					}
					udelay(10);
				}
				if (j)
					b43err(dev->wl,
						"intc override timeout\n");
				b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
						0xFFFE);
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			}
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			break;
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		case N_INTC_OVERRIDE_PA:
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			if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
				tmp = 0x0020;
				val = value << 5;
			} else {
				tmp = 0x0010;
				val = value << 4;
			}
			b43_phy_maskset(dev, reg, ~tmp, val);
			break;
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		case N_INTC_OVERRIDE_EXT_LNA_PU:
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			if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
				tmp = 0x0001;
				val = value;
			} else {
				tmp = 0x0004;
				val = value << 2;
			}
			b43_phy_maskset(dev, reg, ~tmp, val);
			break;
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		case N_INTC_OVERRIDE_EXT_LNA_GAIN:
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			if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
				tmp = 0x0002;
				val = value << 1;
			} else {
				tmp = 0x0008;
				val = value << 3;
			}
			b43_phy_maskset(dev, reg, ~tmp, val);
			break;
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		}
	}
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}
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/**************************************************
 * Various PHY ops
 **************************************************/

/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
static void b43_nphy_write_clip_detection(struct b43_wldev *dev,
					  const u16 *clip_st)
{
	b43_phy_write(dev, B43_NPHY_C1_CLIP1THRES, clip_st[0]);
	b43_phy_write(dev, B43_NPHY_C2_CLIP1THRES, clip_st[1]);
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}

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/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
static void b43_nphy_read_clip_detection(struct b43_wldev *dev, u16 *clip_st)
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{
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	clip_st[0] = b43_phy_read(dev, B43_NPHY_C1_CLIP1THRES);
	clip_st[1] = b43_phy_read(dev, B43_NPHY_C2_CLIP1THRES);
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}

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/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/classifier */
static u16 b43_nphy_classifier(struct b43_wldev *dev, u16 mask, u16 val)
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{
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	u16 tmp;
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	if (dev->dev->core_rev == 16)
		b43_mac_suspend(dev);
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	tmp = b43_phy_read(dev, B43_NPHY_CLASSCTL);
	tmp &= (B43_NPHY_CLASSCTL_CCKEN | B43_NPHY_CLASSCTL_OFDMEN |
		B43_NPHY_CLASSCTL_WAITEDEN);
	tmp &= ~mask;
	tmp |= (val & mask);
	b43_phy_maskset(dev, B43_NPHY_CLASSCTL, 0xFFF8, tmp);
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	if (dev->dev->core_rev == 16)
		b43_mac_enable(dev);
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	return tmp;
}
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/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CCA */
static void b43_nphy_reset_cca(struct b43_wldev *dev)
{
	u16 bbcfg;
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	b43_phy_force_clock(dev, 1);
	bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG);
	b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg | B43_NPHY_BBCFG_RSTCCA);
	udelay(1);
	b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg & ~B43_NPHY_BBCFG_RSTCCA);
	b43_phy_force_clock(dev, 0);
	b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
}
552

553 554 555 556 557
/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/carriersearch */
static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev, bool enable)
{
	struct b43_phy *phy = &dev->phy;
	struct b43_phy_n *nphy = phy->n;
558

559 560 561 562
	if (enable) {
		static const u16 clip[] = { 0xFFFF, 0xFFFF };
		if (nphy->deaf_count++ == 0) {
			nphy->classifier_state = b43_nphy_classifier(dev, 0, 0);
563 564
			b43_nphy_classifier(dev, 0x7,
					    B43_NPHY_CLASSCTL_WAITEDEN);
565 566 567 568
			b43_nphy_read_clip_detection(dev, nphy->clip_state);
			b43_nphy_write_clip_detection(dev, clip);
		}
		b43_nphy_reset_cca(dev);
569
	} else {
570 571 572
		if (--nphy->deaf_count == 0) {
			b43_nphy_classifier(dev, 0x7, nphy->classifier_state);
			b43_nphy_write_clip_detection(dev, nphy->clip_state);
573
		}
574 575 576
	}
}

577 578 579 580 581 582 583 584
/* http://bcm-v4.sipsolutions.net/PHY/N/Read_Lpf_Bw_Ctl */
static u16 b43_nphy_read_lpf_ctl(struct b43_wldev *dev, u16 offset)
{
	if (!offset)
		offset = b43_is_40mhz(dev) ? 0x159 : 0x154;
	return b43_ntab_read(dev, B43_NTAB16(7, offset)) & 0x7;
}

585 586
/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/AdjustLnaGainTbl */
static void b43_nphy_adjust_lna_gain_table(struct b43_wldev *dev)
587
{
588 589
	struct b43_phy_n *nphy = dev->phy.n;

590 591 592 593 594 595
	u8 i;
	s16 tmp;
	u16 data[4];
	s16 gain[2];
	u16 minmax[2];
	static const u16 lna_gain[4] = { -2, 10, 19, 25 };
596 597 598 599

	if (nphy->hang_avoid)
		b43_nphy_stay_in_carrier_search(dev, 1);

600
	if (nphy->gain_boost) {
601
		if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
602 603
			gain[0] = 6;
			gain[1] = 6;
604
		} else {
605 606 607 608
			tmp = 40370 - 315 * dev->phy.channel;
			gain[0] = ((tmp >> 13) + ((tmp >> 12) & 1));
			tmp = 23242 - 224 * dev->phy.channel;
			gain[1] = ((tmp >> 13) + ((tmp >> 12) & 1));
609
		}
610 611 612
	} else {
		gain[0] = 0;
		gain[1] = 0;
613 614 615
	}

	for (i = 0; i < 2; i++) {
616 617 618 619 620
		if (nphy->elna_gain_config) {
			data[0] = 19 + gain[i];
			data[1] = 25 + gain[i];
			data[2] = 25 + gain[i];
			data[3] = 25 + gain[i];
621
		} else {
622 623 624 625
			data[0] = lna_gain[0] + gain[i];
			data[1] = lna_gain[1] + gain[i];
			data[2] = lna_gain[2] + gain[i];
			data[3] = lna_gain[3] + gain[i];
626
		}
627
		b43_ntab_write_bulk(dev, B43_NTAB16(i, 8), 4, data);
628

629
		minmax[i] = 23 + gain[i];
630 631
	}

632 633 634 635
	b43_phy_maskset(dev, B43_NPHY_C1_MINMAX_GAIN, ~B43_NPHY_C1_MINGAIN,
				minmax[0] << B43_NPHY_C1_MINGAIN_SHIFT);
	b43_phy_maskset(dev, B43_NPHY_C2_MINMAX_GAIN, ~B43_NPHY_C2_MINGAIN,
				minmax[1] << B43_NPHY_C2_MINGAIN_SHIFT);
636 637 638

	if (nphy->hang_avoid)
		b43_nphy_stay_in_carrier_search(dev, 0);
639 640
}

641 642 643
/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRfSeq */
static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
					u8 *events, u8 *delays, u8 length)
644
{
645 646 647 648 649
	struct b43_phy_n *nphy = dev->phy.n;
	u8 i;
	u8 end = (dev->phy.rev >= 3) ? 0x1F : 0x0F;
	u16 offset1 = cmd << 4;
	u16 offset2 = offset1 + 0x80;
650

651 652
	if (nphy->hang_avoid)
		b43_nphy_stay_in_carrier_search(dev, true);
653

654 655
	b43_ntab_write_bulk(dev, B43_NTAB8(7, offset1), length, events);
	b43_ntab_write_bulk(dev, B43_NTAB8(7, offset2), length, delays);
656

657 658 659
	for (i = length; i < 16; i++) {
		b43_ntab_write(dev, B43_NTAB8(7, offset1 + i), end);
		b43_ntab_write(dev, B43_NTAB8(7, offset2 + i), 1);
660
	}
661 662 663

	if (nphy->hang_avoid)
		b43_nphy_stay_in_carrier_search(dev, false);
664
}
665

666 667 668 669
/**************************************************
 * Radio 0x2057
 **************************************************/

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static void b43_radio_2057_chantab_upload(struct b43_wldev *dev,
					  const struct b43_nphy_chantabent_rev7 *e_r7,
					  const struct b43_nphy_chantabent_rev7_2g *e_r7_2g)
{
	if (e_r7_2g) {
		b43_radio_write(dev, R2057_VCOCAL_COUNTVAL0, e_r7_2g->radio_vcocal_countval0);
		b43_radio_write(dev, R2057_VCOCAL_COUNTVAL1, e_r7_2g->radio_vcocal_countval1);
		b43_radio_write(dev, R2057_RFPLL_REFMASTER_SPAREXTALSIZE, e_r7_2g->radio_rfpll_refmaster_sparextalsize);
		b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_R1, e_r7_2g->radio_rfpll_loopfilter_r1);
		b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C2, e_r7_2g->radio_rfpll_loopfilter_c2);
		b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C1, e_r7_2g->radio_rfpll_loopfilter_c1);
		b43_radio_write(dev, R2057_CP_KPD_IDAC, e_r7_2g->radio_cp_kpd_idac);
		b43_radio_write(dev, R2057_RFPLL_MMD0, e_r7_2g->radio_rfpll_mmd0);
		b43_radio_write(dev, R2057_RFPLL_MMD1, e_r7_2g->radio_rfpll_mmd1);
		b43_radio_write(dev, R2057_VCOBUF_TUNE, e_r7_2g->radio_vcobuf_tune);
		b43_radio_write(dev, R2057_LOGEN_MX2G_TUNE, e_r7_2g->radio_logen_mx2g_tune);
		b43_radio_write(dev, R2057_LOGEN_INDBUF2G_TUNE, e_r7_2g->radio_logen_indbuf2g_tune);
		b43_radio_write(dev, R2057_TXMIX2G_TUNE_BOOST_PU_CORE0, e_r7_2g->radio_txmix2g_tune_boost_pu_core0);
		b43_radio_write(dev, R2057_PAD2G_TUNE_PUS_CORE0, e_r7_2g->radio_pad2g_tune_pus_core0);
		b43_radio_write(dev, R2057_LNA2G_TUNE_CORE0, e_r7_2g->radio_lna2g_tune_core0);
		b43_radio_write(dev, R2057_TXMIX2G_TUNE_BOOST_PU_CORE1, e_r7_2g->radio_txmix2g_tune_boost_pu_core1);
		b43_radio_write(dev, R2057_PAD2G_TUNE_PUS_CORE1, e_r7_2g->radio_pad2g_tune_pus_core1);
		b43_radio_write(dev, R2057_LNA2G_TUNE_CORE1, e_r7_2g->radio_lna2g_tune_core1);

	} else {
		b43_radio_write(dev, R2057_VCOCAL_COUNTVAL0, e_r7->radio_vcocal_countval0);
		b43_radio_write(dev, R2057_VCOCAL_COUNTVAL1, e_r7->radio_vcocal_countval1);
		b43_radio_write(dev, R2057_RFPLL_REFMASTER_SPAREXTALSIZE, e_r7->radio_rfpll_refmaster_sparextalsize);
		b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_R1, e_r7->radio_rfpll_loopfilter_r1);
		b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C2, e_r7->radio_rfpll_loopfilter_c2);
		b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C1, e_r7->radio_rfpll_loopfilter_c1);
		b43_radio_write(dev, R2057_CP_KPD_IDAC, e_r7->radio_cp_kpd_idac);
		b43_radio_write(dev, R2057_RFPLL_MMD0, e_r7->radio_rfpll_mmd0);
		b43_radio_write(dev, R2057_RFPLL_MMD1, e_r7->radio_rfpll_mmd1);
		b43_radio_write(dev, R2057_VCOBUF_TUNE, e_r7->radio_vcobuf_tune);
		b43_radio_write(dev, R2057_LOGEN_MX2G_TUNE, e_r7->radio_logen_mx2g_tune);
		b43_radio_write(dev, R2057_LOGEN_MX5G_TUNE, e_r7->radio_logen_mx5g_tune);
		b43_radio_write(dev, R2057_LOGEN_INDBUF2G_TUNE, e_r7->radio_logen_indbuf2g_tune);
		b43_radio_write(dev, R2057_LOGEN_INDBUF5G_TUNE, e_r7->radio_logen_indbuf5g_tune);
		b43_radio_write(dev, R2057_TXMIX2G_TUNE_BOOST_PU_CORE0, e_r7->radio_txmix2g_tune_boost_pu_core0);
		b43_radio_write(dev, R2057_PAD2G_TUNE_PUS_CORE0, e_r7->radio_pad2g_tune_pus_core0);
		b43_radio_write(dev, R2057_PGA_BOOST_TUNE_CORE0, e_r7->radio_pga_boost_tune_core0);
		b43_radio_write(dev, R2057_TXMIX5G_BOOST_TUNE_CORE0, e_r7->radio_txmix5g_boost_tune_core0);
		b43_radio_write(dev, R2057_PAD5G_TUNE_MISC_PUS_CORE0, e_r7->radio_pad5g_tune_misc_pus_core0);
		b43_radio_write(dev, R2057_LNA2G_TUNE_CORE0, e_r7->radio_lna2g_tune_core0);
		b43_radio_write(dev, R2057_LNA5G_TUNE_CORE0, e_r7->radio_lna5g_tune_core0);
		b43_radio_write(dev, R2057_TXMIX2G_TUNE_BOOST_PU_CORE1, e_r7->radio_txmix2g_tune_boost_pu_core1);
		b43_radio_write(dev, R2057_PAD2G_TUNE_PUS_CORE1, e_r7->radio_pad2g_tune_pus_core1);
		b43_radio_write(dev, R2057_PGA_BOOST_TUNE_CORE1, e_r7->radio_pga_boost_tune_core1);
		b43_radio_write(dev, R2057_TXMIX5G_BOOST_TUNE_CORE1, e_r7->radio_txmix5g_boost_tune_core1);
		b43_radio_write(dev, R2057_PAD5G_TUNE_MISC_PUS_CORE1, e_r7->radio_pad5g_tune_misc_pus_core1);
		b43_radio_write(dev, R2057_LNA2G_TUNE_CORE1, e_r7->radio_lna2g_tune_core1);
		b43_radio_write(dev, R2057_LNA5G_TUNE_CORE1, e_r7->radio_lna5g_tune_core1);
	}
}

static void b43_radio_2057_setup(struct b43_wldev *dev,
				 const struct b43_nphy_chantabent_rev7 *tabent_r7,
				 const struct b43_nphy_chantabent_rev7_2g *tabent_r7_2g)
{
	struct b43_phy *phy = &dev->phy;

	b43_radio_2057_chantab_upload(dev, tabent_r7, tabent_r7_2g);

	switch (phy->radio_rev) {
	case 0 ... 4:
	case 6:
		if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
			b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_R1, 0x3f);
			b43_radio_write(dev, R2057_CP_KPD_IDAC, 0x3f);
			b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C1, 0x8);
			b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C2, 0x8);
		} else {
			b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_R1, 0x1f);
			b43_radio_write(dev, R2057_CP_KPD_IDAC, 0x3f);
			b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C1, 0x8);
			b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C2, 0x8);
		}
		break;
749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767
	case 9: /* e.g. PHY rev 16 */
		b43_radio_write(dev, R2057_LOGEN_PTAT_RESETS, 0x20);
		b43_radio_write(dev, R2057_VCOBUF_IDACS, 0x18);
		if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
			b43_radio_write(dev, R2057_LOGEN_PTAT_RESETS, 0x38);
			b43_radio_write(dev, R2057_VCOBUF_IDACS, 0x0f);

			if (b43_is_40mhz(dev)) {
				/* TODO */
			} else {
				b43_radio_write(dev,
						R2057_PAD_BIAS_FILTER_BWS_CORE0,
						0x3c);
				b43_radio_write(dev,
						R2057_PAD_BIAS_FILTER_BWS_CORE1,
						0x3c);
			}
		}
		break;
768 769 770 771 772 773
	case 14: /* 2 GHz only */
		b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_R1, 0x1b);
		b43_radio_write(dev, R2057_CP_KPD_IDAC, 0x3f);
		b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C1, 0x1f);
		b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C2, 0x1f);
		break;
774 775
	}

776 777 778 779 780 781 782 783 784 785
	if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
		u16 txmix2g_tune_boost_pu = 0;
		u16 pad2g_tune_pus = 0;

		if (b43_nphy_ipa(dev)) {
			switch (phy->radio_rev) {
			case 9:
				txmix2g_tune_boost_pu = 0x0041;
				/* TODO */
				break;
786 787 788 789
			case 14:
				txmix2g_tune_boost_pu = 0x21;
				pad2g_tune_pus = 0x23;
				break;
790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805
			}
		}

		if (txmix2g_tune_boost_pu)
			b43_radio_write(dev, R2057_TXMIX2G_TUNE_BOOST_PU_CORE0,
					txmix2g_tune_boost_pu);
		if (pad2g_tune_pus)
			b43_radio_write(dev, R2057_PAD2G_TUNE_PUS_CORE0,
					pad2g_tune_pus);
		if (txmix2g_tune_boost_pu)
			b43_radio_write(dev, R2057_TXMIX2G_TUNE_BOOST_PU_CORE1,
					txmix2g_tune_boost_pu);
		if (pad2g_tune_pus)
			b43_radio_write(dev, R2057_PAD2G_TUNE_PUS_CORE1,
					pad2g_tune_pus);
	}
806 807 808 809 810 811 812 813 814 815 816

	usleep_range(50, 100);

	/* VCO calibration */
	b43_radio_mask(dev, R2057_RFPLL_MISC_EN, ~0x01);
	b43_radio_mask(dev, R2057_RFPLL_MISC_CAL_RESETN, ~0x04);
	b43_radio_set(dev, R2057_RFPLL_MISC_CAL_RESETN, 0x4);
	b43_radio_set(dev, R2057_RFPLL_MISC_EN, 0x01);
	usleep_range(300, 600);
}

817 818 819
/* Calibrate resistors in LPF of PLL?
 * http://bcm-v4.sipsolutions.net/PHY/radio205x_rcal
 */
820 821 822
static u8 b43_radio_2057_rcal(struct b43_wldev *dev)
{
	struct b43_phy *phy = &dev->phy;
823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838
	u16 saved_regs_phy[12];
	u16 saved_regs_phy_rf[6];
	u16 saved_regs_radio[2] = { };
	static const u16 phy_to_store[] = {
		B43_NPHY_RFCTL_RSSIO1, B43_NPHY_RFCTL_RSSIO2,
		B43_NPHY_RFCTL_LUT_TRSW_LO1, B43_NPHY_RFCTL_LUT_TRSW_LO2,
		B43_NPHY_RFCTL_RXG1, B43_NPHY_RFCTL_RXG2,
		B43_NPHY_RFCTL_TXG1, B43_NPHY_RFCTL_TXG2,
		B43_NPHY_REV7_RF_CTL_MISC_REG3, B43_NPHY_REV7_RF_CTL_MISC_REG4,
		B43_NPHY_REV7_RF_CTL_MISC_REG5, B43_NPHY_REV7_RF_CTL_MISC_REG6,
	};
	static const u16 phy_to_store_rf[] = {
		B43_NPHY_REV3_RFCTL_OVER0, B43_NPHY_REV3_RFCTL_OVER1,
		B43_NPHY_REV7_RF_CTL_OVER3, B43_NPHY_REV7_RF_CTL_OVER4,
		B43_NPHY_REV7_RF_CTL_OVER5, B43_NPHY_REV7_RF_CTL_OVER6,
	};
839
	u16 tmp;
840
	int i;
841

842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860
	/* Save */
	for (i = 0; i < ARRAY_SIZE(phy_to_store); i++)
		saved_regs_phy[i] = b43_phy_read(dev, phy_to_store[i]);
	for (i = 0; i < ARRAY_SIZE(phy_to_store_rf); i++)
		saved_regs_phy_rf[i] = b43_phy_read(dev, phy_to_store_rf[i]);

	/* Set */
	for (i = 0; i < ARRAY_SIZE(phy_to_store); i++)
		b43_phy_write(dev, phy_to_store[i], 0);
	b43_phy_write(dev, B43_NPHY_REV3_RFCTL_OVER0, 0x07ff);
	b43_phy_write(dev, B43_NPHY_REV3_RFCTL_OVER1, 0x07ff);
	b43_phy_write(dev, B43_NPHY_REV7_RF_CTL_OVER3, 0x07ff);
	b43_phy_write(dev, B43_NPHY_REV7_RF_CTL_OVER4, 0x07ff);
	b43_phy_write(dev, B43_NPHY_REV7_RF_CTL_OVER5, 0x007f);
	b43_phy_write(dev, B43_NPHY_REV7_RF_CTL_OVER6, 0x007f);

	switch (phy->radio_rev) {
	case 5:
		b43_phy_mask(dev, B43_NPHY_REV7_RF_CTL_OVER3, ~0x2);
861 862
		udelay(10);
		b43_radio_set(dev, R2057_IQTEST_SEL_PU, 0x1);
863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878
		b43_radio_maskset(dev, R2057v7_IQTEST_SEL_PU2, ~0x2, 0x1);
		break;
	case 9:
		b43_phy_set(dev, B43_NPHY_REV7_RF_CTL_OVER3, 0x2);
		b43_phy_set(dev, B43_NPHY_REV7_RF_CTL_MISC_REG3, 0x2);
		saved_regs_radio[0] = b43_radio_read(dev, R2057_IQTEST_SEL_PU);
		b43_radio_write(dev, R2057_IQTEST_SEL_PU, 0x11);
		break;
	case 14:
		saved_regs_radio[0] = b43_radio_read(dev, R2057_IQTEST_SEL_PU);
		saved_regs_radio[1] = b43_radio_read(dev, R2057v7_IQTEST_SEL_PU2);
		b43_phy_set(dev, B43_NPHY_REV7_RF_CTL_MISC_REG3, 0x2);
		b43_phy_set(dev, B43_NPHY_REV7_RF_CTL_OVER3, 0x2);
		b43_radio_write(dev, R2057v7_IQTEST_SEL_PU2, 0x2);
		b43_radio_write(dev, R2057_IQTEST_SEL_PU, 0x1);
		break;
879 880
	}

881
	/* Enable */
882 883
	b43_radio_set(dev, R2057_RCAL_CONFIG, 0x1);
	udelay(10);
884 885 886 887 888 889 890 891 892 893

	/* Start */
	b43_radio_set(dev, R2057_RCAL_CONFIG, 0x2);
	usleep_range(100, 200);

	/* Stop */
	b43_radio_mask(dev, R2057_RCAL_CONFIG, ~0x2);

	/* Wait and check for result */
	if (!b43_radio_wait_value(dev, R2057_RCAL_STATUS, 1, 1, 100, 1000000)) {
894 895 896 897
		b43err(dev->wl, "Radio 0x2057 rcal timeout\n");
		return 0;
	}
	tmp = b43_radio_read(dev, R2057_RCAL_STATUS) & 0x3E;
898 899

	/* Disable */
900 901
	b43_radio_mask(dev, R2057_RCAL_CONFIG, ~0x1);

902 903 904 905 906 907 908 909 910
	/* Restore */
	for (i = 0; i < ARRAY_SIZE(phy_to_store_rf); i++)
		b43_phy_write(dev, phy_to_store_rf[i], saved_regs_phy_rf[i]);
	for (i = 0; i < ARRAY_SIZE(phy_to_store); i++)
		b43_phy_write(dev, phy_to_store[i], saved_regs_phy[i]);

	switch (phy->radio_rev) {
	case 0 ... 4:
	case 6:
911 912 913
		b43_radio_maskset(dev, R2057_TEMPSENSE_CONFIG, ~0x3C, tmp);
		b43_radio_maskset(dev, R2057_BANDGAP_RCAL_TRIM, ~0xF0,
				  tmp << 2);
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		break;
	case 5:
		b43_radio_mask(dev, R2057_IPA2G_CASCONV_CORE0, ~0x1);
		b43_radio_mask(dev, R2057v7_IQTEST_SEL_PU2, ~0x2);
		break;
	case 9:
		b43_radio_write(dev, R2057_IQTEST_SEL_PU, saved_regs_radio[0]);
		break;
	case 14:
		b43_radio_write(dev, R2057_IQTEST_SEL_PU, saved_regs_radio[0]);
		b43_radio_write(dev, R2057v7_IQTEST_SEL_PU2, saved_regs_radio[1]);
		break;
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	}

	return tmp & 0x3e;
}

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/* Calibrate the internal RC oscillator?
 * http://bcm-v4.sipsolutions.net/PHY/radio2057_rccal
 */
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static u16 b43_radio_2057_rccal(struct b43_wldev *dev)
{
	struct b43_phy *phy = &dev->phy;
	bool special = (phy->radio_rev == 3 || phy->radio_rev == 4 ||
			phy->radio_rev == 6);
	u16 tmp;

941
	/* Setup cal */
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	if (special) {
		b43_radio_write(dev, R2057_RCCAL_MASTER, 0x61);
		b43_radio_write(dev, R2057_RCCAL_TRC0, 0xC0);
	} else {
946
		b43_radio_write(dev, R2057v7_RCCAL_MASTER, 0x61);
947
		b43_radio_write(dev, R2057_RCCAL_TRC0, 0xE9);
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	}
	b43_radio_write(dev, R2057_RCCAL_X1, 0x6E);
950 951

	/* Start, wait, stop */
952
	b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x55);
953
	if (!b43_radio_wait_value(dev, R2057_RCCAL_DONE_OSCCAP, 2, 2, 500,
954 955
				  5000000))
		b43dbg(dev->wl, "Radio 0x2057 rccal timeout\n");
956
	usleep_range(35, 70);
957
	b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x15);
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	usleep_range(70, 140);

	/* Setup cal */
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	if (special) {
		b43_radio_write(dev, R2057_RCCAL_MASTER, 0x69);
		b43_radio_write(dev, R2057_RCCAL_TRC0, 0xB0);
	} else {
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		b43_radio_write(dev, R2057v7_RCCAL_MASTER, 0x69);
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		b43_radio_write(dev, R2057_RCCAL_TRC0, 0xD5);
	}
	b43_radio_write(dev, R2057_RCCAL_X1, 0x6E);
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	/* Start, wait, stop */
	usleep_range(35, 70);
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	b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x55);
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	usleep_range(70, 140);
	if (!b43_radio_wait_value(dev, R2057_RCCAL_DONE_OSCCAP, 2, 2, 500,
975
				  5000000))
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		b43dbg(dev->wl, "Radio 0x2057 rccal timeout\n");
977
	usleep_range(35, 70);
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	b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x15);
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	usleep_range(70, 140);

	/* Setup cal */
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	if (special) {
		b43_radio_write(dev, R2057_RCCAL_MASTER, 0x73);
		b43_radio_write(dev, R2057_RCCAL_X1, 0x28);
		b43_radio_write(dev, R2057_RCCAL_TRC0, 0xB0);
	} else {
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		b43_radio_write(dev, R2057v7_RCCAL_MASTER, 0x73);
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		b43_radio_write(dev, R2057_RCCAL_X1, 0x6E);
		b43_radio_write(dev, R2057_RCCAL_TRC0, 0x99);
	}
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	/* Start, wait, stop */
	usleep_range(35, 70);
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	b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x55);
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	usleep_range(70, 140);
	if (!b43_radio_wait_value(dev, R2057_RCCAL_DONE_OSCCAP, 2, 2, 500,
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				  5000000)) {
		b43err(dev->wl, "Radio 0x2057 rcal timeout\n");
		return 0;
	}
	tmp = b43_radio_read(dev, R2057_RCCAL_DONE_OSCCAP);
1002
	usleep_range(35, 70);
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	b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x15);
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	usleep_range(70, 140);

	if (special)
		b43_radio_mask(dev, R2057_RCCAL_MASTER, ~0x1);
	else
		b43_radio_mask(dev, R2057v7_RCCAL_MASTER, ~0x1);

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	return tmp;
}

static void b43_radio_2057_init_pre(struct b43_wldev *dev)
{
	b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, ~B43_NPHY_RFCTL_CMD_CHIP0PU);
	/* Maybe wl meant to reset and set (order?) RFCTL_CMD_OEPORFORCE? */
	b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_OEPORFORCE);
	b43_phy_set(dev, B43_NPHY_RFCTL_CMD, ~B43_NPHY_RFCTL_CMD_OEPORFORCE);
	b43_phy_set(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_CHIP0PU);
}

static void b43_radio_2057_init_post(struct b43_wldev *dev)
{
	b43_radio_set(dev, R2057_XTALPUOVR_PINCTRL, 0x1);

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	if (0) /* FIXME: Is this BCM43217 specific? */
		b43_radio_set(dev, R2057_XTALPUOVR_PINCTRL, 0x2);

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	b43_radio_set(dev, R2057_RFPLL_MISC_CAL_RESETN, 0x78);
	b43_radio_set(dev, R2057_XTAL_CONFIG2, 0x80);
	mdelay(2);
	b43_radio_mask(dev, R2057_RFPLL_MISC_CAL_RESETN, ~0x78);
	b43_radio_mask(dev, R2057_XTAL_CONFIG2, ~0x80);

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	if (dev->phy.do_full_init) {
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		b43_radio_2057_rcal(dev);
		b43_radio_2057_rccal(dev);
	}
	b43_radio_mask(dev, R2057_RFPLL_MASTER, ~0x8);
}

/* http://bcm-v4.sipsolutions.net/802.11/Radio/2057/Init */
static void b43_radio_2057_init(struct b43_wldev *dev)
{
	b43_radio_2057_init_pre(dev);
	r2057_upload_inittabs(dev);
	b43_radio_2057_init_post(dev);
}

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/**************************************************
1052
 * Radio 0x2056
1053
 **************************************************/
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static void b43_chantab_radio_2056_upload(struct b43_wldev *dev,
				const struct b43_nphy_channeltab_entry_rev3 *e)
1057
{
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	b43_radio_write(dev, B2056_SYN_PLL_VCOCAL1, e->radio_syn_pll_vcocal1);
	b43_radio_write(dev, B2056_SYN_PLL_VCOCAL2, e->radio_syn_pll_vcocal2);
	b43_radio_write(dev, B2056_SYN_PLL_REFDIV, e->radio_syn_pll_refdiv);
	b43_radio_write(dev, B2056_SYN_PLL_MMD2, e->radio_syn_pll_mmd2);
	b43_radio_write(dev, B2056_SYN_PLL_MMD1, e->radio_syn_pll_mmd1);
	b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1,
					e->radio_syn_pll_loopfilter1);
	b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2,
					e->radio_syn_pll_loopfilter2);
	b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER3,
					e->radio_syn_pll_loopfilter3);
	b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4,
					e->radio_syn_pll_loopfilter4);
	b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER5,
					e->radio_syn_pll_loopfilter5);
	b43_radio_write(dev, B2056_SYN_RESERVED_ADDR27,
					e->radio_syn_reserved_addr27);
	b43_radio_write(dev, B2056_SYN_RESERVED_ADDR28,
					e->radio_syn_reserved_addr28);
	b43_radio_write(dev, B2056_SYN_RESERVED_ADDR29,
					e->radio_syn_reserved_addr29);
	b43_radio_write(dev, B2056_SYN_LOGEN_VCOBUF1,
					e->radio_syn_logen_vcobuf1);
	b43_radio_write(dev, B2056_SYN_LOGEN_MIXER2, e->radio_syn_logen_mixer2);
	b43_radio_write(dev, B2056_SYN_LOGEN_BUF3, e->radio_syn_logen_buf3);
	b43_radio_write(dev, B2056_SYN_LOGEN_BUF4, e->radio_syn_logen_buf4);

	b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAA_TUNE,
					e->radio_rx0_lnaa_tune);
	b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAG_TUNE,
					e->radio_rx0_lnag_tune);

	b43_radio_write(dev, B2056_TX0 | B2056_TX_INTPAA_BOOST_TUNE,
					e->radio_tx0_intpaa_boost_tune);
	b43_radio_write(dev, B2056_TX0 | B2056_TX_INTPAG_BOOST_TUNE,
					e->radio_tx0_intpag_boost_tune);
	b43_radio_write(dev, B2056_TX0 | B2056_TX_PADA_BOOST_TUNE,
					e->radio_tx0_pada_boost_tune);
	b43_radio_write(dev, B2056_TX0 | B2056_TX_PADG_BOOST_TUNE,
					e->radio_tx0_padg_boost_tune);
	b43_radio_write(dev, B2056_TX0 | B2056_TX_PGAA_BOOST_TUNE,
					e->radio_tx0_pgaa_boost_tune);
	b43_radio_write(dev, B2056_TX0 | B2056_TX_PGAG_BOOST_TUNE,
					e->radio_tx0_pgag_boost_tune);
	b43_radio_write(dev, B2056_TX0 | B2056_TX_MIXA_BOOST_TUNE,
					e->radio_tx0_mixa_boost_tune);
	b43_radio_write(dev, B2056_TX0 | B2056_TX_MIXG_BOOST_TUNE,
					e->radio_tx0_mixg_boost_tune);

	b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAA_TUNE,
					e->radio_rx1_lnaa_tune);
	b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAG_TUNE,
					e->radio_rx1_lnag_tune);

	b43_radio_write(dev, B2056_TX1 | B2056_TX_INTPAA_BOOST_TUNE,
					e->radio_tx1_intpaa_boost_tune);
	b43_radio_write(dev, B2056_TX1 | B2056_TX_INTPAG_BOOST_TUNE,
					e->radio_tx1_intpag_boost_tune);
	b43_radio_write(dev, B2056_TX1 | B2056_TX_PADA_BOOST_TUNE,
					e->radio_tx1_pada_boost_tune);
	b43_radio_write(dev, B2056_TX1 | B2056_TX_PADG_BOOST_TUNE,
					e->radio_tx1_padg_boost_tune);
	b43_radio_write(dev, B2056_TX1 | B2056_TX_PGAA_BOOST_TUNE,
					e->radio_tx1_pgaa_boost_tune);
	b43_radio_write(dev, B2056_TX1 | B2056_TX_PGAG_BOOST_TUNE,
					e->radio_tx1_pgag_boost_tune);
	b43_radio_write(dev, B2056_TX1 | B2056_TX_MIXA_BOOST_TUNE,
					e->radio_tx1_mixa_boost_tune);
	b43_radio_write(dev, B2056_TX1 | B2056_TX_MIXG_BOOST_TUNE,
					e->radio_tx1_mixg_boost_tune);
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}

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/* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2056Setup */
static void b43_radio_2056_setup(struct b43_wldev *dev,
				const struct b43_nphy_channeltab_entry_rev3 *e)
1133
{
1134
	struct b43_phy *phy = &dev->phy;
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Rafał Miłecki committed
1135
	struct ssb_sprom *sprom = dev->dev->bus_sprom;
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	enum ieee80211_band band = b43_current_band(dev->wl);
	u16 offset;
	u8 i;
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	u16 bias, cbias;
	u16 pag_boost, padg_boost, pgag_boost, mixg_boost;
	u16 paa_boost, pada_boost, pgaa_boost, mixa_boost;
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	bool is_pkg_fab_smic;
1143

1144
	B43_WARN_ON(dev->phy.rev < 3);
1145

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	is_pkg_fab_smic =
		((dev->dev->chip_id == BCMA_CHIP_ID_BCM43224 ||
		  dev->dev->chip_id == BCMA_CHIP_ID_BCM43225 ||
		  dev->dev->chip_id == BCMA_CHIP_ID_BCM43421) &&
		 dev->dev->chip_pkg == BCMA_PKG_ID_BCM43224_FAB_SMIC);

1152
	b43_chantab_radio_2056_upload(dev, e);
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	b2056_upload_syn_pll_cp2(dev, band == IEEE80211_BAND_5GHZ);

	if (sprom->boardflags2_lo & B43_BFL2_GPLL_WAR &&
	    b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
		b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1, 0x1F);
		b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2, 0x1F);
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		if (dev->dev->chip_id == BCMA_CHIP_ID_BCM4716 ||
		    dev->dev->chip_id == BCMA_CHIP_ID_BCM47162) {
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			b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x14);
			b43_radio_write(dev, B2056_SYN_PLL_CP2, 0);
		} else {
			b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x0B);
			b43_radio_write(dev, B2056_SYN_PLL_CP2, 0x14);
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		}
1167
	}
1168 1169 1170 1171 1172 1173 1174
	if (sprom->boardflags2_hi & B43_BFH2_GPLL_WAR2 &&
	    b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
		b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1, 0x1f);
		b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2, 0x1f);
		b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x0b);
		b43_radio_write(dev, B2056_SYN_PLL_CP2, 0x20);
	}
1175 1176 1177 1178 1179 1180
	if (sprom->boardflags2_lo & B43_BFL2_APLL_WAR &&
	    b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
		b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1, 0x1F);
		b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2, 0x1F);
		b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x05);
		b43_radio_write(dev, B2056_SYN_PLL_CP2, 0x0C);
1181
	}
1182

1183 1184 1185 1186 1187 1188 1189
	if (dev->phy.n->ipa2g_on && band == IEEE80211_BAND_2GHZ) {
		for (i = 0; i < 2; i++) {
			offset = i ? B2056_TX1 : B2056_TX0;
			if (dev->phy.rev >= 5) {
				b43_radio_write(dev,
					offset | B2056_TX_PADG_IDAC, 0xcc);

1190 1191
				if (dev->dev->chip_id == BCMA_CHIP_ID_BCM4716 ||
				    dev->dev->chip_id == BCMA_CHIP_ID_BCM47162) {
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					bias = 0x40;
					cbias = 0x45;
					pag_boost = 0x5;
					pgag_boost = 0x33;
					mixg_boost = 0x55;
				} else {
					bias = 0x25;
					cbias = 0x20;
1200 1201 1202 1203
					if (is_pkg_fab_smic) {
						bias = 0x2a;
						cbias = 0x38;
					}
1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231
					pag_boost = 0x4;
					pgag_boost = 0x03;
					mixg_boost = 0x65;
				}
				padg_boost = 0x77;

				b43_radio_write(dev,
					offset | B2056_TX_INTPAG_IMAIN_STAT,
					bias);
				b43_radio_write(dev,
					offset | B2056_TX_INTPAG_IAUX_STAT,
					bias);
				b43_radio_write(dev,
					offset | B2056_TX_INTPAG_CASCBIAS,
					cbias);
				b43_radio_write(dev,
					offset | B2056_TX_INTPAG_BOOST_TUNE,
					pag_boost);
				b43_radio_write(dev,
					offset | B2056_TX_PGAG_BOOST_TUNE,
					pgag_boost);
				b43_radio_write(dev,
					offset | B2056_TX_PADG_BOOST_TUNE,
					padg_boost);
				b43_radio_write(dev,
					offset | B2056_TX_MIXG_BOOST_TUNE,
					mixg_boost);
			} else {
1232
				bias = b43_is_40mhz(dev) ? 0x40 : 0x20;
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				b43_radio_write(dev,
					offset | B2056_TX_INTPAG_IMAIN_STAT,
					bias);
				b43_radio_write(dev,
					offset | B2056_TX_INTPAG_IAUX_STAT,
					bias);
				b43_radio_write(dev,
					offset | B2056_TX_INTPAG_CASCBIAS,
					0x30);
			}
			b43_radio_write(dev, offset | B2056_TX_PA_SPARE1, 0xee);
		}
	} else if (dev->phy.n->ipa5g_on && band == IEEE80211_BAND_5GHZ) {
1246
		u16 freq = phy->chandef->chan->center_freq;
1247 1248 1249 1250 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271
		if (freq < 5100) {
			paa_boost = 0xA;
			pada_boost = 0x77;
			pgaa_boost = 0xF;
			mixa_boost = 0xF;
		} else if (freq < 5340) {
			paa_boost = 0x8;
			pada_boost = 0x77;
			pgaa_boost = 0xFB;
			mixa_boost = 0xF;
		} else if (freq < 5650) {
			paa_boost = 0x0;
			pada_boost = 0x77;
			pgaa_boost = 0xB;
			mixa_boost = 0xF;
		} else {
			paa_boost = 0x0;
			pada_boost = 0x77;
			if (freq != 5825)
				pgaa_boost = -(freq - 18) / 36 + 168;
			else
				pgaa_boost = 6;
			mixa_boost = 0xF;
		}

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		cbias = is_pkg_fab_smic ? 0x35 : 0x30;

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		for (i = 0; i < 2; i++) {
			offset = i ? B2056_TX1 : B2056_TX0;

			b43_radio_write(dev,
				offset | B2056_TX_INTPAA_BOOST_TUNE, paa_boost);
			b43_radio_write(dev,
				offset | B2056_TX_PADA_BOOST_TUNE, pada_boost);
			b43_radio_write(dev,
				offset | B2056_TX_PGAA_BOOST_TUNE, pgaa_boost);
			b43_radio_write(dev,
				offset | B2056_TX_MIXA_BOOST_TUNE, mixa_boost);
			b43_radio_write(dev,
				offset | B2056_TX_TXSPARE1, 0x30);
			b43_radio_write(dev,
				offset | B2056_TX_PA_SPARE2, 0xee);
			b43_radio_write(dev,
				offset | B2056_TX_PADA_CASCBIAS, 0x03);
			b43_radio_write(dev,
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				offset | B2056_TX_INTPAA_IAUX_STAT, 0x30);
1293
			b43_radio_write(dev,
1294
				offset | B2056_TX_INTPAA_IMAIN_STAT, 0x30);
1295
			b43_radio_write(dev,
1296
				offset | B2056_TX_INTPAA_CASCBIAS, cbias);
1297
		}
1298
	}
1299

1300 1301 1302 1303 1304 1305 1306 1307
	udelay(50);
	/* VCO calibration */
	b43_radio_write(dev, B2056_SYN_PLL_VCOCAL12, 0x00);
	b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x38);
	b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x18);
	b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x38);
	b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x39);
	udelay(300);
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}

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static u8 b43_radio_2056_rcal(struct b43_wldev *dev)
{
	struct b43_phy *phy = &dev->phy;
	u16 mast2, tmp;

	if (phy->rev != 3)
		return 0;

	mast2 = b43_radio_read(dev, B2056_SYN_PLL_MAST2);
	b43_radio_write(dev, B2056_SYN_PLL_MAST2, mast2 | 0x7);

	udelay(10);
	b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x01);
	udelay(10);
	b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x09);

	if (!b43_radio_wait_value(dev, B2056_SYN_RCAL_CODE_OUT, 0x80, 0x80, 100,
				  1000000)) {
		b43err(dev->wl, "Radio recalibration timeout\n");
		return 0;
	}

	b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x01);
	tmp = b43_radio_read(dev, B2056_SYN_RCAL_CODE_OUT);
	b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x00);

	b43_radio_write(dev, B2056_SYN_PLL_MAST2, mast2);

	return tmp & 0x1f;
}

1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358 1359 1360 1361 1362
static void b43_radio_init2056_pre(struct b43_wldev *dev)
{
	b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
		     ~B43_NPHY_RFCTL_CMD_CHIP0PU);
	/* Maybe wl meant to reset and set (order?) RFCTL_CMD_OEPORFORCE? */
	b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
		     B43_NPHY_RFCTL_CMD_OEPORFORCE);
	b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
		    ~B43_NPHY_RFCTL_CMD_OEPORFORCE);
	b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
		    B43_NPHY_RFCTL_CMD_CHIP0PU);
}

static void b43_radio_init2056_post(struct b43_wldev *dev)
{
	b43_radio_set(dev, B2056_SYN_COM_CTRL, 0xB);
	b43_radio_set(dev, B2056_SYN_COM_PU, 0x2);
	b43_radio_set(dev, B2056_SYN_COM_RESET, 0x2);
	msleep(1);
	b43_radio_mask(dev, B2056_SYN_COM_RESET, ~0x2);
	b43_radio_mask(dev, B2056_SYN_PLL_MAST2, ~0xFC);
	b43_radio_mask(dev, B2056_SYN_RCCAL_CTRL0, ~0x1);
1363
	if (dev->phy.do_full_init)
1364
		b43_radio_2056_rcal(dev);
1365 1366
}

1367 1368 1369 1370 1371 1372
/*
 * Initialize a Broadcom 2056 N-radio
 * http://bcm-v4.sipsolutions.net/802.11/Radio/2056/Init
 */
static void b43_radio_init2056(struct b43_wldev *dev)
{
1373 1374 1375
	b43_radio_init2056_pre(dev);
	b2056_upload_inittabs(dev, 0, 0);
	b43_radio_init2056_post(dev);
1376 1377
}

1378 1379 1380 1381 1382 1383
/**************************************************
 * Radio 0x2055
 **************************************************/

static void b43_chantab_radio_upload(struct b43_wldev *dev,
				const struct b43_nphy_channeltab_entry_rev2 *e)
1384
{
1385 1386 1387 1388 1389
	b43_radio_write(dev, B2055_PLL_REF, e->radio_pll_ref);
	b43_radio_write(dev, B2055_RF_PLLMOD0, e->radio_rf_pllmod0);
	b43_radio_write(dev, B2055_RF_PLLMOD1, e->radio_rf_pllmod1);
	b43_radio_write(dev, B2055_VCO_CAPTAIL, e->radio_vco_captail);
	b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
1390

1391 1392 1393 1394 1395
	b43_radio_write(dev, B2055_VCO_CAL1, e->radio_vco_cal1);
	b43_radio_write(dev, B2055_VCO_CAL2, e->radio_vco_cal2);
	b43_radio_write(dev, B2055_PLL_LFC1, e->radio_pll_lfc1);
	b43_radio_write(dev, B2055_PLL_LFR1, e->radio_pll_lfr1);
	b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
1396

1397 1398 1399 1400 1401
	b43_radio_write(dev, B2055_PLL_LFC2, e->radio_pll_lfc2);
	b43_radio_write(dev, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf);
	b43_radio_write(dev, B2055_LGEN_TUNE1, e->radio_lgen_tune1);
	b43_radio_write(dev, B2055_LGEN_TUNE2, e->radio_lgen_tune2);
	b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
1402

1403 1404 1405 1406 1407
	b43_radio_write(dev, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune);
	b43_radio_write(dev, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune);
	b43_radio_write(dev, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1);
	b43_radio_write(dev, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn);
	b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
1408

1409 1410 1411 1412 1413
	b43_radio_write(dev, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim);
	b43_radio_write(dev, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune);
	b43_radio_write(dev, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune);
	b43_radio_write(dev, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1);
	b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
1414

1415 1416
	b43_radio_write(dev, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn);
	b43_radio_write(dev, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim);
1417 1418
}

1419 1420 1421
/* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2055Setup */
static void b43_radio_2055_setup(struct b43_wldev *dev,
				const struct b43_nphy_channeltab_entry_rev2 *e)
1422
{
1423
	B43_WARN_ON(dev->phy.rev >= 3);
1424

1425 1426 1427 1428 1429 1430 1431
	b43_chantab_radio_upload(dev, e);
	udelay(50);
	b43_radio_write(dev, B2055_VCO_CAL10, 0x05);
	b43_radio_write(dev, B2055_VCO_CAL10, 0x45);
	b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
	b43_radio_write(dev, B2055_VCO_CAL10, 0x65);
	udelay(300);
1432 1433
}

1434
static void b43_radio_init2055_pre(struct b43_wldev *dev)
1435
{
1436 1437 1438 1439 1440 1441 1442
	b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
		     ~B43_NPHY_RFCTL_CMD_PORFORCE);
	b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
		    B43_NPHY_RFCTL_CMD_CHIP0PU |
		    B43_NPHY_RFCTL_CMD_OEPORFORCE);
	b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
		    B43_NPHY_RFCTL_CMD_PORFORCE);
1443 1444
}

1445
static void b43_radio_init2055_post(struct b43_wldev *dev)
1446 1447
{
	struct b43_phy_n *nphy = dev->phy.n;
1448 1449
	struct ssb_sprom *sprom = dev->dev->bus_sprom;
	bool workaround = false;
1450

1451 1452
	if (sprom->revision < 4)
		workaround = (dev->dev->board_vendor != PCI_VENDOR_ID_BROADCOM
1453
			      && dev->dev->board_type == SSB_BOARD_CB2_4321
1454
			      && dev->dev->board_rev >= 0x41);
1455
	else
1456 1457
		workaround =
			!(sprom->boardflags2_lo & B43_BFL2_RXBB_INT_REG_DIS);
1458

1459 1460 1461 1462 1463 1464 1465 1466 1467 1468 1469 1470
	b43_radio_mask(dev, B2055_MASTER1, 0xFFF3);
	if (workaround) {
		b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
		b43_radio_mask(dev, B2055_C2_RX_BB_REG, 0x7F);
	}
	b43_radio_maskset(dev, B2055_RRCCAL_NOPTSEL, 0xFFC0, 0x2C);
	b43_radio_write(dev, B2055_CAL_MISC, 0x3C);
	b43_radio_mask(dev, B2055_CAL_MISC, 0xFFBE);
	b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80);
	b43_radio_set(dev, B2055_CAL_MISC, 0x1);
	msleep(1);
	b43_radio_set(dev, B2055_CAL_MISC, 0x40);
1471
	if (!b43_radio_wait_value(dev, B2055_CAL_COUT2, 0x80, 0x80, 10, 2000))
1472 1473 1474 1475 1476 1477 1478 1479 1480 1481 1482 1483 1484 1485 1486 1487 1488
		b43err(dev->wl, "radio post init timeout\n");
	b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F);
	b43_switch_channel(dev, dev->phy.channel);
	b43_radio_write(dev, B2055_C1_RX_BB_LPF, 0x9);
	b43_radio_write(dev, B2055_C2_RX_BB_LPF, 0x9);
	b43_radio_write(dev, B2055_C1_RX_BB_MIDACHP, 0x83);
	b43_radio_write(dev, B2055_C2_RX_BB_MIDACHP, 0x83);
	b43_radio_maskset(dev, B2055_C1_LNA_GAINBST, 0xFFF8, 0x6);
	b43_radio_maskset(dev, B2055_C2_LNA_GAINBST, 0xFFF8, 0x6);
	if (!nphy->gain_boost) {
		b43_radio_set(dev, B2055_C1_RX_RFSPC1, 0x2);
		b43_radio_set(dev, B2055_C2_RX_RFSPC1, 0x2);
	} else {
		b43_radio_mask(dev, B2055_C1_RX_RFSPC1, 0xFFFD);
		b43_radio_mask(dev, B2055_C2_RX_RFSPC1, 0xFFFD);
	}
	udelay(2);
1489 1490
}

1491 1492 1493 1494 1495
/*
 * Initialize a Broadcom 2055 N-radio
 * http://bcm-v4.sipsolutions.net/802.11/Radio/2055/Init
 */
static void b43_radio_init2055(struct b43_wldev *dev)
1496
{
1497 1498 1499 1500
	b43_radio_init2055_pre(dev);
	if (b43_status(dev) < B43_STAT_INITIALIZED) {
		/* Follow wl, not specs. Do not force uploading all regs */
		b2055_upload_inittab(dev, 0, 0);
1501
	} else {
1502 1503
		bool ghz5 = b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ;
		b2055_upload_inittab(dev, ghz5, 0);
1504
	}
1505
	b43_radio_init2055_post(dev);
1506 1507
}

1508 1509 1510
/**************************************************
 * Samples
 **************************************************/
1511

1512 1513 1514 1515 1516 1517 1518 1519 1520 1521 1522 1523 1524 1525 1526 1527 1528 1529 1530 1531 1532 1533 1534 1535 1536
/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/LoadSampleTable */
static int b43_nphy_load_samples(struct b43_wldev *dev,
					struct b43_c32 *samples, u16 len) {
	struct b43_phy_n *nphy = dev->phy.n;
	u16 i;
	u32 *data;

	data = kzalloc(len * sizeof(u32), GFP_KERNEL);
	if (!data) {
		b43err(dev->wl, "allocation for samples loading failed\n");
		return -ENOMEM;
	}
	if (nphy->hang_avoid)
		b43_nphy_stay_in_carrier_search(dev, 1);

	for (i = 0; i < len; i++) {
		data[i] = (samples[i].i & 0x3FF << 10);
		data[i] |= samples[i].q & 0x3FF;
	}
	b43_ntab_write_bulk(dev, B43_NTAB32(17, 0), len, data);

	kfree(data);
	if (nphy->hang_avoid)
		b43_nphy_stay_in_carrier_search(dev, 0);
	return 0;
1537 1538
}

1539 1540 1541
/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GenLoadSamples */
static u16 b43_nphy_gen_load_samples(struct b43_wldev *dev, u32 freq, u16 max,
					bool test)
1542
{
1543 1544 1545
	int i;
	u16 bw, len, rot, angle;
	struct b43_c32 *samples;
1546

1547
	bw = b43_is_40mhz(dev) ? 40 : 20;
1548
	len = bw << 3;
1549

1550 1551 1552 1553 1554
	if (test) {
		if (b43_phy_read(dev, B43_NPHY_BBCFG) & B43_NPHY_BBCFG_RSTRX)
			bw = 82;
		else
			bw = 80;
1555

1556
		if (b43_is_40mhz(dev))
1557 1558 1559
			bw <<= 1;

		len = bw << 1;
1560 1561
	}

1562 1563 1564 1565 1566 1567 1568
	samples = kcalloc(len, sizeof(struct b43_c32), GFP_KERNEL);
	if (!samples) {
		b43err(dev->wl, "allocation for samples generation failed\n");
		return 0;
	}
	rot = (((freq * 36) / bw) << 16) / 100;
	angle = 0;
1569

1570 1571 1572 1573 1574
	for (i = 0; i < len; i++) {
		samples[i] = b43_cordic(angle);
		angle += rot;
		samples[i].q = CORDIC_CONVERT(samples[i].q * max);
		samples[i].i = CORDIC_CONVERT(samples[i].i * max);
1575
	}
1576 1577 1578 1579

	i = b43_nphy_load_samples(dev, samples, len);
	kfree(samples);
	return (i < 0) ? 0 : len;
1580 1581
}

1582 1583
/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RunSamples */
static void b43_nphy_run_samples(struct b43_wldev *dev, u16 samps, u16 loops,
1584 1585
				 u16 wait, bool iqmode, bool dac_test,
				 bool modify_bbmult)
1586
{
1587
	struct b43_phy *phy = &dev->phy;
1588
	struct b43_phy_n *nphy = dev->phy.n;
1589
	int i;
1590 1591
	u16 seq_mode;
	u32 tmp;
1592

1593
	b43_nphy_stay_in_carrier_search(dev, true);
1594

1595
	if (phy->rev >= 7) {
1596 1597 1598 1599 1600 1601 1602 1603 1604 1605 1606 1607 1608 1609 1610 1611 1612
		bool lpf_bw3, lpf_bw4;

		lpf_bw3 = b43_phy_read(dev, B43_NPHY_REV7_RF_CTL_OVER3) & 0x80;
		lpf_bw4 = b43_phy_read(dev, B43_NPHY_REV7_RF_CTL_OVER3) & 0x80;

		if (lpf_bw3 || lpf_bw4) {
			/* TODO */
		} else {
			u16 value = b43_nphy_read_lpf_ctl(dev, 0);
			if (phy->rev >= 19)
				b43_nphy_rf_ctl_override_rev19(dev, 0x80, value,
							       0, false, 1);
			else
				b43_nphy_rf_ctl_override_rev7(dev, 0x80, value,
							      0, false, 1);
			nphy->lpf_bw_overrode_for_sample_play = true;
		}
1613 1614
	}

1615 1616 1617 1618
	if ((nphy->bb_mult_save & 0x80000000) == 0) {
		tmp = b43_ntab_read(dev, B43_NTAB16(15, 87));
		nphy->bb_mult_save = (tmp & 0xFFFF) | 0x80000000;
	}
1619

1620 1621 1622 1623
	if (modify_bbmult) {
		tmp = !b43_is_40mhz(dev) ? 0x6464 : 0x4747;
		b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
	}
1624

1625
	b43_phy_write(dev, B43_NPHY_SAMP_DEPCNT, (samps - 1));
1626

1627 1628 1629 1630
	if (loops != 0xFFFF)
		b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, (loops - 1));
	else
		b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, loops);
1631

1632
	b43_phy_write(dev, B43_NPHY_SAMP_WAITCNT, wait);
1633

1634
	seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
1635

1636 1637 1638 1639 1640
	b43_phy_set(dev, B43_NPHY_RFSEQMODE, B43_NPHY_RFSEQMODE_CAOVER);
	if (iqmode) {
		b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
		b43_phy_set(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8000);
	} else {
1641 1642
		tmp = dac_test ? 5 : 1;
		b43_phy_write(dev, B43_NPHY_SAMP_CMD, tmp);
1643 1644
	}
	for (i = 0; i < 100; i++) {
1645
		if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & 1)) {
1646 1647
			i = 0;
			break;
1648
		}
1649
		udelay(10);
1650
	}
1651 1652
	if (i)
		b43err(dev->wl, "run samples timeout\n");
1653

1654
	b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
1655 1656

	b43_nphy_stay_in_carrier_search(dev, false);
1657 1658
}

1659 1660 1661 1662 1663 1664
/**************************************************
 * RSSI
 **************************************************/

/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ScaleOffsetRssi */
static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale,
1665 1666
					s8 offset, u8 core,
					enum n_rail_type rail,
1667
					enum n_rssi_type rssi_type)
1668
{
1669 1670 1671
	u16 tmp;
	bool core1or5 = (core == 1) || (core == 5);
	bool core2or5 = (core == 2) || (core == 5);
1672

1673 1674
	offset = clamp_val(offset, -32, 31);
	tmp = ((scale & 0x3F) << 8) | (offset & 0x3F);
1675

1676
	switch (rssi_type) {
1677
	case N_RSSI_NB:
1678 1679 1680 1681 1682 1683 1684 1685 1686
		if (core1or5 && rail == N_RAIL_I)
			b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, tmp);
		if (core1or5 && rail == N_RAIL_Q)
			b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, tmp);
		if (core2or5 && rail == N_RAIL_I)
			b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, tmp);
		if (core2or5 && rail == N_RAIL_Q)
			b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, tmp);
		break;
1687
	case N_RSSI_W1:
1688 1689 1690 1691 1692 1693 1694 1695 1696
		if (core1or5 && rail == N_RAIL_I)
			b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, tmp);
		if (core1or5 && rail == N_RAIL_Q)
			b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, tmp);
		if (core2or5 && rail == N_RAIL_I)
			b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, tmp);
		if (core2or5 && rail == N_RAIL_Q)
			b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, tmp);
		break;
1697
	case N_RSSI_W2:
1698 1699 1700 1701 1702 1703 1704 1705 1706
		if (core1or5 && rail == N_RAIL_I)
			b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, tmp);
		if (core1or5 && rail == N_RAIL_Q)
			b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, tmp);
		if (core2or5 && rail == N_RAIL_I)
			b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, tmp);
		if (core2or5 && rail == N_RAIL_Q)
			b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, tmp);
		break;
1707
	case N_RSSI_TBD:
1708 1709 1710 1711 1712 1713 1714 1715 1716
		if (core1or5 && rail == N_RAIL_I)
			b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TBD, tmp);
		if (core1or5 && rail == N_RAIL_Q)
			b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TBD, tmp);
		if (core2or5 && rail == N_RAIL_I)
			b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TBD, tmp);
		if (core2or5 && rail == N_RAIL_Q)
			b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TBD, tmp);
		break;
1717
	case N_RSSI_IQ:
1718 1719 1720 1721 1722 1723 1724 1725 1726
		if (core1or5 && rail == N_RAIL_I)
			b43_phy_write(dev, B43_NPHY_RSSIMC_0I_PWRDET, tmp);
		if (core1or5 && rail == N_RAIL_Q)
			b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_PWRDET, tmp);
		if (core2or5 && rail == N_RAIL_I)
			b43_phy_write(dev, B43_NPHY_RSSIMC_1I_PWRDET, tmp);
		if (core2or5 && rail == N_RAIL_Q)
			b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_PWRDET, tmp);
		break;
1727
	case N_RSSI_TSSI_2G:
1728 1729 1730 1731 1732
		if (core1or5)
			b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TSSI, tmp);
		if (core2or5)
			b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TSSI, tmp);
		break;
1733
	case N_RSSI_TSSI_5G:
1734 1735 1736 1737 1738 1739
		if (core1or5)
			b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TSSI, tmp);
		if (core2or5)
			b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TSSI, tmp);
		break;
	}
1740 1741
}

1742 1743 1744 1745 1746 1747
static void b43_nphy_rssi_select_rev19(struct b43_wldev *dev, u8 code,
				       enum n_rssi_type rssi_type)
{
	/* TODO */
}

1748 1749
static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code,
				      enum n_rssi_type rssi_type)
1750
{
1751 1752
	u8 i;
	u16 reg, val;
1753

1754 1755 1756 1757 1758 1759 1760 1761 1762 1763 1764 1765 1766
	if (code == 0) {
		b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, 0xFDFF);
		b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, 0xFDFF);
		b43_phy_mask(dev, B43_NPHY_AFECTL_C1, 0xFCFF);
		b43_phy_mask(dev, B43_NPHY_AFECTL_C2, 0xFCFF);
		b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S0, 0xFFDF);
		b43_phy_mask(dev, B43_NPHY_TXF_40CO_B32S1, 0xFFDF);
		b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0xFFC3);
		b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0xFFC3);
	} else {
		for (i = 0; i < 2; i++) {
			if ((code == 1 && i == 1) || (code == 2 && !i))
				continue;
1767

1768 1769 1770
			reg = (i == 0) ?
				B43_NPHY_AFECTL_OVER1 : B43_NPHY_AFECTL_OVER;
			b43_phy_maskset(dev, reg, 0xFDFF, 0x0200);
1771

1772 1773 1774
			if (rssi_type == N_RSSI_W1 ||
			    rssi_type == N_RSSI_W2 ||
			    rssi_type == N_RSSI_NB) {
1775 1776 1777 1778
				reg = (i == 0) ?
					B43_NPHY_AFECTL_C1 :
					B43_NPHY_AFECTL_C2;
				b43_phy_maskset(dev, reg, 0xFCFF, 0);
1779

1780 1781 1782 1783
				reg = (i == 0) ?
					B43_NPHY_RFCTL_LUT_TRSW_UP1 :
					B43_NPHY_RFCTL_LUT_TRSW_UP2;
				b43_phy_maskset(dev, reg, 0xFFC3, 0);
1784

1785
				if (rssi_type == N_RSSI_W1)
1786
					val = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 4 : 8;
1787
				else if (rssi_type == N_RSSI_W2)
1788 1789 1790 1791
					val = 16;
				else
					val = 32;
				b43_phy_set(dev, reg, val);
1792

1793 1794 1795 1796 1797
				reg = (i == 0) ?
					B43_NPHY_TXF_40CO_B1S0 :
					B43_NPHY_TXF_40CO_B32S1;
				b43_phy_set(dev, reg, 0x0020);
			} else {
1798
				if (rssi_type == N_RSSI_TBD)
1799
					val = 0x0100;
1800
				else if (rssi_type == N_RSSI_IQ)
1801 1802 1803
					val = 0x0200;
				else
					val = 0x0300;
1804

1805 1806 1807
				reg = (i == 0) ?
					B43_NPHY_AFECTL_C1 :
					B43_NPHY_AFECTL_C2;
1808

1809 1810
				b43_phy_maskset(dev, reg, 0xFCFF, val);
				b43_phy_maskset(dev, reg, 0xF3FF, val << 2);
1811

1812 1813
				if (rssi_type != N_RSSI_IQ &&
				    rssi_type != N_RSSI_TBD) {
1814 1815
					enum ieee80211_band band =
						b43_current_band(dev->wl);
1816

1817 1818 1819 1820 1821 1822 1823 1824 1825
					if (dev->phy.rev < 7) {
						if (b43_nphy_ipa(dev))
							val = (band == IEEE80211_BAND_5GHZ) ? 0xC : 0xE;
						else
							val = 0x11;
						reg = (i == 0) ? B2056_TX0 : B2056_TX1;
						reg |= B2056_TX_TX_SSI_MUX;
						b43_radio_write(dev, reg, val);
					}
1826

1827 1828 1829 1830 1831 1832 1833
					reg = (i == 0) ?
						B43_NPHY_AFECTL_OVER1 :
						B43_NPHY_AFECTL_OVER;
					b43_phy_set(dev, reg, 0x0200);
				}
			}
		}
1834 1835 1836
	}
}

1837 1838
static void b43_nphy_rev2_rssi_select(struct b43_wldev *dev, u8 code,
				      enum n_rssi_type rssi_type)
1839
{
1840
	u16 val;
1841
	bool rssi_w1_w2_nb = false;
1842

1843 1844 1845 1846
	switch (rssi_type) {
	case N_RSSI_W1:
	case N_RSSI_W2:
	case N_RSSI_NB:
1847
		val = 0;
1848 1849 1850
		rssi_w1_w2_nb = true;
		break;
	case N_RSSI_TBD:
1851
		val = 1;
1852 1853
		break;
	case N_RSSI_IQ:
1854
		val = 2;
1855 1856
		break;
	default:
1857
		val = 3;
1858
	}
1859

1860 1861 1862
	val = (val << 12) | (val << 14);
	b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, val);
	b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, val);
1863

1864
	if (rssi_w1_w2_nb) {
1865
		b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO1, 0xFFCF,
1866
				(rssi_type + 1) << 4);
1867
		b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO2, 0xFFCF,
1868
				(rssi_type + 1) << 4);
1869 1870
	}

1871 1872
	if (code == 0) {
		b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x3000);
1873
		if (rssi_w1_w2_nb) {
1874 1875 1876 1877 1878 1879 1880 1881 1882 1883 1884 1885 1886 1887 1888
			b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
				~(B43_NPHY_RFCTL_CMD_RXEN |
				  B43_NPHY_RFCTL_CMD_CORESEL));
			b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
				~(0x1 << 12 |
				  0x1 << 5 |
				  0x1 << 1 |
				  0x1));
			b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
				~B43_NPHY_RFCTL_CMD_START);
			udelay(20);
			b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
		}
	} else {
		b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x3000);
1889
		if (rssi_w1_w2_nb) {
1890 1891 1892 1893 1894 1895 1896 1897 1898 1899 1900 1901 1902 1903
			b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
				~(B43_NPHY_RFCTL_CMD_RXEN |
				  B43_NPHY_RFCTL_CMD_CORESEL),
				(B43_NPHY_RFCTL_CMD_RXEN |
				 code << B43_NPHY_RFCTL_CMD_CORESEL_SHIFT));
			b43_phy_set(dev, B43_NPHY_RFCTL_OVER,
				(0x1 << 12 |
				  0x1 << 5 |
				  0x1 << 1 |
				  0x1));
			b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
				B43_NPHY_RFCTL_CMD_START);
			udelay(20);
			b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
1904 1905 1906 1907
		}
	}
}

1908
/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSISel */
1909 1910
static void b43_nphy_rssi_select(struct b43_wldev *dev, u8 code,
				 enum n_rssi_type type)
1911
{
1912 1913 1914
	if (dev->phy.rev >= 19)
		b43_nphy_rssi_select_rev19(dev, code, type);
	else if (dev->phy.rev >= 3)
1915 1916 1917 1918
		b43_nphy_rev3_rssi_select(dev, code, type);
	else
		b43_nphy_rev2_rssi_select(dev, code, type);
}
1919

1920
/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRssi2055Vcm */
1921 1922
static void b43_nphy_set_rssi_2055_vcm(struct b43_wldev *dev,
				       enum n_rssi_type rssi_type, u8 *buf)
1923 1924
{
	int i;
1925
	for (i = 0; i < 2; i++) {
1926
		if (rssi_type == N_RSSI_NB) {
1927 1928 1929 1930 1931 1932 1933 1934 1935 1936 1937
			if (i == 0) {
				b43_radio_maskset(dev, B2055_C1_B0NB_RSSIVCM,
						  0xFC, buf[0]);
				b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
						  0xFC, buf[1]);
			} else {
				b43_radio_maskset(dev, B2055_C2_B0NB_RSSIVCM,
						  0xFC, buf[2 * i]);
				b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
						  0xFC, buf[2 * i + 1]);
			}
1938
		} else {
1939 1940 1941 1942 1943 1944
			if (i == 0)
				b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
						  0xF3, buf[0] << 2);
			else
				b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
						  0xF3, buf[2 * i + 1] << 2);
1945 1946 1947 1948
		}
	}
}

1949
/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PollRssi */
1950 1951
static int b43_nphy_poll_rssi(struct b43_wldev *dev, enum n_rssi_type rssi_type,
			      s32 *buf, u8 nsamp)
1952
{
1953 1954 1955 1956
	int i;
	int out;
	u16 save_regs_phy[9];
	u16 s[2];
1957

1958 1959
	/* TODO: rev7+ is treated like rev3+, what about rev19+? */

1960
	if (dev->phy.rev >= 3) {
1961 1962 1963
		save_regs_phy[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
		save_regs_phy[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
		save_regs_phy[2] = b43_phy_read(dev,
1964
						B43_NPHY_RFCTL_LUT_TRSW_UP1);
1965
		save_regs_phy[3] = b43_phy_read(dev,
1966 1967 1968 1969 1970 1971
						B43_NPHY_RFCTL_LUT_TRSW_UP2);
		save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
		save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
		save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S0);
		save_regs_phy[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B32S1);
		save_regs_phy[8] = 0;
1972
	} else {
1973 1974 1975 1976 1977 1978 1979 1980 1981 1982
		save_regs_phy[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
		save_regs_phy[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
		save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
		save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_RFCTL_CMD);
		save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
		save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
		save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
		save_regs_phy[7] = 0;
		save_regs_phy[8] = 0;
	}
1983

1984
	b43_nphy_rssi_select(dev, 5, rssi_type);
1985

1986 1987 1988 1989
	if (dev->phy.rev < 2) {
		save_regs_phy[8] = b43_phy_read(dev, B43_NPHY_GPIO_SEL);
		b43_phy_write(dev, B43_NPHY_GPIO_SEL, 5);
	}
1990

1991 1992 1993 1994 1995 1996 1997
	for (i = 0; i < 4; i++)
		buf[i] = 0;

	for (i = 0; i < nsamp; i++) {
		if (dev->phy.rev < 2) {
			s[0] = b43_phy_read(dev, B43_NPHY_GPIO_LOOUT);
			s[1] = b43_phy_read(dev, B43_NPHY_GPIO_HIOUT);
1998
		} else {
1999 2000
			s[0] = b43_phy_read(dev, B43_NPHY_RSSI1);
			s[1] = b43_phy_read(dev, B43_NPHY_RSSI2);
2001 2002
		}

2003 2004 2005 2006 2007 2008 2009
		buf[0] += ((s8)((s[0] & 0x3F) << 2)) >> 2;
		buf[1] += ((s8)(((s[0] >> 8) & 0x3F) << 2)) >> 2;
		buf[2] += ((s8)((s[1] & 0x3F) << 2)) >> 2;
		buf[3] += ((s8)(((s[1] >> 8) & 0x3F) << 2)) >> 2;
	}
	out = (buf[0] & 0xFF) << 24 | (buf[1] & 0xFF) << 16 |
		(buf[2] & 0xFF) << 8 | (buf[3] & 0xFF);
2010

2011 2012
	if (dev->phy.rev < 2)
		b43_phy_write(dev, B43_NPHY_GPIO_SEL, save_regs_phy[8]);
2013

2014
	if (dev->phy.rev >= 3) {
2015 2016
		b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[0]);
		b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[1]);
2017
		b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1,
2018
				save_regs_phy[2]);
2019
		b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2,
2020
				save_regs_phy[3]);
2021 2022 2023 2024 2025 2026 2027 2028 2029 2030 2031 2032 2033
		b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, save_regs_phy[4]);
		b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[5]);
		b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, save_regs_phy[6]);
		b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, save_regs_phy[7]);
	} else {
		b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[0]);
		b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[1]);
		b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[2]);
		b43_phy_write(dev, B43_NPHY_RFCTL_CMD, save_regs_phy[3]);
		b43_phy_write(dev, B43_NPHY_RFCTL_OVER, save_regs_phy[4]);
		b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, save_regs_phy[5]);
		b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, save_regs_phy[6]);
	}
2034

2035 2036
	return out;
}
2037

2038 2039 2040
/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICalRev3 */
static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
{
2041
	struct b43_phy *phy = &dev->phy;
2042 2043 2044
	struct b43_phy_n *nphy = dev->phy.n;

	u16 saved_regs_phy_rfctl[2];
2045 2046
	u16 saved_regs_phy[22];
	u16 regs_to_store_rev3[] = {
2047 2048 2049 2050 2051 2052 2053 2054
		B43_NPHY_AFECTL_OVER1, B43_NPHY_AFECTL_OVER,
		B43_NPHY_AFECTL_C1, B43_NPHY_AFECTL_C2,
		B43_NPHY_TXF_40CO_B1S1, B43_NPHY_RFCTL_OVER,
		B43_NPHY_TXF_40CO_B1S0, B43_NPHY_TXF_40CO_B32S1,
		B43_NPHY_RFCTL_CMD,
		B43_NPHY_RFCTL_LUT_TRSW_UP1, B43_NPHY_RFCTL_LUT_TRSW_UP2,
		B43_NPHY_RFCTL_RSSIO1, B43_NPHY_RFCTL_RSSIO2
	};
2055 2056 2057 2058
	u16 regs_to_store_rev7[] = {
		B43_NPHY_AFECTL_OVER1, B43_NPHY_AFECTL_OVER,
		B43_NPHY_AFECTL_C1, B43_NPHY_AFECTL_C2,
		B43_NPHY_TXF_40CO_B1S1, B43_NPHY_RFCTL_OVER,
2059 2060
		B43_NPHY_REV7_RF_CTL_OVER3, B43_NPHY_REV7_RF_CTL_OVER4,
		B43_NPHY_REV7_RF_CTL_OVER5, B43_NPHY_REV7_RF_CTL_OVER6,
2061 2062 2063 2064
		0x2ff,
		B43_NPHY_TXF_40CO_B1S0, B43_NPHY_TXF_40CO_B32S1,
		B43_NPHY_RFCTL_CMD,
		B43_NPHY_RFCTL_LUT_TRSW_UP1, B43_NPHY_RFCTL_LUT_TRSW_UP2,
2065 2066
		B43_NPHY_REV7_RF_CTL_MISC_REG3, B43_NPHY_REV7_RF_CTL_MISC_REG4,
		B43_NPHY_REV7_RF_CTL_MISC_REG5, B43_NPHY_REV7_RF_CTL_MISC_REG6,
2067 2068 2069 2070
		B43_NPHY_RFCTL_RSSIO1, B43_NPHY_RFCTL_RSSIO2
	};
	u16 *regs_to_store;
	int regs_amount;
2071 2072 2073 2074 2075 2076 2077

	u16 class;

	u16 clip_state[2];
	u16 clip_off[2] = { 0xFFFF, 0xFFFF };

	u8 vcm_final = 0;
2078
	s32 offset[4];
2079 2080 2081 2082 2083 2084 2085 2086 2087
	s32 results[8][4] = { };
	s32 results_min[4] = { };
	s32 poll_results[4] = { };

	u16 *rssical_radio_regs = NULL;
	u16 *rssical_phy_regs = NULL;

	u16 r; /* routing */
	u8 rx_core_state;
2088
	int core, i, j, vcm;
2089

2090 2091 2092 2093 2094 2095 2096 2097 2098
	if (dev->phy.rev >= 7) {
		regs_to_store = regs_to_store_rev7;
		regs_amount = ARRAY_SIZE(regs_to_store_rev7);
	} else {
		regs_to_store = regs_to_store_rev3;
		regs_amount = ARRAY_SIZE(regs_to_store_rev3);
	}
	BUG_ON(regs_amount > ARRAY_SIZE(saved_regs_phy));

2099 2100 2101 2102 2103 2104 2105
	class = b43_nphy_classifier(dev, 0, 0);
	b43_nphy_classifier(dev, 7, 4);
	b43_nphy_read_clip_detection(dev, clip_state);
	b43_nphy_write_clip_detection(dev, clip_off);

	saved_regs_phy_rfctl[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
	saved_regs_phy_rfctl[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
2106
	for (i = 0; i < regs_amount; i++)
2107 2108
		saved_regs_phy[i] = b43_phy_read(dev, regs_to_store[i]);

2109 2110
	b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_OFF, 0, 7);
	b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, 1, 7);
2111 2112

	if (dev->phy.rev >= 7) {
2113 2114 2115 2116 2117 2118 2119 2120
		b43_nphy_rf_ctl_override_one_to_many(dev,
						     N_RF_CTL_OVER_CMD_RXRF_PU,
						     0, 0, false);
		b43_nphy_rf_ctl_override_one_to_many(dev,
						     N_RF_CTL_OVER_CMD_RX_PU,
						     1, 0, false);
		b43_nphy_rf_ctl_override_rev7(dev, 0x80, 1, 0, false, 0);
		b43_nphy_rf_ctl_override_rev7(dev, 0x80, 1, 0, false, 0);
2121
		if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2122 2123 2124 2125
			b43_nphy_rf_ctl_override_rev7(dev, 0x20, 0, 0, false,
						      0);
			b43_nphy_rf_ctl_override_rev7(dev, 0x10, 1, 0, false,
						      0);
2126
		} else {
2127 2128 2129 2130
			b43_nphy_rf_ctl_override_rev7(dev, 0x10, 0, 0, false,
						      0);
			b43_nphy_rf_ctl_override_rev7(dev, 0x20, 1, 0, false,
						      0);
2131
		}
2132
	} else {
2133 2134 2135 2136 2137 2138 2139 2140 2141 2142 2143
		b43_nphy_rf_ctl_override(dev, 0x1, 0, 0, false);
		b43_nphy_rf_ctl_override(dev, 0x2, 1, 0, false);
		b43_nphy_rf_ctl_override(dev, 0x80, 1, 0, false);
		b43_nphy_rf_ctl_override(dev, 0x40, 1, 0, false);
		if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
			b43_nphy_rf_ctl_override(dev, 0x20, 0, 0, false);
			b43_nphy_rf_ctl_override(dev, 0x10, 1, 0, false);
		} else {
			b43_nphy_rf_ctl_override(dev, 0x10, 0, 0, false);
			b43_nphy_rf_ctl_override(dev, 0x20, 1, 0, false);
		}
2144 2145 2146 2147 2148 2149 2150
	}

	rx_core_state = b43_nphy_get_rx_core_state(dev);
	for (core = 0; core < 2; core++) {
		if (!(rx_core_state & (1 << core)))
			continue;
		r = core ? B2056_RX1 : B2056_RX0;
2151 2152 2153 2154
		b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1, N_RAIL_I,
					   N_RSSI_NB);
		b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1, N_RAIL_Q,
					   N_RSSI_NB);
2155 2156 2157

		/* Grab RSSI results for every possible VCM */
		for (vcm = 0; vcm < 8; vcm++) {
2158
			if (dev->phy.rev >= 7)
2159 2160 2161 2162
				b43_radio_maskset(dev,
						  core ? R2057_NB_MASTER_CORE1 :
							 R2057_NB_MASTER_CORE0,
						  ~R2057_VCM_MASK, vcm);
2163 2164 2165
			else
				b43_radio_maskset(dev, r | B2056_RX_RSSI_MISC,
						  0xE3, vcm << 2);
2166
			b43_nphy_poll_rssi(dev, N_RSSI_NB, results[vcm], 8);
2167
		}
2168 2169

		/* Find out which VCM got the best results */
2170
		for (i = 0; i < 4; i += 2) {
2171
			s32 currd;
2172
			s32 mind = 0x100000;
2173 2174 2175 2176
			s32 minpoll = 249;
			u8 minvcm = 0;
			if (2 * core != i)
				continue;
2177 2178 2179 2180 2181 2182
			for (vcm = 0; vcm < 8; vcm++) {
				currd = results[vcm][i] * results[vcm][i] +
					results[vcm][i + 1] * results[vcm][i];
				if (currd < mind) {
					mind = currd;
					minvcm = vcm;
2183
				}
2184 2185
				if (results[vcm][i] < minpoll)
					minpoll = results[vcm][i];
2186 2187 2188 2189
			}
			vcm_final = minvcm;
			results_min[i] = minpoll;
		}
2190 2191

		/* Select the best VCM */
2192
		if (dev->phy.rev >= 7)
2193 2194 2195 2196
			b43_radio_maskset(dev,
					  core ? R2057_NB_MASTER_CORE1 :
						 R2057_NB_MASTER_CORE0,
					  ~R2057_VCM_MASK, vcm);
2197 2198 2199
		else
			b43_radio_maskset(dev, r | B2056_RX_RSSI_MISC,
					  0xE3, vcm_final << 2);
2200

2201 2202 2203 2204 2205 2206 2207 2208 2209 2210 2211 2212
		for (i = 0; i < 4; i++) {
			if (core != i / 2)
				continue;
			offset[i] = -results[vcm_final][i];
			if (offset[i] < 0)
				offset[i] = -((abs(offset[i]) + 4) / 8);
			else
				offset[i] = (offset[i] + 4) / 8;
			if (results_min[i] == 248)
				offset[i] = -32;
			b43_nphy_scale_offset_rssi(dev, 0, offset[i],
						   (i / 2 == 0) ? 1 : 2,
2213
						   (i % 2 == 0) ? N_RAIL_I : N_RAIL_Q,
2214
						   N_RSSI_NB);
2215 2216
		}
	}
2217

2218 2219 2220 2221
	for (core = 0; core < 2; core++) {
		if (!(rx_core_state & (1 << core)))
			continue;
		for (i = 0; i < 2; i++) {
2222 2223 2224 2225
			b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1,
						   N_RAIL_I, i);
			b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1,
						   N_RAIL_Q, i);
2226 2227
			b43_nphy_poll_rssi(dev, i, poll_results, 8);
			for (j = 0; j < 4; j++) {
2228
				if (j / 2 == core) {
2229
					offset[j] = 232 - poll_results[j];
2230 2231 2232 2233 2234 2235 2236
					if (offset[j] < 0)
						offset[j] = -(abs(offset[j] + 4) / 8);
					else
						offset[j] = (offset[j] + 4) / 8;
					b43_nphy_scale_offset_rssi(dev, 0,
						offset[2 * core], core + 1, j % 2, i);
				}
2237 2238 2239 2240 2241 2242 2243 2244 2245 2246 2247 2248 2249 2250 2251
			}
		}
	}

	b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, saved_regs_phy_rfctl[0]);
	b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, saved_regs_phy_rfctl[1]);

	b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);

	b43_phy_set(dev, B43_NPHY_TXF_40CO_B1S1, 0x1);
	b43_phy_set(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_START);
	b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1, ~0x1);

	b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1);
	b43_phy_set(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_RXTX);
2252
	b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
2253

2254
	for (i = 0; i < regs_amount; i++)
2255 2256 2257 2258 2259 2260 2261 2262 2263 2264
		b43_phy_write(dev, regs_to_store[i], saved_regs_phy[i]);

	/* Store for future configuration */
	if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
		rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G;
		rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G;
	} else {
		rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G;
		rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G;
	}
2265
	if (dev->phy.rev >= 7) {
2266 2267 2268 2269
		rssical_radio_regs[0] = b43_radio_read(dev,
						       R2057_NB_MASTER_CORE0);
		rssical_radio_regs[1] = b43_radio_read(dev,
						       R2057_NB_MASTER_CORE1);
2270 2271 2272 2273 2274 2275
	} else {
		rssical_radio_regs[0] = b43_radio_read(dev, B2056_RX0 |
						       B2056_RX_RSSI_MISC);
		rssical_radio_regs[1] = b43_radio_read(dev, B2056_RX1 |
						       B2056_RX_RSSI_MISC);
	}
2276 2277 2278 2279 2280 2281 2282 2283 2284 2285 2286 2287 2288 2289 2290
	rssical_phy_regs[0] = b43_phy_read(dev, B43_NPHY_RSSIMC_0I_RSSI_Z);
	rssical_phy_regs[1] = b43_phy_read(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z);
	rssical_phy_regs[2] = b43_phy_read(dev, B43_NPHY_RSSIMC_1I_RSSI_Z);
	rssical_phy_regs[3] = b43_phy_read(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z);
	rssical_phy_regs[4] = b43_phy_read(dev, B43_NPHY_RSSIMC_0I_RSSI_X);
	rssical_phy_regs[5] = b43_phy_read(dev, B43_NPHY_RSSIMC_0Q_RSSI_X);
	rssical_phy_regs[6] = b43_phy_read(dev, B43_NPHY_RSSIMC_1I_RSSI_X);
	rssical_phy_regs[7] = b43_phy_read(dev, B43_NPHY_RSSIMC_1Q_RSSI_X);
	rssical_phy_regs[8] = b43_phy_read(dev, B43_NPHY_RSSIMC_0I_RSSI_Y);
	rssical_phy_regs[9] = b43_phy_read(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y);
	rssical_phy_regs[10] = b43_phy_read(dev, B43_NPHY_RSSIMC_1I_RSSI_Y);
	rssical_phy_regs[11] = b43_phy_read(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y);

	/* Remember for which channel we store configuration */
	if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
2291
		nphy->rssical_chanspec_2G.center_freq = phy->chandef->chan->center_freq;
2292
	else
2293
		nphy->rssical_chanspec_5G.center_freq = phy->chandef->chan->center_freq;
2294 2295 2296 2297 2298 2299

	/* End of calibration, restore configuration */
	b43_nphy_classifier(dev, 7, class);
	b43_nphy_write_clip_detection(dev, clip_state);
}

2300
/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal */
2301
static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, enum n_rssi_type type)
2302
{
2303
	int i, j, vcm;
2304 2305 2306 2307 2308 2309
	u8 state[4];
	u8 code, val;
	u16 class, override;
	u8 regs_save_radio[2];
	u16 regs_save_phy[2];

2310
	s32 offset[4];
2311 2312 2313 2314 2315 2316 2317 2318 2319 2320
	u8 core;
	u8 rail;

	u16 clip_state[2];
	u16 clip_off[2] = { 0xFFFF, 0xFFFF };
	s32 results_min[4] = { };
	u8 vcm_final[4] = { };
	s32 results[4][4] = { };
	s32 miniq[4][2] = { };

2321
	if (type == N_RSSI_NB) {
2322 2323
		code = 0;
		val = 6;
2324
	} else if (type == N_RSSI_W1 || type == N_RSSI_W2) {
2325 2326 2327 2328 2329 2330 2331 2332 2333 2334 2335 2336 2337 2338 2339 2340 2341 2342
		code = 25;
		val = 4;
	} else {
		B43_WARN_ON(1);
		return;
	}

	class = b43_nphy_classifier(dev, 0, 0);
	b43_nphy_classifier(dev, 7, 4);
	b43_nphy_read_clip_detection(dev, clip_state);
	b43_nphy_write_clip_detection(dev, clip_off);

	if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
		override = 0x140;
	else
		override = 0x110;

	regs_save_phy[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
2343
	regs_save_radio[0] = b43_radio_read(dev, B2055_C1_PD_RXTX);
2344
	b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, override);
2345
	b43_radio_write(dev, B2055_C1_PD_RXTX, val);
2346 2347

	regs_save_phy[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
2348
	regs_save_radio[1] = b43_radio_read(dev, B2055_C2_PD_RXTX);
2349
	b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, override);
2350
	b43_radio_write(dev, B2055_C2_PD_RXTX, val);
2351

2352 2353
	state[0] = b43_radio_read(dev, B2055_C1_PD_RSSIMISC) & 0x07;
	state[1] = b43_radio_read(dev, B2055_C2_PD_RSSIMISC) & 0x07;
2354 2355
	b43_radio_mask(dev, B2055_C1_PD_RSSIMISC, 0xF8);
	b43_radio_mask(dev, B2055_C2_PD_RSSIMISC, 0xF8);
2356 2357
	state[2] = b43_radio_read(dev, B2055_C1_SP_RSSI) & 0x07;
	state[3] = b43_radio_read(dev, B2055_C2_SP_RSSI) & 0x07;
2358 2359

	b43_nphy_rssi_select(dev, 5, type);
2360 2361
	b43_nphy_scale_offset_rssi(dev, 0, 0, 5, N_RAIL_I, type);
	b43_nphy_scale_offset_rssi(dev, 0, 0, 5, N_RAIL_Q, type);
2362

2363
	for (vcm = 0; vcm < 4; vcm++) {
2364 2365
		u8 tmp[4];
		for (j = 0; j < 4; j++)
2366
			tmp[j] = vcm;
2367
		if (type != N_RSSI_W2)
2368
			b43_nphy_set_rssi_2055_vcm(dev, type, tmp);
2369
		b43_nphy_poll_rssi(dev, type, results[vcm], 8);
2370
		if (type == N_RSSI_W1 || type == N_RSSI_W2)
2371
			for (j = 0; j < 2; j++)
2372 2373
				miniq[vcm][j] = min(results[vcm][2 * j],
						    results[vcm][2 * j + 1]);
2374 2375 2376
	}

	for (i = 0; i < 4; i++) {
2377
		s32 mind = 0x100000;
2378 2379
		u8 minvcm = 0;
		s32 minpoll = 249;
2380 2381
		s32 currd;
		for (vcm = 0; vcm < 4; vcm++) {
2382
			if (type == N_RSSI_NB)
2383
				currd = abs(results[vcm][i] - code * 8);
2384
			else
2385
				currd = abs(miniq[vcm][i / 2] - code * 8);
2386

2387 2388 2389
			if (currd < mind) {
				mind = currd;
				minvcm = vcm;
2390 2391
			}

2392 2393
			if (results[vcm][i] < minpoll)
				minpoll = results[vcm][i];
2394
		}
2395 2396 2397
		results_min[i] = minpoll;
		vcm_final[i] = minvcm;
	}
2398

2399
	if (type != N_RSSI_W2)
2400
		b43_nphy_set_rssi_2055_vcm(dev, type, vcm_final);
2401

2402 2403 2404 2405 2406 2407 2408 2409 2410 2411 2412 2413
	for (i = 0; i < 4; i++) {
		offset[i] = (code * 8) - results[vcm_final[i]][i];

		if (offset[i] < 0)
			offset[i] = -((abs(offset[i]) + 4) / 8);
		else
			offset[i] = (offset[i] + 4) / 8;

		if (results_min[i] == 248)
			offset[i] = code - 32;

		core = (i / 2) ? 2 : 1;
2414
		rail = (i % 2) ? N_RAIL_Q : N_RAIL_I;
2415 2416 2417 2418 2419 2420 2421 2422 2423 2424

		b43_nphy_scale_offset_rssi(dev, 0, offset[i], core, rail,
						type);
	}

	b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[0]);
	b43_radio_maskset(dev, B2055_C2_PD_RSSIMISC, 0xF8, state[1]);

	switch (state[2]) {
	case 1:
2425
		b43_nphy_rssi_select(dev, 1, N_RSSI_NB);
2426 2427
		break;
	case 4:
2428
		b43_nphy_rssi_select(dev, 1, N_RSSI_W1);
2429 2430
		break;
	case 2:
2431
		b43_nphy_rssi_select(dev, 1, N_RSSI_W2);
2432 2433
		break;
	default:
2434
		b43_nphy_rssi_select(dev, 1, N_RSSI_W2);
2435 2436 2437 2438 2439
		break;
	}

	switch (state[3]) {
	case 1:
2440
		b43_nphy_rssi_select(dev, 2, N_RSSI_NB);
2441 2442
		break;
	case 4:
2443
		b43_nphy_rssi_select(dev, 2, N_RSSI_W1);
2444 2445
		break;
	default:
2446
		b43_nphy_rssi_select(dev, 2, N_RSSI_W2);
2447 2448 2449 2450 2451 2452
		break;
	}

	b43_nphy_rssi_select(dev, 0, type);

	b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs_save_phy[0]);
2453
	b43_radio_write(dev, B2055_C1_PD_RXTX, regs_save_radio[0]);
2454
	b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs_save_phy[1]);
2455
	b43_radio_write(dev, B2055_C2_PD_RXTX, regs_save_radio[1]);
2456 2457 2458 2459 2460 2461 2462 2463 2464 2465 2466 2467 2468 2469

	b43_nphy_classifier(dev, 7, class);
	b43_nphy_write_clip_detection(dev, clip_state);
	/* Specs don't say about reset here, but it makes wl and b43 dumps
	   identical, it really seems wl performs this */
	b43_nphy_reset_cca(dev);
}

/*
 * RSSI Calibration
 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal
 */
static void b43_nphy_rssi_cal(struct b43_wldev *dev)
{
2470 2471 2472
	if (dev->phy.rev >= 19) {
		/* TODO */
	} else if (dev->phy.rev >= 3) {
2473 2474
		b43_nphy_rev3_rssi_cal(dev);
	} else {
2475 2476 2477
		b43_nphy_rev2_rssi_cal(dev, N_RSSI_NB);
		b43_nphy_rev2_rssi_cal(dev, N_RSSI_W1);
		b43_nphy_rev2_rssi_cal(dev, N_RSSI_W2);
2478 2479 2480
	}
}

2481 2482 2483 2484
/**************************************************
 * Workarounds
 **************************************************/

2485 2486 2487 2488 2489 2490 2491 2492 2493 2494 2495 2496 2497 2498 2499
static void b43_nphy_gain_ctl_workarounds_rev19(struct b43_wldev *dev)
{
	/* TODO */
}

static void b43_nphy_gain_ctl_workarounds_rev7(struct b43_wldev *dev)
{
	struct b43_phy *phy = &dev->phy;

	switch (phy->rev) {
	/* TODO */
	}
}

static void b43_nphy_gain_ctl_workarounds_rev3(struct b43_wldev *dev)
2500 2501 2502 2503 2504 2505 2506 2507 2508 2509 2510 2511 2512
{
	struct ssb_sprom *sprom = dev->dev->bus_sprom;

	bool ghz5;
	bool ext_lna;
	u16 rssi_gain;
	struct nphy_gain_ctl_workaround_entry *e;
	u8 lpf_gain[6] = { 0x00, 0x06, 0x0C, 0x12, 0x12, 0x12 };
	u8 lpf_bits[6] = { 0, 1, 2, 3, 3, 3 };

	/* Prepare values */
	ghz5 = b43_phy_read(dev, B43_NPHY_BANDCTL)
		& B43_NPHY_BANDCTL_5GHZ;
2513 2514
	ext_lna = ghz5 ? sprom->boardflags_hi & B43_BFH_EXTLNA_5GHZ :
		sprom->boardflags_lo & B43_BFL_EXTLNA;
2515 2516 2517 2518 2519 2520 2521 2522 2523
	e = b43_nphy_get_gain_ctl_workaround_ent(dev, ghz5, ext_lna);
	if (ghz5 && dev->phy.rev >= 5)
		rssi_gain = 0x90;
	else
		rssi_gain = 0x50;

	b43_phy_set(dev, B43_NPHY_RXCTL, 0x0040);

	/* Set Clip 2 detect */
2524 2525
	b43_phy_set(dev, B43_NPHY_C1_CGAINI, B43_NPHY_C1_CGAINI_CL2DETECT);
	b43_phy_set(dev, B43_NPHY_C2_CGAINI, B43_NPHY_C2_CGAINI_CL2DETECT);
2526 2527 2528 2529 2530 2531 2532 2533 2534 2535 2536 2537 2538 2539 2540 2541 2542 2543 2544 2545 2546 2547 2548 2549 2550 2551 2552 2553 2554 2555 2556 2557 2558

	b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAG1_IDAC,
			0x17);
	b43_radio_write(dev, B2056_RX1 | B2056_RX_BIASPOLE_LNAG1_IDAC,
			0x17);
	b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAG2_IDAC, 0xF0);
	b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAG2_IDAC, 0xF0);
	b43_radio_write(dev, B2056_RX0 | B2056_RX_RSSI_POLE, 0x00);
	b43_radio_write(dev, B2056_RX1 | B2056_RX_RSSI_POLE, 0x00);
	b43_radio_write(dev, B2056_RX0 | B2056_RX_RSSI_GAIN,
			rssi_gain);
	b43_radio_write(dev, B2056_RX1 | B2056_RX_RSSI_GAIN,
			rssi_gain);
	b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAA1_IDAC,
			0x17);
	b43_radio_write(dev, B2056_RX1 | B2056_RX_BIASPOLE_LNAA1_IDAC,
			0x17);
	b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAA2_IDAC, 0xFF);
	b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAA2_IDAC, 0xFF);

	b43_ntab_write_bulk(dev, B43_NTAB8(0, 8), 4, e->lna1_gain);
	b43_ntab_write_bulk(dev, B43_NTAB8(1, 8), 4, e->lna1_gain);
	b43_ntab_write_bulk(dev, B43_NTAB8(0, 16), 4, e->lna2_gain);
	b43_ntab_write_bulk(dev, B43_NTAB8(1, 16), 4, e->lna2_gain);
	b43_ntab_write_bulk(dev, B43_NTAB8(0, 32), 10, e->gain_db);
	b43_ntab_write_bulk(dev, B43_NTAB8(1, 32), 10, e->gain_db);
	b43_ntab_write_bulk(dev, B43_NTAB8(2, 32), 10, e->gain_bits);
	b43_ntab_write_bulk(dev, B43_NTAB8(3, 32), 10, e->gain_bits);
	b43_ntab_write_bulk(dev, B43_NTAB8(0, 0x40), 6, lpf_gain);
	b43_ntab_write_bulk(dev, B43_NTAB8(1, 0x40), 6, lpf_gain);
	b43_ntab_write_bulk(dev, B43_NTAB8(2, 0x40), 6, lpf_bits);
	b43_ntab_write_bulk(dev, B43_NTAB8(3, 0x40), 6, lpf_bits);

2559 2560 2561
	b43_phy_write(dev, B43_NPHY_REV3_C1_INITGAIN_A, e->init_gain);
	b43_phy_write(dev, B43_NPHY_REV3_C2_INITGAIN_A, e->init_gain);

2562 2563 2564
	b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x106), 2,
				e->rfseq_init);

2565 2566 2567 2568 2569 2570 2571 2572 2573 2574
	b43_phy_write(dev, B43_NPHY_REV3_C1_CLIP_HIGAIN_A, e->cliphi_gain);
	b43_phy_write(dev, B43_NPHY_REV3_C2_CLIP_HIGAIN_A, e->cliphi_gain);
	b43_phy_write(dev, B43_NPHY_REV3_C1_CLIP_MEDGAIN_A, e->clipmd_gain);
	b43_phy_write(dev, B43_NPHY_REV3_C2_CLIP_MEDGAIN_A, e->clipmd_gain);
	b43_phy_write(dev, B43_NPHY_REV3_C1_CLIP_LOGAIN_A, e->cliplo_gain);
	b43_phy_write(dev, B43_NPHY_REV3_C2_CLIP_LOGAIN_A, e->cliplo_gain);

	b43_phy_maskset(dev, B43_NPHY_CRSMINPOWER0, 0xFF00, e->crsmin);
	b43_phy_maskset(dev, B43_NPHY_CRSMINPOWERL0, 0xFF00, e->crsminl);
	b43_phy_maskset(dev, B43_NPHY_CRSMINPOWERU0, 0xFF00, e->crsminu);
2575 2576 2577 2578 2579 2580 2581 2582 2583 2584 2585 2586 2587 2588 2589 2590 2591 2592 2593 2594 2595 2596 2597 2598 2599 2600 2601
	b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, e->nbclip);
	b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, e->nbclip);
	b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
			~B43_NPHY_C1_CLIPWBTHRES_CLIP2, e->wlclip);
	b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
			~B43_NPHY_C2_CLIPWBTHRES_CLIP2, e->wlclip);
	b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
}

static void b43_nphy_gain_ctl_workarounds_rev1_2(struct b43_wldev *dev)
{
	struct b43_phy_n *nphy = dev->phy.n;

	u8 i, j;
	u8 code;
	u16 tmp;
	u8 rfseq_events[3] = { 6, 8, 7 };
	u8 rfseq_delays[3] = { 10, 30, 1 };

	/* Set Clip 2 detect */
	b43_phy_set(dev, B43_NPHY_C1_CGAINI, B43_NPHY_C1_CGAINI_CL2DETECT);
	b43_phy_set(dev, B43_NPHY_C2_CGAINI, B43_NPHY_C2_CGAINI_CL2DETECT);

	/* Set narrowband clip threshold */
	b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, 0x84);
	b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, 0x84);

2602
	if (!b43_is_40mhz(dev)) {
2603 2604 2605 2606 2607 2608 2609 2610 2611 2612 2613 2614 2615
		/* Set dwell lengths */
		b43_phy_write(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 0x002B);
		b43_phy_write(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 0x002B);
		b43_phy_write(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 0x0009);
		b43_phy_write(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 0x0009);
	}

	/* Set wideband clip 2 threshold */
	b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
			~B43_NPHY_C1_CLIPWBTHRES_CLIP2, 21);
	b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
			~B43_NPHY_C2_CLIPWBTHRES_CLIP2, 21);

2616
	if (!b43_is_40mhz(dev)) {
2617 2618 2619 2620 2621 2622 2623 2624 2625 2626 2627 2628 2629 2630
		b43_phy_maskset(dev, B43_NPHY_C1_CGAINI,
			~B43_NPHY_C1_CGAINI_GAINBKOFF, 0x1);
		b43_phy_maskset(dev, B43_NPHY_C2_CGAINI,
			~B43_NPHY_C2_CGAINI_GAINBKOFF, 0x1);
		b43_phy_maskset(dev, B43_NPHY_C1_CCK_CGAINI,
			~B43_NPHY_C1_CCK_CGAINI_GAINBKOFF, 0x1);
		b43_phy_maskset(dev, B43_NPHY_C2_CCK_CGAINI,
			~B43_NPHY_C2_CCK_CGAINI_GAINBKOFF, 0x1);
	}

	b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);

	if (nphy->gain_boost) {
		if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ &&
2631
		    b43_is_40mhz(dev))
2632 2633 2634 2635
			code = 4;
		else
			code = 5;
	} else {
2636
		code = b43_is_40mhz(dev) ? 6 : 7;
2637 2638 2639 2640 2641 2642 2643 2644 2645 2646 2647 2648 2649 2650 2651 2652 2653 2654 2655 2656 2657 2658 2659 2660 2661 2662 2663 2664 2665 2666 2667 2668 2669 2670 2671 2672 2673 2674 2675 2676 2677 2678 2679 2680 2681
	}

	/* Set HPVGA2 index */
	b43_phy_maskset(dev, B43_NPHY_C1_INITGAIN, ~B43_NPHY_C1_INITGAIN_HPVGA2,
			code << B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT);
	b43_phy_maskset(dev, B43_NPHY_C2_INITGAIN, ~B43_NPHY_C2_INITGAIN_HPVGA2,
			code << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT);

	b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
	/* specs say about 2 loops, but wl does 4 */
	for (i = 0; i < 4; i++)
		b43_phy_write(dev, B43_NPHY_TABLE_DATALO, (code << 8 | 0x7C));

	b43_nphy_adjust_lna_gain_table(dev);

	if (nphy->elna_gain_config) {
		b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0808);
		b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
		b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
		b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
		b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);

		b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0C08);
		b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
		b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
		b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
		b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);

		b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
		/* specs say about 2 loops, but wl does 4 */
		for (i = 0; i < 4; i++)
			b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
						(code << 8 | 0x74));
	}

	if (dev->phy.rev == 2) {
		for (i = 0; i < 4; i++) {
			b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
					(0x0400 * i) + 0x0020);
			for (j = 0; j < 21; j++) {
				tmp = j * (i < 2 ? 3 : 1);
				b43_phy_write(dev,
					B43_NPHY_TABLE_DATALO, tmp);
			}
		}
2682
	}
2683 2684 2685 2686 2687 2688 2689 2690 2691 2692 2693 2694 2695

	b43_nphy_set_rf_sequence(dev, 5, rfseq_events, rfseq_delays, 3);
	b43_phy_maskset(dev, B43_NPHY_OVER_DGAIN1,
		~B43_NPHY_OVER_DGAIN_CCKDGECV & 0xFFFF,
		0x5A << B43_NPHY_OVER_DGAIN_CCKDGECV_SHIFT);

	if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
		b43_phy_maskset(dev, B43_PHY_N(0xC5D), 0xFF80, 4);
}

/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/WorkaroundsGainCtrl */
static void b43_nphy_gain_ctl_workarounds(struct b43_wldev *dev)
{
2696 2697 2698 2699
	if (dev->phy.rev >= 19)
		b43_nphy_gain_ctl_workarounds_rev19(dev);
	else if (dev->phy.rev >= 7)
		b43_nphy_gain_ctl_workarounds_rev7(dev);
2700
	else if (dev->phy.rev >= 3)
2701
		b43_nphy_gain_ctl_workarounds_rev3(dev);
2702 2703
	else
		b43_nphy_gain_ctl_workarounds_rev1_2(dev);
2704 2705
}

2706 2707 2708 2709 2710 2711 2712 2713 2714 2715 2716 2717 2718 2719 2720 2721 2722 2723 2724 2725 2726 2727 2728 2729 2730 2731 2732 2733 2734 2735 2736 2737 2738 2739 2740 2741 2742 2743 2744 2745 2746 2747 2748 2749
static void b43_nphy_workarounds_rev7plus(struct b43_wldev *dev)
{
	struct ssb_sprom *sprom = dev->dev->bus_sprom;
	struct b43_phy *phy = &dev->phy;

	u8 rx2tx_events_ipa[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0xF, 0x3,
					0x1F };
	u8 rx2tx_delays_ipa[9] = { 8, 6, 6, 4, 4, 16, 43, 1, 1 };

	u16 ntab7_15e_16e[] = { 0x10f, 0x10f };
	u8 ntab7_138_146[] = { 0x11, 0x11 };
	u8 ntab7_133[] = { 0x77, 0x11, 0x11 };

	u16 lpf_20, lpf_40, lpf_11b;
	u16 bcap_val, bcap_val_11b, bcap_val_11n_20, bcap_val_11n_40;
	u16 scap_val, scap_val_11b, scap_val_11n_20, scap_val_11n_40;
	bool rccal_ovrd = false;

	u16 rx2tx_lut_20_11b, rx2tx_lut_20_11n, rx2tx_lut_40_11n;
	u16 bias, conv, filt;

	u32 tmp32;
	u8 core;

	if (phy->rev == 7) {
		b43_phy_set(dev, B43_NPHY_FINERX2_CGC, 0x10);
		b43_phy_maskset(dev, B43_NPHY_FREQGAIN0, 0xFF80, 0x0020);
		b43_phy_maskset(dev, B43_NPHY_FREQGAIN0, 0x80FF, 0x2700);
		b43_phy_maskset(dev, B43_NPHY_FREQGAIN1, 0xFF80, 0x002E);
		b43_phy_maskset(dev, B43_NPHY_FREQGAIN1, 0x80FF, 0x3300);
		b43_phy_maskset(dev, B43_NPHY_FREQGAIN2, 0xFF80, 0x0037);
		b43_phy_maskset(dev, B43_NPHY_FREQGAIN2, 0x80FF, 0x3A00);
		b43_phy_maskset(dev, B43_NPHY_FREQGAIN3, 0xFF80, 0x003C);
		b43_phy_maskset(dev, B43_NPHY_FREQGAIN3, 0x80FF, 0x3E00);
		b43_phy_maskset(dev, B43_NPHY_FREQGAIN4, 0xFF80, 0x003E);
		b43_phy_maskset(dev, B43_NPHY_FREQGAIN4, 0x80FF, 0x3F00);
		b43_phy_maskset(dev, B43_NPHY_FREQGAIN5, 0xFF80, 0x0040);
		b43_phy_maskset(dev, B43_NPHY_FREQGAIN5, 0x80FF, 0x4000);
		b43_phy_maskset(dev, B43_NPHY_FREQGAIN6, 0xFF80, 0x0040);
		b43_phy_maskset(dev, B43_NPHY_FREQGAIN6, 0x80FF, 0x4000);
		b43_phy_maskset(dev, B43_NPHY_FREQGAIN7, 0xFF80, 0x0040);
		b43_phy_maskset(dev, B43_NPHY_FREQGAIN7, 0x80FF, 0x4000);
	}
	if (phy->rev <= 8) {
2750 2751
		b43_phy_write(dev, B43_NPHY_FORCEFRONT0, 0x1B0);
		b43_phy_write(dev, B43_NPHY_FORCEFRONT1, 0x1B0);
2752 2753 2754 2755 2756 2757 2758 2759 2760 2761 2762 2763 2764 2765 2766 2767
	}
	if (phy->rev >= 8)
		b43_phy_maskset(dev, B43_NPHY_TXTAILCNT, ~0xFF, 0x72);

	b43_ntab_write(dev, B43_NTAB16(8, 0x00), 2);
	b43_ntab_write(dev, B43_NTAB16(8, 0x10), 2);
	tmp32 = b43_ntab_read(dev, B43_NTAB32(30, 0));
	tmp32 &= 0xffffff;
	b43_ntab_write(dev, B43_NTAB32(30, 0), tmp32);
	b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x15e), 2, ntab7_15e_16e);
	b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x16e), 2, ntab7_15e_16e);

	if (b43_nphy_ipa(dev))
		b43_nphy_set_rf_sequence(dev, 0, rx2tx_events_ipa,
				rx2tx_delays_ipa, ARRAY_SIZE(rx2tx_events_ipa));

2768 2769
	b43_phy_maskset(dev, B43_NPHY_EPS_OVERRIDEI_0, 0x3FFF, 0x4000);
	b43_phy_maskset(dev, B43_NPHY_EPS_OVERRIDEI_1, 0x3FFF, 0x4000);
2770 2771 2772 2773 2774

	lpf_20 = b43_nphy_read_lpf_ctl(dev, 0x154);
	lpf_40 = b43_nphy_read_lpf_ctl(dev, 0x159);
	lpf_11b = b43_nphy_read_lpf_ctl(dev, 0x152);
	if (b43_nphy_ipa(dev)) {
2775
		if ((phy->radio_rev == 5 && b43_is_40mhz(dev)) ||
2776 2777 2778 2779 2780
		    phy->radio_rev == 7 || phy->radio_rev == 8) {
			bcap_val = b43_radio_read(dev, 0x16b);
			scap_val = b43_radio_read(dev, 0x16a);
			scap_val_11b = scap_val;
			bcap_val_11b = bcap_val;
2781
			if (phy->radio_rev == 5 && b43_is_40mhz(dev)) {
2782 2783 2784 2785 2786 2787 2788 2789 2790 2791 2792 2793 2794 2795 2796 2797 2798 2799 2800 2801 2802 2803 2804 2805 2806 2807 2808 2809 2810 2811 2812 2813 2814 2815 2816 2817 2818 2819 2820 2821 2822 2823 2824 2825 2826 2827 2828 2829 2830 2831 2832 2833 2834 2835 2836 2837 2838 2839 2840 2841 2842 2843 2844 2845
				scap_val_11n_20 = scap_val;
				bcap_val_11n_20 = bcap_val;
				scap_val_11n_40 = bcap_val_11n_40 = 0xc;
				rccal_ovrd = true;
			} else { /* Rev 7/8 */
				lpf_20 = 4;
				lpf_11b = 1;
				if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
					scap_val_11n_20 = 0xc;
					bcap_val_11n_20 = 0xc;
					scap_val_11n_40 = 0xa;
					bcap_val_11n_40 = 0xa;
				} else {
					scap_val_11n_20 = 0x14;
					bcap_val_11n_20 = 0x14;
					scap_val_11n_40 = 0xf;
					bcap_val_11n_40 = 0xf;
				}
				rccal_ovrd = true;
			}
		}
	} else {
		if (phy->radio_rev == 5) {
			lpf_20 = 1;
			lpf_40 = 3;
			bcap_val = b43_radio_read(dev, 0x16b);
			scap_val = b43_radio_read(dev, 0x16a);
			scap_val_11b = scap_val;
			bcap_val_11b = bcap_val;
			scap_val_11n_20 = 0x11;
			scap_val_11n_40 = 0x11;
			bcap_val_11n_20 = 0x13;
			bcap_val_11n_40 = 0x13;
			rccal_ovrd = true;
		}
	}
	if (rccal_ovrd) {
		rx2tx_lut_20_11b = (bcap_val_11b << 8) |
				   (scap_val_11b << 3) |
				   lpf_11b;
		rx2tx_lut_20_11n = (bcap_val_11n_20 << 8) |
				   (scap_val_11n_20 << 3) |
				   lpf_20;
		rx2tx_lut_40_11n = (bcap_val_11n_40 << 8) |
				   (scap_val_11n_40 << 3) |
				   lpf_40;
		for (core = 0; core < 2; core++) {
			b43_ntab_write(dev, B43_NTAB16(7, 0x152 + core * 16),
				       rx2tx_lut_20_11b);
			b43_ntab_write(dev, B43_NTAB16(7, 0x153 + core * 16),
				       rx2tx_lut_20_11n);
			b43_ntab_write(dev, B43_NTAB16(7, 0x154 + core * 16),
				       rx2tx_lut_20_11n);
			b43_ntab_write(dev, B43_NTAB16(7, 0x155 + core * 16),
				       rx2tx_lut_40_11n);
			b43_ntab_write(dev, B43_NTAB16(7, 0x156 + core * 16),
				       rx2tx_lut_40_11n);
			b43_ntab_write(dev, B43_NTAB16(7, 0x157 + core * 16),
				       rx2tx_lut_40_11n);
			b43_ntab_write(dev, B43_NTAB16(7, 0x158 + core * 16),
				       rx2tx_lut_40_11n);
			b43_ntab_write(dev, B43_NTAB16(7, 0x159 + core * 16),
				       rx2tx_lut_40_11n);
		}
2846
		b43_nphy_rf_ctl_override_rev7(dev, 16, 1, 3, false, 2);
2847 2848 2849
	}
	b43_phy_write(dev, 0x32F, 0x3);
	if (phy->radio_rev == 4 || phy->radio_rev == 6)
2850
		b43_nphy_rf_ctl_override_rev7(dev, 4, 1, 3, false, 0);
2851 2852 2853 2854 2855 2856 2857 2858 2859 2860 2861 2862 2863 2864 2865 2866 2867 2868 2869 2870 2871 2872 2873 2874 2875 2876 2877 2878 2879 2880 2881 2882 2883 2884 2885 2886 2887 2888 2889 2890 2891 2892 2893 2894 2895 2896 2897 2898 2899 2900 2901 2902 2903 2904 2905 2906 2907 2908 2909 2910 2911 2912 2913 2914 2915 2916 2917 2918 2919 2920 2921 2922

	if (phy->radio_rev == 3 || phy->radio_rev == 4 || phy->radio_rev == 6) {
		if (sprom->revision &&
		    sprom->boardflags2_hi & B43_BFH2_IPALVLSHIFT_3P3) {
			b43_radio_write(dev, 0x5, 0x05);
			b43_radio_write(dev, 0x6, 0x30);
			b43_radio_write(dev, 0x7, 0x00);
			b43_radio_set(dev, 0x4f, 0x1);
			b43_radio_set(dev, 0xd4, 0x1);
			bias = 0x1f;
			conv = 0x6f;
			filt = 0xaa;
		} else {
			bias = 0x2b;
			conv = 0x7f;
			filt = 0xee;
		}
		if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
			for (core = 0; core < 2; core++) {
				if (core == 0) {
					b43_radio_write(dev, 0x5F, bias);
					b43_radio_write(dev, 0x64, conv);
					b43_radio_write(dev, 0x66, filt);
				} else {
					b43_radio_write(dev, 0xE8, bias);
					b43_radio_write(dev, 0xE9, conv);
					b43_radio_write(dev, 0xEB, filt);
				}
			}
		}
	}

	if (b43_nphy_ipa(dev)) {
		if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
			if (phy->radio_rev == 3 || phy->radio_rev == 4 ||
			    phy->radio_rev == 6) {
				for (core = 0; core < 2; core++) {
					if (core == 0)
						b43_radio_write(dev, 0x51,
								0x7f);
					else
						b43_radio_write(dev, 0xd6,
								0x7f);
				}
			}
			if (phy->radio_rev == 3) {
				for (core = 0; core < 2; core++) {
					if (core == 0) {
						b43_radio_write(dev, 0x64,
								0x13);
						b43_radio_write(dev, 0x5F,
								0x1F);
						b43_radio_write(dev, 0x66,
								0xEE);
						b43_radio_write(dev, 0x59,
								0x8A);
						b43_radio_write(dev, 0x80,
								0x3E);
					} else {
						b43_radio_write(dev, 0x69,
								0x13);
						b43_radio_write(dev, 0xE8,
								0x1F);
						b43_radio_write(dev, 0xEB,
								0xEE);
						b43_radio_write(dev, 0xDE,
								0x8A);
						b43_radio_write(dev, 0x105,
								0x3E);
					}
				}
			} else if (phy->radio_rev == 7 || phy->radio_rev == 8) {
2923
				if (!b43_is_40mhz(dev)) {
2924 2925 2926 2927 2928 2929 2930 2931
					b43_radio_write(dev, 0x5F, 0x14);
					b43_radio_write(dev, 0xE8, 0x12);
				} else {
					b43_radio_write(dev, 0x5F, 0x16);
					b43_radio_write(dev, 0xE8, 0x16);
				}
			}
		} else {
2932
			u16 freq = phy->chandef->chan->center_freq;
2933 2934 2935 2936 2937 2938 2939 2940 2941 2942 2943 2944 2945 2946 2947 2948 2949 2950 2951 2952 2953 2954 2955 2956 2957 2958 2959 2960 2961 2962 2963 2964 2965 2966 2967 2968 2969 2970 2971 2972 2973 2974 2975 2976 2977 2978 2979 2980 2981 2982 2983 2984 2985 2986 2987 2988 2989 2990 2991 2992 2993 2994 2995
			if ((freq >= 5180 && freq <= 5230) ||
			    (freq >= 5745 && freq <= 5805)) {
				b43_radio_write(dev, 0x7D, 0xFF);
				b43_radio_write(dev, 0xFE, 0xFF);
			}
		}
	} else {
		if (phy->radio_rev != 5) {
			for (core = 0; core < 2; core++) {
				if (core == 0) {
					b43_radio_write(dev, 0x5c, 0x61);
					b43_radio_write(dev, 0x51, 0x70);
				} else {
					b43_radio_write(dev, 0xe1, 0x61);
					b43_radio_write(dev, 0xd6, 0x70);
				}
			}
		}
	}

	if (phy->radio_rev == 4) {
		b43_ntab_write(dev, B43_NTAB16(8, 0x05), 0x20);
		b43_ntab_write(dev, B43_NTAB16(8, 0x15), 0x20);
		for (core = 0; core < 2; core++) {
			if (core == 0) {
				b43_radio_write(dev, 0x1a1, 0x00);
				b43_radio_write(dev, 0x1a2, 0x3f);
				b43_radio_write(dev, 0x1a6, 0x3f);
			} else {
				b43_radio_write(dev, 0x1a7, 0x00);
				b43_radio_write(dev, 0x1ab, 0x3f);
				b43_radio_write(dev, 0x1ac, 0x3f);
			}
		}
	} else {
		b43_phy_set(dev, B43_NPHY_AFECTL_C1, 0x4);
		b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x4);
		b43_phy_set(dev, B43_NPHY_AFECTL_C2, 0x4);
		b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4);

		b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x1);
		b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x1);
		b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x1);
		b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x1);
		b43_ntab_write(dev, B43_NTAB16(8, 0x05), 0x20);
		b43_ntab_write(dev, B43_NTAB16(8, 0x15), 0x20);

		b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x4);
		b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, ~0x4);
		b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x4);
		b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x4);
	}

	b43_phy_write(dev, B43_NPHY_ENDROP_TLEN, 0x2);

	b43_ntab_write(dev, B43_NTAB32(16, 0x100), 20);
	b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x138), 2, ntab7_138_146);
	b43_ntab_write(dev, B43_NTAB16(7, 0x141), 0x77);
	b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x133), 3, ntab7_133);
	b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x146), 2, ntab7_138_146);
	b43_ntab_write(dev, B43_NTAB16(7, 0x123), 0x77);
	b43_ntab_write(dev, B43_NTAB16(7, 0x12A), 0x77);

2996
	if (!b43_is_40mhz(dev)) {
2997 2998 2999 3000 3001 3002 3003 3004 3005 3006 3007 3008 3009 3010 3011 3012 3013 3014 3015 3016 3017
		b43_ntab_write(dev, B43_NTAB32(16, 0x03), 0x18D);
		b43_ntab_write(dev, B43_NTAB32(16, 0x7F), 0x18D);
	} else {
		b43_ntab_write(dev, B43_NTAB32(16, 0x03), 0x14D);
		b43_ntab_write(dev, B43_NTAB32(16, 0x7F), 0x14D);
	}

	b43_nphy_gain_ctl_workarounds(dev);

	/* TODO
	b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x08), 4,
			    aux_adc_vmid_rev7_core0);
	b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x18), 4,
			    aux_adc_vmid_rev7_core1);
	b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x0C), 4,
			    aux_adc_gain_rev7);
	b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x1C), 4,
			    aux_adc_gain_rev7);
	*/
}

3018
static void b43_nphy_workarounds_rev3plus(struct b43_wldev *dev)
3019
{
3020
	struct b43_phy_n *nphy = dev->phy.n;
Rafał Miłecki's avatar
Rafał Miłecki committed
3021
	struct ssb_sprom *sprom = dev->dev->bus_sprom;
3022

3023
	/* TX to RX */
3024 3025
	u8 tx2rx_events[7] = { 0x4, 0x3, 0x5, 0x2, 0x1, 0x8, 0x1F };
	u8 tx2rx_delays[7] = { 8, 4, 4, 4, 4, 6, 1 };
3026 3027 3028 3029 3030 3031 3032
	/* RX to TX */
	u8 rx2tx_events_ipa[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0xF, 0x3,
					0x1F };
	u8 rx2tx_delays_ipa[9] = { 8, 6, 6, 4, 4, 16, 43, 1, 1 };
	u8 rx2tx_events[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0x3, 0x4, 0x1F };
	u8 rx2tx_delays[9] = { 8, 6, 6, 4, 4, 18, 42, 1, 1 };

3033 3034 3035 3036 3037 3038 3039 3040 3041 3042 3043 3044 3045 3046 3047 3048 3049
	u16 vmids[5][4] = {
		{ 0xa2, 0xb4, 0xb4, 0x89, }, /* 0 */
		{ 0xb4, 0xb4, 0xb4, 0x24, }, /* 1 */
		{ 0xa2, 0xb4, 0xb4, 0x74, }, /* 2 */
		{ 0xa2, 0xb4, 0xb4, 0x270, }, /* 3 */
		{ 0xa2, 0xb4, 0xb4, 0x00, }, /* 4 and 5 */
	};
	u16 gains[5][4] = {
		{ 0x02, 0x02, 0x02, 0x00, }, /* 0 */
		{ 0x02, 0x02, 0x02, 0x02, }, /* 1 */
		{ 0x02, 0x02, 0x02, 0x04, }, /* 2 */
		{ 0x02, 0x02, 0x02, 0x00, }, /* 3 */
		{ 0x02, 0x02, 0x02, 0x00, }, /* 4 and 5 */
	};
	u16 *vmid, *gain;

	u8 pdet_range;
3050 3051 3052
	u16 tmp16;
	u32 tmp32;

3053 3054
	b43_phy_write(dev, B43_NPHY_FORCEFRONT0, 0x1f8);
	b43_phy_write(dev, B43_NPHY_FORCEFRONT1, 0x1f8);
3055

3056 3057 3058
	tmp32 = b43_ntab_read(dev, B43_NTAB32(30, 0));
	tmp32 &= 0xffffff;
	b43_ntab_write(dev, B43_NTAB32(30, 0), tmp32);
3059

3060 3061 3062 3063 3064 3065
	b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x0125);
	b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x01B3);
	b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x0105);
	b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x016E);
	b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0x00CD);
	b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x0020);
3066

3067 3068
	b43_phy_write(dev, B43_NPHY_REV3_C1_CLIP_LOGAIN_B, 0x000C);
	b43_phy_write(dev, B43_NPHY_REV3_C2_CLIP_LOGAIN_B, 0x000C);
3069

3070
	/* TX to RX */
3071 3072
	b43_nphy_set_rf_sequence(dev, 1, tx2rx_events, tx2rx_delays,
				 ARRAY_SIZE(tx2rx_events));
3073 3074 3075

	/* RX to TX */
	if (b43_nphy_ipa(dev))
3076 3077
		b43_nphy_set_rf_sequence(dev, 0, rx2tx_events_ipa,
				rx2tx_delays_ipa, ARRAY_SIZE(rx2tx_events_ipa));
3078 3079 3080 3081 3082 3083 3084
	if (nphy->hw_phyrxchain != 3 &&
	    nphy->hw_phyrxchain != nphy->hw_phytxchain) {
		if (b43_nphy_ipa(dev)) {
			rx2tx_delays[5] = 59;
			rx2tx_delays[6] = 1;
			rx2tx_events[7] = 0x1F;
		}
3085
		b43_nphy_set_rf_sequence(dev, 0, rx2tx_events, rx2tx_delays,
3086
					 ARRAY_SIZE(rx2tx_events));
3087
	}
3088

3089 3090 3091
	tmp16 = (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) ?
		0x2 : 0x9C40;
	b43_phy_write(dev, B43_NPHY_ENDROP_TLEN, tmp16);
3092

3093
	b43_phy_maskset(dev, B43_NPHY_SGILTRNOFFSET, 0xF0FF, 0x0700);
3094

3095
	if (!b43_is_40mhz(dev)) {
3096 3097 3098 3099 3100 3101
		b43_ntab_write(dev, B43_NTAB32(16, 3), 0x18D);
		b43_ntab_write(dev, B43_NTAB32(16, 127), 0x18D);
	} else {
		b43_ntab_write(dev, B43_NTAB32(16, 3), 0x14D);
		b43_ntab_write(dev, B43_NTAB32(16, 127), 0x14D);
	}
3102

3103
	b43_nphy_gain_ctl_workarounds(dev);
3104

3105 3106
	b43_ntab_write(dev, B43_NTAB16(8, 0), 2);
	b43_ntab_write(dev, B43_NTAB16(8, 16), 2);
3107

3108 3109 3110 3111 3112 3113 3114 3115 3116 3117 3118 3119 3120 3121 3122 3123 3124 3125 3126 3127 3128 3129 3130 3131 3132 3133 3134 3135 3136 3137 3138 3139 3140 3141 3142 3143 3144 3145 3146 3147 3148 3149 3150 3151 3152 3153 3154 3155 3156 3157 3158 3159 3160 3161 3162 3163 3164 3165 3166 3167 3168 3169 3170 3171 3172
	if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
		pdet_range = sprom->fem.ghz2.pdet_range;
	else
		pdet_range = sprom->fem.ghz5.pdet_range;
	vmid = vmids[min_t(u16, pdet_range, 4)];
	gain = gains[min_t(u16, pdet_range, 4)];
	switch (pdet_range) {
	case 3:
		if (!(dev->phy.rev >= 4 &&
		      b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ))
			break;
		/* FALL THROUGH */
	case 0:
	case 1:
		b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x08), 4, vmid);
		b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x18), 4, vmid);
		b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x0c), 4, gain);
		b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x1c), 4, gain);
		break;
	case 2:
		if (dev->phy.rev >= 6) {
			if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
				vmid[3] = 0x94;
			else
				vmid[3] = 0x8e;
			gain[3] = 3;
		} else if (dev->phy.rev == 5) {
			vmid[3] = 0x84;
			gain[3] = 2;
		}
		b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x08), 4, vmid);
		b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x18), 4, vmid);
		b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x0c), 4, gain);
		b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x1c), 4, gain);
		break;
	case 4:
	case 5:
		if (b43_current_band(dev->wl) != IEEE80211_BAND_2GHZ) {
			if (pdet_range == 4) {
				vmid[3] = 0x8e;
				tmp16 = 0x96;
				gain[3] = 0x2;
			} else {
				vmid[3] = 0x89;
				tmp16 = 0x89;
				gain[3] = 0;
			}
		} else {
			if (pdet_range == 4) {
				vmid[3] = 0x89;
				tmp16 = 0x8b;
				gain[3] = 0x2;
			} else {
				vmid[3] = 0x74;
				tmp16 = 0x70;
				gain[3] = 0;
			}
		}
		b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x08), 4, vmid);
		b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x0c), 4, gain);
		vmid[3] = tmp16;
		b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x18), 4, vmid);
		b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x1c), 4, gain);
		break;
	}
3173

3174 3175 3176 3177 3178 3179 3180 3181
	b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_MAST_BIAS, 0x00);
	b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_MAST_BIAS, 0x00);
	b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_MAIN, 0x06);
	b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_MAIN, 0x06);
	b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_AUX, 0x07);
	b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_AUX, 0x07);
	b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_LOB_BIAS, 0x88);
	b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_LOB_BIAS, 0x88);
3182 3183
	b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_CMFB_IDAC, 0x00);
	b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_CMFB_IDAC, 0x00);
3184 3185 3186 3187 3188 3189 3190 3191 3192 3193 3194 3195 3196 3197 3198 3199 3200
	b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXG_CMFB_IDAC, 0x00);
	b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXG_CMFB_IDAC, 0x00);

	/* N PHY WAR TX Chain Update with hw_phytxchain as argument */

	if ((sprom->boardflags2_lo & B43_BFL2_APLL_WAR &&
	     b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ||
	    (sprom->boardflags2_lo & B43_BFL2_GPLL_WAR &&
	     b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ))
		tmp32 = 0x00088888;
	else
		tmp32 = 0x88888888;
	b43_ntab_write(dev, B43_NTAB32(30, 1), tmp32);
	b43_ntab_write(dev, B43_NTAB32(30, 2), tmp32);
	b43_ntab_write(dev, B43_NTAB32(30, 3), tmp32);

	if (dev->phy.rev == 4 &&
3201
	    b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
3202 3203 3204 3205 3206
		b43_radio_write(dev, B2056_TX0 | B2056_TX_GMBB_IDAC,
				0x70);
		b43_radio_write(dev, B2056_TX1 | B2056_TX_GMBB_IDAC,
				0x70);
	}
3207

3208
	/* Dropped probably-always-true condition */
3209 3210
	b43_phy_write(dev, B43_NPHY_ED_CRS40ASSERTTHRESH0, 0x03eb);
	b43_phy_write(dev, B43_NPHY_ED_CRS40ASSERTTHRESH1, 0x03eb);
3211
	b43_phy_write(dev, B43_NPHY_ED_CRS40DEASSERTTHRESH0, 0x0341);
3212 3213 3214 3215 3216 3217 3218 3219 3220
	b43_phy_write(dev, B43_NPHY_ED_CRS40DEASSERTTHRESH1, 0x0341);
	b43_phy_write(dev, B43_NPHY_ED_CRS20LASSERTTHRESH0, 0x042b);
	b43_phy_write(dev, B43_NPHY_ED_CRS20LASSERTTHRESH1, 0x042b);
	b43_phy_write(dev, B43_NPHY_ED_CRS20LDEASSERTTHRESH0, 0x0381);
	b43_phy_write(dev, B43_NPHY_ED_CRS20LDEASSERTTHRESH1, 0x0381);
	b43_phy_write(dev, B43_NPHY_ED_CRS20UASSERTTHRESH0, 0x042b);
	b43_phy_write(dev, B43_NPHY_ED_CRS20UASSERTTHRESH1, 0x042b);
	b43_phy_write(dev, B43_NPHY_ED_CRS20UDEASSERTTHRESH0, 0x0381);
	b43_phy_write(dev, B43_NPHY_ED_CRS20UDEASSERTTHRESH1, 0x0381);
3221 3222 3223

	if (dev->phy.rev >= 6 && sprom->boardflags2_lo & B43_BFL2_SINGLEANT_CCK)
		; /* TODO: 0x0080000000000000 HF */
3224
}
3225

3226 3227 3228 3229 3230
static void b43_nphy_workarounds_rev1_2(struct b43_wldev *dev)
{
	struct ssb_sprom *sprom = dev->dev->bus_sprom;
	struct b43_phy *phy = &dev->phy;
	struct b43_phy_n *nphy = phy->n;
3231

3232 3233
	u8 events1[7] = { 0x0, 0x1, 0x2, 0x8, 0x4, 0x5, 0x3 };
	u8 delays1[7] = { 0x8, 0x6, 0x6, 0x2, 0x4, 0x3C, 0x1 };
3234

3235 3236
	u8 events2[7] = { 0x0, 0x3, 0x5, 0x4, 0x2, 0x1, 0x8 };
	u8 delays2[7] = { 0x8, 0x6, 0x2, 0x4, 0x4, 0x6, 0x1 };
3237

3238
	if (sprom->boardflags2_lo & B43_BFL2_SKWRKFEM_BRD ||
3239
	    dev->dev->board_type == BCMA_BOARD_TYPE_BCM943224M93) {
3240 3241 3242 3243
		delays1[0] = 0x1;
		delays1[5] = 0x14;
	}

3244 3245 3246 3247
	if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ &&
	    nphy->band5g_pwrgain) {
		b43_radio_mask(dev, B2055_C1_TX_RF_SPARE, ~0x8);
		b43_radio_mask(dev, B2055_C2_TX_RF_SPARE, ~0x8);
3248
	} else {
3249 3250 3251
		b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8);
		b43_radio_set(dev, B2055_C2_TX_RF_SPARE, 0x8);
	}
3252

3253 3254
	b43_ntab_write(dev, B43_NTAB16(8, 0x00), 0x000A);
	b43_ntab_write(dev, B43_NTAB16(8, 0x10), 0x000A);
3255 3256 3257 3258
	if (dev->phy.rev < 3) {
		b43_ntab_write(dev, B43_NTAB16(8, 0x02), 0xCDAA);
		b43_ntab_write(dev, B43_NTAB16(8, 0x12), 0xCDAA);
	}
3259 3260 3261 3262 3263 3264 3265 3266 3267

	if (dev->phy.rev < 2) {
		b43_ntab_write(dev, B43_NTAB16(8, 0x08), 0x0000);
		b43_ntab_write(dev, B43_NTAB16(8, 0x18), 0x0000);
		b43_ntab_write(dev, B43_NTAB16(8, 0x07), 0x7AAB);
		b43_ntab_write(dev, B43_NTAB16(8, 0x17), 0x7AAB);
		b43_ntab_write(dev, B43_NTAB16(8, 0x06), 0x0800);
		b43_ntab_write(dev, B43_NTAB16(8, 0x16), 0x0800);
	}
3268

3269 3270 3271 3272
	b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
	b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
	b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
	b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
3273

3274 3275 3276
	b43_nphy_set_rf_sequence(dev, 0, events1, delays1, 7);
	b43_nphy_set_rf_sequence(dev, 1, events2, delays2, 7);

3277
	b43_nphy_gain_ctl_workarounds(dev);
3278 3279 3280 3281 3282 3283 3284 3285 3286

	if (dev->phy.rev < 2) {
		if (b43_phy_read(dev, B43_NPHY_RXCTL) & 0x2)
			b43_hf_write(dev, b43_hf_read(dev) |
					B43_HF_MLADVW);
	} else if (dev->phy.rev == 2) {
		b43_phy_write(dev, B43_NPHY_CRSCHECK2, 0);
		b43_phy_write(dev, B43_NPHY_CRSCHECK3, 0);
	}
3287

3288 3289 3290 3291 3292 3293 3294 3295 3296 3297 3298 3299
	if (dev->phy.rev < 2)
		b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL,
				~B43_NPHY_SCRAM_SIGCTL_SCM);

	/* Set phase track alpha and beta */
	b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125);
	b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3);
	b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105);
	b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E);
	b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD);
	b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20);

3300 3301 3302 3303 3304 3305 3306
	if (dev->phy.rev < 3) {
		b43_phy_mask(dev, B43_NPHY_PIL_DW1,
			     ~B43_NPHY_PIL_DW_64QAM & 0xFFFF);
		b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B1, 0xB5);
		b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B2, 0xA4);
		b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B3, 0x00);
	}
3307 3308 3309 3310 3311

	if (dev->phy.rev == 2)
		b43_phy_set(dev, B43_NPHY_FINERX2_CGC,
				B43_NPHY_FINERX2_CGC_DECGC);
}
3312

3313 3314 3315 3316 3317
/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Workarounds */
static void b43_nphy_workarounds(struct b43_wldev *dev)
{
	struct b43_phy *phy = &dev->phy;
	struct b43_phy_n *nphy = phy->n;
3318

3319 3320 3321 3322
	if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
		b43_nphy_classifier(dev, 1, 0);
	else
		b43_nphy_classifier(dev, 1, 1);
3323

3324 3325 3326 3327 3328 3329
	if (nphy->hang_avoid)
		b43_nphy_stay_in_carrier_search(dev, 1);

	b43_phy_set(dev, B43_NPHY_IQFLIP,
		    B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2);

3330
	/* TODO: rev19+ */
3331 3332 3333
	if (dev->phy.rev >= 7)
		b43_nphy_workarounds_rev7plus(dev);
	else if (dev->phy.rev >= 3)
3334 3335 3336
		b43_nphy_workarounds_rev3plus(dev);
	else
		b43_nphy_workarounds_rev1_2(dev);
3337 3338 3339 3340 3341

	if (nphy->hang_avoid)
		b43_nphy_stay_in_carrier_search(dev, 0);
}

3342 3343 3344 3345 3346 3347 3348 3349 3350
/**************************************************
 * Tx/Rx common
 **************************************************/

/*
 * Transmits a known value for LO calibration
 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TXTone
 */
static int b43_nphy_tx_tone(struct b43_wldev *dev, u32 freq, u16 max_val,
3351
			    bool iqmode, bool dac_test, bool modify_bbmult)
3352 3353 3354 3355
{
	u16 samp = b43_nphy_gen_load_samples(dev, freq, max_val, dac_test);
	if (samp == 0)
		return -1;
3356 3357
	b43_nphy_run_samples(dev, samp, 0xFFFF, 0, iqmode, dac_test,
			     modify_bbmult);
3358 3359 3360 3361 3362 3363 3364 3365 3366 3367 3368 3369 3370 3371 3372 3373 3374 3375 3376 3377 3378 3379 3380 3381 3382 3383 3384 3385 3386 3387 3388 3389 3390 3391
	return 0;
}

/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Chains */
static void b43_nphy_update_txrx_chain(struct b43_wldev *dev)
{
	struct b43_phy_n *nphy = dev->phy.n;

	bool override = false;
	u16 chain = 0x33;

	if (nphy->txrx_chain == 0) {
		chain = 0x11;
		override = true;
	} else if (nphy->txrx_chain == 1) {
		chain = 0x22;
		override = true;
	}

	b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
			~(B43_NPHY_RFSEQCA_TXEN | B43_NPHY_RFSEQCA_RXEN),
			chain);

	if (override)
		b43_phy_set(dev, B43_NPHY_RFSEQMODE,
				B43_NPHY_RFSEQMODE_CAOVER);
	else
		b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
				~B43_NPHY_RFSEQMODE_CAOVER);
}

/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/stop-playback */
static void b43_nphy_stop_playback(struct b43_wldev *dev)
{
3392
	struct b43_phy *phy = &dev->phy;
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	struct b43_phy_n *nphy = dev->phy.n;
	u16 tmp;

	if (nphy->hang_avoid)
		b43_nphy_stay_in_carrier_search(dev, 1);

	tmp = b43_phy_read(dev, B43_NPHY_SAMP_STAT);
	if (tmp & 0x1)
		b43_phy_set(dev, B43_NPHY_SAMP_CMD, B43_NPHY_SAMP_CMD_STOP);
	else if (tmp & 0x2)
		b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);

	b43_phy_mask(dev, B43_NPHY_SAMP_CMD, ~0x0004);

	if (nphy->bb_mult_save & 0x80000000) {
		tmp = nphy->bb_mult_save & 0xFFFF;
		b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
		nphy->bb_mult_save = 0;
	}

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	if (phy->rev >= 7) {
		if (phy->rev >= 19)
			b43_nphy_rf_ctl_override_rev19(dev, 0x80, 0, 0, true,
						       1);
		else
			b43_nphy_rf_ctl_override_rev7(dev, 0x80, 0, 0, true, 1);
		nphy->lpf_bw_overrode_for_sample_play = false;
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	}

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	if (nphy->hang_avoid)
		b43_nphy_stay_in_carrier_search(dev, 0);
}

/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IqCalGainParams */
static void b43_nphy_iq_cal_gain_params(struct b43_wldev *dev, u16 core,
					struct nphy_txgains target,
					struct nphy_iqcal_params *params)
{
3431
	struct b43_phy *phy = &dev->phy;
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	int i, j, indx;
	u16 gain;

	if (dev->phy.rev >= 3) {
3436
		params->tx_lpf = target.tx_lpf[core]; /* Rev 7+ */
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		params->txgm = target.txgm[core];
		params->pga = target.pga[core];
		params->pad = target.pad[core];
		params->ipa = target.ipa[core];
3441 3442 3443
		if (phy->rev >= 19) {
			/* TODO */
		} else if (phy->rev >= 7) {
3444
			params->cal_gain = (params->txgm << 12) | (params->pga << 8) | (params->pad << 3) | (params->ipa) | (params->tx_lpf << 15);
3445 3446 3447
		} else {
			params->cal_gain = (params->txgm << 12) | (params->pga << 8) | (params->pad << 4) | (params->ipa);
		}
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		for (j = 0; j < 5; j++)
			params->ncorr[j] = 0x79;
	} else {
		gain = (target.pad[core]) | (target.pga[core] << 4) |
			(target.txgm[core] << 8);

		indx = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ?
			1 : 0;
		for (i = 0; i < 9; i++)
			if (tbl_iqcal_gainparams[indx][i][0] == gain)
				break;
		i = min(i, 8);

		params->txgm = tbl_iqcal_gainparams[indx][i][1];
		params->pga = tbl_iqcal_gainparams[indx][i][2];
		params->pad = tbl_iqcal_gainparams[indx][i][3];
		params->cal_gain = (params->txgm << 7) | (params->pga << 4) |
					(params->pad << 2);
		for (j = 0; j < 4; j++)
			params->ncorr[j] = tbl_iqcal_gainparams[indx][i][4 + j];
	}
}

3471
/**************************************************
3472
 * Tx and Rx
3473
 **************************************************/
3474

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static void b43_nphy_op_adjust_txpower(struct b43_wldev *dev)
{//TODO
}
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3478

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static enum b43_txpwr_result b43_nphy_op_recalc_txpower(struct b43_wldev *dev,
							bool ignore_tssi)
{//TODO
	return B43_TXPWR_RES_DONE;
}
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3484

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/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlEnable */
static void b43_nphy_tx_power_ctrl(struct b43_wldev *dev, bool enable)
{
3488
	struct b43_phy *phy = &dev->phy;
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	struct b43_phy_n *nphy = dev->phy.n;
	u8 i;
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	u16 bmask, val, tmp;
	enum ieee80211_band band = b43_current_band(dev->wl);
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3493

3494 3495
	if (nphy->hang_avoid)
		b43_nphy_stay_in_carrier_search(dev, 1);
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3496

3497 3498
	nphy->txpwrctrl = enable;
	if (!enable) {
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		if (dev->phy.rev >= 3 &&
		    (b43_phy_read(dev, B43_NPHY_TXPCTL_CMD) &
		     (B43_NPHY_TXPCTL_CMD_COEFF |
		      B43_NPHY_TXPCTL_CMD_HWPCTLEN |
		      B43_NPHY_TXPCTL_CMD_PCTLEN))) {
			/* We disable enabled TX pwr ctl, save it's state */
			nphy->tx_pwr_idx[0] = b43_phy_read(dev,
						B43_NPHY_C1_TXPCTL_STAT) & 0x7f;
			nphy->tx_pwr_idx[1] = b43_phy_read(dev,
						B43_NPHY_C2_TXPCTL_STAT) & 0x7f;
		}
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3510

3511 3512 3513
		b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6840);
		for (i = 0; i < 84; i++)
			b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0);
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3514

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		b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6C40);
		for (i = 0; i < 84; i++)
			b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0);
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3518

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		tmp = B43_NPHY_TXPCTL_CMD_COEFF | B43_NPHY_TXPCTL_CMD_HWPCTLEN;
		if (dev->phy.rev >= 3)
			tmp |= B43_NPHY_TXPCTL_CMD_PCTLEN;
		b43_phy_mask(dev, B43_NPHY_TXPCTL_CMD, ~tmp);
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3523

3524 3525 3526 3527 3528 3529
		if (dev->phy.rev >= 3) {
			b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100);
			b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100);
		} else {
			b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000);
		}
3530

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		if (dev->phy.rev == 2)
			b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
				~B43_NPHY_BPHY_CTL3_SCALE, 0x53);
		else if (dev->phy.rev < 2)
			b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
				~B43_NPHY_BPHY_CTL3_SCALE, 0x5A);
3537

3538
		if (dev->phy.rev < 2 && b43_is_40mhz(dev))
3539
			b43_hf_write(dev, b43_hf_read(dev) | B43_HF_TSSIRPSMW);
3540
	} else {
3541 3542 3543 3544
		b43_ntab_write_bulk(dev, B43_NTAB16(26, 64), 84,
				    nphy->adj_pwr_tbl);
		b43_ntab_write_bulk(dev, B43_NTAB16(27, 64), 84,
				    nphy->adj_pwr_tbl);
3545

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		bmask = B43_NPHY_TXPCTL_CMD_COEFF |
			B43_NPHY_TXPCTL_CMD_HWPCTLEN;
		/* wl does useless check for "enable" param here */
		val = B43_NPHY_TXPCTL_CMD_COEFF | B43_NPHY_TXPCTL_CMD_HWPCTLEN;
		if (dev->phy.rev >= 3) {
			bmask |= B43_NPHY_TXPCTL_CMD_PCTLEN;
			if (val)
				val |= B43_NPHY_TXPCTL_CMD_PCTLEN;
		}
		b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD, ~(bmask), val);
3556

3557
		if (band == IEEE80211_BAND_5GHZ) {
3558 3559 3560
			if (phy->rev >= 19) {
				/* TODO */
			} else if (phy->rev >= 7) {
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				b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
						~B43_NPHY_TXPCTL_CMD_INIT,
						0x32);
				b43_phy_maskset(dev, B43_NPHY_TXPCTL_INIT,
						~B43_NPHY_TXPCTL_INIT_PIDXI1,
						0x32);
3567 3568 3569
			} else {
				b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
						~B43_NPHY_TXPCTL_CMD_INIT,
3570
						0x64);
3571 3572 3573 3574 3575 3576
				if (phy->rev > 1)
					b43_phy_maskset(dev,
							B43_NPHY_TXPCTL_INIT,
							~B43_NPHY_TXPCTL_INIT_PIDXI1,
							0x64);
			}
3577
		}
3578

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		if (dev->phy.rev >= 3) {
			if (nphy->tx_pwr_idx[0] != 128 &&
			    nphy->tx_pwr_idx[1] != 128) {
				/* Recover TX pwr ctl state */
				b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
						~B43_NPHY_TXPCTL_CMD_INIT,
						nphy->tx_pwr_idx[0]);
				if (dev->phy.rev > 1)
					b43_phy_maskset(dev,
						B43_NPHY_TXPCTL_INIT,
						~0xff, nphy->tx_pwr_idx[1]);
			}
		}
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		if (phy->rev >= 7) {
			/* TODO */
		}

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		if (dev->phy.rev >= 3) {
			b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, ~0x100);
			b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x100);
		} else {
			b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x4000);
		}
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3604 3605 3606 3607
		if (dev->phy.rev == 2)
			b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, ~0xFF, 0x3b);
		else if (dev->phy.rev < 2)
			b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, ~0xFF, 0x40);
3608

3609
		if (dev->phy.rev < 2 && b43_is_40mhz(dev))
3610
			b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_TSSIRPSMW);
3611

3612
		if (b43_nphy_ipa(dev)) {
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			b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x4);
			b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x4);
3615 3616 3617
		}
	}

3618 3619
	if (nphy->hang_avoid)
		b43_nphy_stay_in_carrier_search(dev, 0);
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3620 3621
}

3622
/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrFix */
3623
static void b43_nphy_tx_power_fix(struct b43_wldev *dev)
3624
{
3625
	struct b43_phy *phy = &dev->phy;
3626
	struct b43_phy_n *nphy = dev->phy.n;
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3627
	struct ssb_sprom *sprom = dev->dev->bus_sprom;
3628

3629 3630
	u8 txpi[2], bbmult, i;
	u16 tmp, radio_gain, dac_gain;
3631
	u16 freq = phy->chandef->chan->center_freq;
3632 3633
	u32 txgain;
	/* u32 gaintbl; rev3+ */
3634 3635

	if (nphy->hang_avoid)
3636
		b43_nphy_stay_in_carrier_search(dev, 1);
3637

3638
	/* TODO: rev19+ */
3639 3640 3641
	if (dev->phy.rev >= 7) {
		txpi[0] = txpi[1] = 30;
	} else if (dev->phy.rev >= 3) {
3642 3643 3644 3645 3646 3647 3648 3649 3650 3651 3652 3653 3654 3655 3656 3657 3658 3659 3660 3661 3662
		txpi[0] = 40;
		txpi[1] = 40;
	} else if (sprom->revision < 4) {
		txpi[0] = 72;
		txpi[1] = 72;
	} else {
		if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
			txpi[0] = sprom->txpid2g[0];
			txpi[1] = sprom->txpid2g[1];
		} else if (freq >= 4900 && freq < 5100) {
			txpi[0] = sprom->txpid5gl[0];
			txpi[1] = sprom->txpid5gl[1];
		} else if (freq >= 5100 && freq < 5500) {
			txpi[0] = sprom->txpid5g[0];
			txpi[1] = sprom->txpid5g[1];
		} else if (freq >= 5500) {
			txpi[0] = sprom->txpid5gh[0];
			txpi[1] = sprom->txpid5gh[1];
		} else {
			txpi[0] = 91;
			txpi[1] = 91;
3663 3664
		}
	}
3665
	if (dev->phy.rev < 7 &&
3666
	    (txpi[0] < 40 || txpi[0] > 100 || txpi[1] < 40 || txpi[1] > 100))
3667
		txpi[0] = txpi[1] = 91;
3668

3669 3670 3671 3672
	/*
	for (i = 0; i < 2; i++) {
		nphy->txpwrindex[i].index_internal = txpi[i];
		nphy->txpwrindex[i].index_internal_save = txpi[i];
3673
	}
3674
	*/
3675

3676
	for (i = 0; i < 2; i++) {
3677 3678 3679 3680 3681
		const u32 *table = b43_nphy_get_tx_gain_table(dev);

		if (!table)
			break;
		txgain = *(table + txpi[i]);
3682 3683

		if (dev->phy.rev >= 3)
3684
			radio_gain = (txgain >> 16) & 0x1FFFF;
3685
		else
3686
			radio_gain = (txgain >> 16) & 0x1FFF;
3687

3688 3689 3690 3691
		if (dev->phy.rev >= 7)
			dac_gain = (txgain >> 8) & 0x7;
		else
			dac_gain = (txgain >> 8) & 0x3F;
3692
		bbmult = txgain & 0xFF;
3693

3694 3695 3696 3697 3698 3699 3700 3701
		if (dev->phy.rev >= 3) {
			if (i == 0)
				b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100);
			else
				b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100);
		} else {
			b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000);
		}
3702

3703 3704 3705 3706
		if (i == 0)
			b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN1, dac_gain);
		else
			b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN2, dac_gain);
3707

3708
		b43_ntab_write(dev, B43_NTAB16(0x7, 0x110 + i), radio_gain);
3709

3710
		tmp = b43_ntab_read(dev, B43_NTAB16(0xF, 0x57));
3711 3712 3713 3714
		if (i == 0)
			tmp = (tmp & 0x00FF) | (bbmult << 8);
		else
			tmp = (tmp & 0xFF00) | bbmult;
3715
		b43_ntab_write(dev, B43_NTAB16(0xF, 0x57), tmp);
3716

3717 3718 3719 3720
		if (b43_nphy_ipa(dev)) {
			u32 tmp32;
			u16 reg = (i == 0) ?
				B43_NPHY_PAPD_EN0 : B43_NPHY_PAPD_EN1;
3721 3722
			tmp32 = b43_ntab_read(dev, B43_NTAB32(26 + i,
							      576 + txpi[i]));
3723 3724
			b43_phy_maskset(dev, reg, 0xE00F, (u32) tmp32 << 4);
			b43_phy_set(dev, reg, 0x4);
3725 3726 3727
		}
	}

3728
	b43_phy_mask(dev, B43_NPHY_BPHY_CTL2, ~B43_NPHY_BPHY_CTL2_LUT);
3729

3730 3731
	if (nphy->hang_avoid)
		b43_nphy_stay_in_carrier_search(dev, 0);
3732
}
3733

3734 3735 3736 3737 3738 3739 3740
static void b43_nphy_ipa_internal_tssi_setup(struct b43_wldev *dev)
{
	struct b43_phy *phy = &dev->phy;

	u8 core;
	u16 r; /* routing */

3741 3742 3743
	if (phy->rev >= 19) {
		/* TODO */
	} else if (phy->rev >= 7) {
3744 3745 3746 3747 3748 3749 3750 3751 3752 3753 3754 3755 3756 3757 3758 3759 3760 3761 3762 3763 3764 3765 3766 3767 3768 3769 3770 3771 3772 3773 3774 3775 3776 3777 3778 3779 3780 3781 3782 3783 3784 3785 3786 3787 3788 3789 3790 3791 3792 3793 3794 3795 3796 3797 3798 3799 3800 3801 3802 3803 3804 3805 3806 3807 3808 3809 3810 3811 3812 3813 3814 3815 3816 3817 3818 3819 3820 3821 3822 3823 3824 3825 3826 3827 3828 3829 3830
		for (core = 0; core < 2; core++) {
			r = core ? 0x190 : 0x170;
			if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
				b43_radio_write(dev, r + 0x5, 0x5);
				b43_radio_write(dev, r + 0x9, 0xE);
				if (phy->rev != 5)
					b43_radio_write(dev, r + 0xA, 0);
				if (phy->rev != 7)
					b43_radio_write(dev, r + 0xB, 1);
				else
					b43_radio_write(dev, r + 0xB, 0x31);
			} else {
				b43_radio_write(dev, r + 0x5, 0x9);
				b43_radio_write(dev, r + 0x9, 0xC);
				b43_radio_write(dev, r + 0xB, 0x0);
				if (phy->rev != 5)
					b43_radio_write(dev, r + 0xA, 1);
				else
					b43_radio_write(dev, r + 0xA, 0x31);
			}
			b43_radio_write(dev, r + 0x6, 0);
			b43_radio_write(dev, r + 0x7, 0);
			b43_radio_write(dev, r + 0x8, 3);
			b43_radio_write(dev, r + 0xC, 0);
		}
	} else {
		if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
			b43_radio_write(dev, B2056_SYN_RESERVED_ADDR31, 0x128);
		else
			b43_radio_write(dev, B2056_SYN_RESERVED_ADDR31, 0x80);
		b43_radio_write(dev, B2056_SYN_RESERVED_ADDR30, 0);
		b43_radio_write(dev, B2056_SYN_GPIO_MASTER1, 0x29);

		for (core = 0; core < 2; core++) {
			r = core ? B2056_TX1 : B2056_TX0;

			b43_radio_write(dev, r | B2056_TX_IQCAL_VCM_HG, 0);
			b43_radio_write(dev, r | B2056_TX_IQCAL_IDAC, 0);
			b43_radio_write(dev, r | B2056_TX_TSSI_VCM, 3);
			b43_radio_write(dev, r | B2056_TX_TX_AMP_DET, 0);
			b43_radio_write(dev, r | B2056_TX_TSSI_MISC1, 8);
			b43_radio_write(dev, r | B2056_TX_TSSI_MISC2, 0);
			b43_radio_write(dev, r | B2056_TX_TSSI_MISC3, 0);
			if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
				b43_radio_write(dev, r | B2056_TX_TX_SSI_MASTER,
						0x5);
				if (phy->rev != 5)
					b43_radio_write(dev, r | B2056_TX_TSSIA,
							0x00);
				if (phy->rev >= 5)
					b43_radio_write(dev, r | B2056_TX_TSSIG,
							0x31);
				else
					b43_radio_write(dev, r | B2056_TX_TSSIG,
							0x11);
				b43_radio_write(dev, r | B2056_TX_TX_SSI_MUX,
						0xE);
			} else {
				b43_radio_write(dev, r | B2056_TX_TX_SSI_MASTER,
						0x9);
				b43_radio_write(dev, r | B2056_TX_TSSIA, 0x31);
				b43_radio_write(dev, r | B2056_TX_TSSIG, 0x0);
				b43_radio_write(dev, r | B2056_TX_TX_SSI_MUX,
						0xC);
			}
		}
	}
}

/*
 * Stop radio and transmit known signal. Then check received signal strength to
 * get TSSI (Transmit Signal Strength Indicator).
 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlIdleTssi
 */
static void b43_nphy_tx_power_ctl_idle_tssi(struct b43_wldev *dev)
{
	struct b43_phy *phy = &dev->phy;
	struct b43_phy_n *nphy = dev->phy.n;

	u32 tmp;
	s32 rssi[4] = { };

	/* TODO: check if we can transmit */

	if (b43_nphy_ipa(dev))
		b43_nphy_ipa_internal_tssi_setup(dev);

3831 3832 3833
	if (phy->rev >= 19)
		b43_nphy_rf_ctl_override_rev19(dev, 0x2000, 0, 3, false, 0);
	else if (phy->rev >= 7)
3834
		b43_nphy_rf_ctl_override_rev7(dev, 0x2000, 0, 3, false, 0);
3835
	else if (phy->rev >= 3)
3836
		b43_nphy_rf_ctl_override(dev, 0x2000, 0, 3, false);
3837 3838

	b43_nphy_stop_playback(dev);
3839
	b43_nphy_tx_tone(dev, 4000, 0, false, false, false);
3840
	udelay(20);
3841
	tmp = b43_nphy_poll_rssi(dev, N_RSSI_TSSI_2G, rssi, 1);
3842
	b43_nphy_stop_playback(dev);
3843

3844
	b43_nphy_rssi_select(dev, 0, N_RSSI_W1);
3845

3846 3847 3848
	if (phy->rev >= 19)
		b43_nphy_rf_ctl_override_rev19(dev, 0x2000, 0, 3, true, 0);
	else if (phy->rev >= 7)
3849
		b43_nphy_rf_ctl_override_rev7(dev, 0x2000, 0, 3, true, 0);
3850
	else if (phy->rev >= 3)
3851
		b43_nphy_rf_ctl_override(dev, 0x2000, 0, 3, true);
3852

3853 3854 3855 3856
	if (phy->rev >= 19) {
		/* TODO */
		return;
	} else if (phy->rev >= 3) {
3857 3858 3859 3860 3861 3862 3863 3864 3865 3866
		nphy->pwr_ctl_info[0].idle_tssi_5g = (tmp >> 24) & 0xFF;
		nphy->pwr_ctl_info[1].idle_tssi_5g = (tmp >> 8) & 0xFF;
	} else {
		nphy->pwr_ctl_info[0].idle_tssi_5g = (tmp >> 16) & 0xFF;
		nphy->pwr_ctl_info[1].idle_tssi_5g = tmp & 0xFF;
	}
	nphy->pwr_ctl_info[0].idle_tssi_2g = (tmp >> 24) & 0xFF;
	nphy->pwr_ctl_info[1].idle_tssi_2g = (tmp >> 8) & 0xFF;
}

3867 3868 3869 3870 3871 3872 3873 3874
/* http://bcm-v4.sipsolutions.net/PHY/N/TxPwrLimitToTbl */
static void b43_nphy_tx_prepare_adjusted_power_table(struct b43_wldev *dev)
{
	struct b43_phy_n *nphy = dev->phy.n;

	u8 idx, delta;
	u8 i, stf_mode;

3875 3876 3877 3878 3879 3880 3881 3882 3883 3884 3885 3886 3887 3888
	/* Array adj_pwr_tbl corresponds to the hardware table. It consists of
	 * 21 groups, each containing 4 entries.
	 *
	 * First group has entries for CCK modulation.
	 * The rest of groups has 1 entry per modulation (SISO, CDD, STBC, SDM).
	 *
	 * Group 0 is for CCK
	 * Groups 1..4 use BPSK (group per coding rate)
	 * Groups 5..8 use QPSK (group per coding rate)
	 * Groups 9..12 use 16-QAM (group per coding rate)
	 * Groups 13..16 use 64-QAM (group per coding rate)
	 * Groups 17..20 are unknown
	 */

3889 3890 3891 3892 3893 3894 3895
	for (i = 0; i < 4; i++)
		nphy->adj_pwr_tbl[i] = nphy->tx_power_offset[i];

	for (stf_mode = 0; stf_mode < 4; stf_mode++) {
		delta = 0;
		switch (stf_mode) {
		case 0:
3896
			if (b43_is_40mhz(dev) && dev->phy.rev >= 5) {
3897 3898 3899
				idx = 68;
			} else {
				delta = 1;
3900
				idx = b43_is_40mhz(dev) ? 52 : 4;
3901 3902 3903
			}
			break;
		case 1:
3904
			idx = b43_is_40mhz(dev) ? 76 : 28;
3905 3906
			break;
		case 2:
3907
			idx = b43_is_40mhz(dev) ? 84 : 36;
3908 3909
			break;
		case 3:
3910
			idx = b43_is_40mhz(dev) ? 92 : 44;
3911 3912 3913 3914 3915 3916 3917 3918 3919 3920 3921 3922 3923 3924 3925 3926 3927 3928 3929 3930
			break;
		}

		for (i = 0; i < 20; i++) {
			nphy->adj_pwr_tbl[4 + 4 * i + stf_mode] =
				nphy->tx_power_offset[idx];
			if (i == 0)
				idx += delta;
			if (i == 14)
				idx += 1 - delta;
			if (i == 3 || i == 4 || i == 7 || i == 8 || i == 11 ||
			    i == 13)
				idx += 1;
		}
	}
}

/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlSetup */
static void b43_nphy_tx_power_ctl_setup(struct b43_wldev *dev)
{
3931
	struct b43_phy *phy = &dev->phy;
3932 3933 3934 3935 3936 3937 3938 3939 3940
	struct b43_phy_n *nphy = dev->phy.n;
	struct ssb_sprom *sprom = dev->dev->bus_sprom;

	s16 a1[2], b0[2], b1[2];
	u8 idle[2];
	s8 target[2];
	s32 num, den, pwr;
	u32 regval[64];

3941
	u16 freq = phy->chandef->chan->center_freq;
3942 3943 3944 3945 3946 3947 3948 3949 3950 3951 3952 3953 3954 3955 3956 3957 3958 3959 3960 3961 3962 3963 3964 3965 3966 3967 3968 3969 3970 3971 3972 3973 3974 3975 3976 3977 3978 3979 3980 3981 3982 3983 3984 3985 3986 3987 3988 3989 3990 3991 3992 3993 3994 3995 3996 3997 3998 3999 4000 4001 4002 4003 4004 4005 4006 4007 4008 4009 4010 4011 4012 4013 4014 4015 4016 4017 4018 4019 4020 4021 4022 4023 4024 4025 4026 4027 4028 4029 4030 4031 4032 4033 4034 4035 4036 4037 4038 4039 4040 4041 4042 4043 4044 4045 4046 4047
	u16 tmp;
	u16 r; /* routing */
	u8 i, c;

	if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12) {
		b43_maskset32(dev, B43_MMIO_MACCTL, ~0, 0x200000);
		b43_read32(dev, B43_MMIO_MACCTL);
		udelay(1);
	}

	if (nphy->hang_avoid)
		b43_nphy_stay_in_carrier_search(dev, true);

	b43_phy_set(dev, B43_NPHY_TSSIMODE, B43_NPHY_TSSIMODE_EN);
	if (dev->phy.rev >= 3)
		b43_phy_mask(dev, B43_NPHY_TXPCTL_CMD,
			     ~B43_NPHY_TXPCTL_CMD_PCTLEN & 0xFFFF);
	else
		b43_phy_set(dev, B43_NPHY_TXPCTL_CMD,
			    B43_NPHY_TXPCTL_CMD_PCTLEN);

	if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12)
		b43_maskset32(dev, B43_MMIO_MACCTL, ~0x200000, 0);

	if (sprom->revision < 4) {
		idle[0] = nphy->pwr_ctl_info[0].idle_tssi_2g;
		idle[1] = nphy->pwr_ctl_info[1].idle_tssi_2g;
		target[0] = target[1] = 52;
		a1[0] = a1[1] = -424;
		b0[0] = b0[1] = 5612;
		b1[0] = b1[1] = -1393;
	} else {
		if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
			for (c = 0; c < 2; c++) {
				idle[c] = nphy->pwr_ctl_info[c].idle_tssi_2g;
				target[c] = sprom->core_pwr_info[c].maxpwr_2g;
				a1[c] = sprom->core_pwr_info[c].pa_2g[0];
				b0[c] = sprom->core_pwr_info[c].pa_2g[1];
				b1[c] = sprom->core_pwr_info[c].pa_2g[2];
			}
		} else if (freq >= 4900 && freq < 5100) {
			for (c = 0; c < 2; c++) {
				idle[c] = nphy->pwr_ctl_info[c].idle_tssi_5g;
				target[c] = sprom->core_pwr_info[c].maxpwr_5gl;
				a1[c] = sprom->core_pwr_info[c].pa_5gl[0];
				b0[c] = sprom->core_pwr_info[c].pa_5gl[1];
				b1[c] = sprom->core_pwr_info[c].pa_5gl[2];
			}
		} else if (freq >= 5100 && freq < 5500) {
			for (c = 0; c < 2; c++) {
				idle[c] = nphy->pwr_ctl_info[c].idle_tssi_5g;
				target[c] = sprom->core_pwr_info[c].maxpwr_5g;
				a1[c] = sprom->core_pwr_info[c].pa_5g[0];
				b0[c] = sprom->core_pwr_info[c].pa_5g[1];
				b1[c] = sprom->core_pwr_info[c].pa_5g[2];
			}
		} else if (freq >= 5500) {
			for (c = 0; c < 2; c++) {
				idle[c] = nphy->pwr_ctl_info[c].idle_tssi_5g;
				target[c] = sprom->core_pwr_info[c].maxpwr_5gh;
				a1[c] = sprom->core_pwr_info[c].pa_5gh[0];
				b0[c] = sprom->core_pwr_info[c].pa_5gh[1];
				b1[c] = sprom->core_pwr_info[c].pa_5gh[2];
			}
		} else {
			idle[0] = nphy->pwr_ctl_info[0].idle_tssi_5g;
			idle[1] = nphy->pwr_ctl_info[1].idle_tssi_5g;
			target[0] = target[1] = 52;
			a1[0] = a1[1] = -424;
			b0[0] = b0[1] = 5612;
			b1[0] = b1[1] = -1393;
		}
	}
	/* target[0] = target[1] = nphy->tx_power_max; */

	if (dev->phy.rev >= 3) {
		if (sprom->fem.ghz2.tssipos)
			b43_phy_set(dev, B43_NPHY_TXPCTL_ITSSI, 0x4000);
		if (dev->phy.rev >= 7) {
			for (c = 0; c < 2; c++) {
				r = c ? 0x190 : 0x170;
				if (b43_nphy_ipa(dev))
					b43_radio_write(dev, r + 0x9, (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) ? 0xE : 0xC);
			}
		} else {
			if (b43_nphy_ipa(dev)) {
				tmp = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 0xC : 0xE;
				b43_radio_write(dev,
					B2056_TX0 | B2056_TX_TX_SSI_MUX, tmp);
				b43_radio_write(dev,
					B2056_TX1 | B2056_TX_TX_SSI_MUX, tmp);
			} else {
				b43_radio_write(dev,
					B2056_TX0 | B2056_TX_TX_SSI_MUX, 0x11);
				b43_radio_write(dev,
					B2056_TX1 | B2056_TX_TX_SSI_MUX, 0x11);
			}
		}
	}

	if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12) {
		b43_maskset32(dev, B43_MMIO_MACCTL, ~0, 0x200000);
		b43_read32(dev, B43_MMIO_MACCTL);
		udelay(1);
	}

4048 4049 4050
	if (phy->rev >= 19) {
		/* TODO */
	} else if (phy->rev >= 7) {
4051 4052 4053 4054 4055 4056 4057 4058 4059 4060 4061 4062 4063 4064 4065 4066 4067 4068 4069 4070 4071 4072 4073 4074 4075 4076 4077 4078 4079 4080 4081 4082 4083 4084 4085 4086 4087 4088 4089 4090 4091 4092 4093 4094 4095 4096
		b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
				~B43_NPHY_TXPCTL_CMD_INIT, 0x19);
		b43_phy_maskset(dev, B43_NPHY_TXPCTL_INIT,
				~B43_NPHY_TXPCTL_INIT_PIDXI1, 0x19);
	} else {
		b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
				~B43_NPHY_TXPCTL_CMD_INIT, 0x40);
		if (dev->phy.rev > 1)
			b43_phy_maskset(dev, B43_NPHY_TXPCTL_INIT,
				~B43_NPHY_TXPCTL_INIT_PIDXI1, 0x40);
	}

	if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12)
		b43_maskset32(dev, B43_MMIO_MACCTL, ~0x200000, 0);

	b43_phy_write(dev, B43_NPHY_TXPCTL_N,
		      0xF0 << B43_NPHY_TXPCTL_N_TSSID_SHIFT |
		      3 << B43_NPHY_TXPCTL_N_NPTIL2_SHIFT);
	b43_phy_write(dev, B43_NPHY_TXPCTL_ITSSI,
		      idle[0] << B43_NPHY_TXPCTL_ITSSI_0_SHIFT |
		      idle[1] << B43_NPHY_TXPCTL_ITSSI_1_SHIFT |
		      B43_NPHY_TXPCTL_ITSSI_BINF);
	b43_phy_write(dev, B43_NPHY_TXPCTL_TPWR,
		      target[0] << B43_NPHY_TXPCTL_TPWR_0_SHIFT |
		      target[1] << B43_NPHY_TXPCTL_TPWR_1_SHIFT);

	for (c = 0; c < 2; c++) {
		for (i = 0; i < 64; i++) {
			num = 8 * (16 * b0[c] + b1[c] * i);
			den = 32768 + a1[c] * i;
			pwr = max((4 * num + den / 2) / den, -8);
			if (dev->phy.rev < 3 && (i <= (31 - idle[c] + 1)))
				pwr = max(pwr, target[c] + 1);
			regval[i] = pwr;
		}
		b43_ntab_write_bulk(dev, B43_NTAB32(26 + c, 0), 64, regval);
	}

	b43_nphy_tx_prepare_adjusted_power_table(dev);
	b43_ntab_write_bulk(dev, B43_NTAB16(26, 64), 84, nphy->adj_pwr_tbl);
	b43_ntab_write_bulk(dev, B43_NTAB16(27, 64), 84, nphy->adj_pwr_tbl);

	if (nphy->hang_avoid)
		b43_nphy_stay_in_carrier_search(dev, false);
}

4097 4098 4099
static void b43_nphy_tx_gain_table_upload(struct b43_wldev *dev)
{
	struct b43_phy *phy = &dev->phy;
4100

4101 4102 4103 4104 4105
	const u32 *table = NULL;
	u32 rfpwr_offset;
	u8 pga_gain;
	int i;

4106
	table = b43_nphy_get_tx_gain_table(dev);
4107 4108 4109
	if (!table)
		return;

4110 4111 4112
	b43_ntab_write_bulk(dev, B43_NTAB32(26, 192), 128, table);
	b43_ntab_write_bulk(dev, B43_NTAB32(27, 192), 128, table);

4113 4114 4115
	if (phy->rev < 3)
		return;

4116
#if 0
4117
	nphy->gmval = (table[0] >> 16) & 0x7000;
4118
#endif
4119

4120 4121 4122 4123 4124 4125 4126 4127
	for (i = 0; i < 128; i++) {
		if (phy->rev >= 19) {
			/* TODO */
			return;
		} else if (phy->rev >= 7) {
			/* TODO */
			return;
		} else {
4128 4129
			pga_gain = (table[i] >> 24) & 0xF;
			if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
4130
				rfpwr_offset = b43_ntab_papd_pga_gain_delta_ipa_2g[pga_gain];
4131
			else
4132
				rfpwr_offset = 0; /* FIXME */
4133
		}
4134 4135 4136

		b43_ntab_write(dev, B43_NTAB32(26, 576 + i), rfpwr_offset);
		b43_ntab_write(dev, B43_NTAB32(27, 576 + i), rfpwr_offset);
4137 4138 4139
	}
}

4140 4141
/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PA%20override */
static void b43_nphy_pa_override(struct b43_wldev *dev, bool enable)
4142
{
4143 4144 4145
	struct b43_phy_n *nphy = dev->phy.n;
	enum ieee80211_band band;
	u16 tmp;
4146

4147 4148 4149 4150 4151 4152
	if (!enable) {
		nphy->rfctrl_intc1_save = b43_phy_read(dev,
						       B43_NPHY_RFCTL_INTC1);
		nphy->rfctrl_intc2_save = b43_phy_read(dev,
						       B43_NPHY_RFCTL_INTC2);
		band = b43_current_band(dev->wl);
4153
		if (dev->phy.rev >= 7) {
4154
			tmp = 0x1480;
4155
		} else if (dev->phy.rev >= 3) {
4156 4157 4158 4159 4160 4161 4162 4163 4164 4165 4166 4167 4168 4169 4170 4171 4172
			if (band == IEEE80211_BAND_5GHZ)
				tmp = 0x600;
			else
				tmp = 0x480;
		} else {
			if (band == IEEE80211_BAND_5GHZ)
				tmp = 0x180;
			else
				tmp = 0x120;
		}
		b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
		b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
	} else {
		b43_phy_write(dev, B43_NPHY_RFCTL_INTC1,
				nphy->rfctrl_intc1_save);
		b43_phy_write(dev, B43_NPHY_RFCTL_INTC2,
				nphy->rfctrl_intc2_save);
4173 4174 4175
	}
}

4176 4177 4178 4179 4180
/*
 * TX low-pass filter bandwidth setup
 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxLpFbw
 */
static void b43_nphy_tx_lpf_bw(struct b43_wldev *dev)
4181 4182 4183
{
	u16 tmp;

4184 4185
	if (dev->phy.rev < 3 || dev->phy.rev >= 7)
		return;
4186

4187 4188 4189 4190 4191 4192 4193 4194 4195
	if (b43_nphy_ipa(dev))
		tmp = b43_is_40mhz(dev) ? 5 : 4;
	else
		tmp = b43_is_40mhz(dev) ? 3 : 1;
	b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S2,
		      (tmp << 9) | (tmp << 6) | (tmp << 3) | tmp);

	if (b43_nphy_ipa(dev)) {
		tmp = b43_is_40mhz(dev) ? 4 : 1;
4196
		b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S2,
4197
			      (tmp << 9) | (tmp << 6) | (tmp << 3) | tmp);
4198 4199
	}
}
4200

4201 4202 4203
/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqEst */
static void b43_nphy_rx_iq_est(struct b43_wldev *dev, struct nphy_iq_est *est,
				u16 samps, u8 time, bool wait)
4204
{
4205 4206
	int i;
	u16 tmp;
4207

4208 4209 4210 4211
	b43_phy_write(dev, B43_NPHY_IQEST_SAMCNT, samps);
	b43_phy_maskset(dev, B43_NPHY_IQEST_WT, ~B43_NPHY_IQEST_WT_VAL, time);
	if (wait)
		b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_MODE);
4212
	else
4213
		b43_phy_mask(dev, B43_NPHY_IQEST_CMD, ~B43_NPHY_IQEST_CMD_MODE);
4214

4215
	b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_START);
4216

4217 4218 4219 4220 4221 4222 4223 4224 4225
	for (i = 1000; i; i--) {
		tmp = b43_phy_read(dev, B43_NPHY_IQEST_CMD);
		if (!(tmp & B43_NPHY_IQEST_CMD_START)) {
			est->i0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI0) << 16) |
					b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO0);
			est->q0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI0) << 16) |
					b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO0);
			est->iq0_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI0) << 16) |
					b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO0);
4226

4227 4228 4229 4230 4231 4232 4233
			est->i1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI1) << 16) |
					b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO1);
			est->q1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI1) << 16) |
					b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO1);
			est->iq1_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI1) << 16) |
					b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO1);
			return;
4234
		}
4235
		udelay(10);
4236
	}
4237
	memset(est, 0, sizeof(*est));
4238 4239
}

4240 4241 4242
/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqCoeffs */
static void b43_nphy_rx_iq_coeffs(struct b43_wldev *dev, bool write,
					struct b43_phy_n_iq_comp *pcomp)
4243
{
4244 4245 4246 4247 4248
	if (write) {
		b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPA0, pcomp->a0);
		b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPB0, pcomp->b0);
		b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPA1, pcomp->a1);
		b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPB1, pcomp->b1);
4249
	} else {
4250 4251 4252 4253 4254 4255
		pcomp->a0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPA0);
		pcomp->b0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPB0);
		pcomp->a1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPA1);
		pcomp->b1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPB1);
	}
}
4256

4257 4258
#if 0
/* Ready but not used anywhere */
4259 4260 4261 4262
/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhyCleanup */
static void b43_nphy_rx_cal_phy_cleanup(struct b43_wldev *dev, u8 core)
{
	u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
4263

4264 4265 4266 4267 4268 4269 4270 4271 4272 4273 4274 4275 4276 4277 4278 4279 4280
	b43_phy_write(dev, B43_NPHY_RFSEQCA, regs[0]);
	if (core == 0) {
		b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[1]);
		b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
	} else {
		b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
		b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
	}
	b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[3]);
	b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[4]);
	b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, regs[5]);
	b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, regs[6]);
	b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, regs[7]);
	b43_phy_write(dev, B43_NPHY_RFCTL_OVER, regs[8]);
	b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
	b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
}
4281

4282 4283 4284 4285 4286
/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhySetup */
static void b43_nphy_rx_cal_phy_setup(struct b43_wldev *dev, u8 core)
{
	u8 rxval, txval;
	u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
4287

4288 4289 4290 4291 4292 4293 4294 4295 4296 4297 4298 4299 4300 4301 4302 4303
	regs[0] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
	if (core == 0) {
		regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
		regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
	} else {
		regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
		regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
	}
	regs[3] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
	regs[4] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
	regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
	regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
	regs[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S1);
	regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
	regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
	regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
4304

4305 4306
	b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
	b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
4307

4308 4309
	b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
			~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF,
4310 4311 4312 4313 4314 4315 4316
			((1 - core) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
	b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
			((1 - core) << B43_NPHY_RFSEQCA_TXEN_SHIFT));
	b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
			(core << B43_NPHY_RFSEQCA_RXEN_SHIFT));
	b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXDIS,
			(core << B43_NPHY_RFSEQCA_TXDIS_SHIFT));
4317

4318 4319 4320 4321 4322 4323 4324
	if (core == 0) {
		b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x0007);
		b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0007);
	} else {
		b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x0007);
		b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0007);
	}
4325

4326
	b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_PA, 0, 3);
4327
	b43_nphy_rf_ctl_override(dev, 8, 0, 3, false);
4328
	b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
4329

4330 4331 4332 4333 4334 4335
	if (core == 0) {
		rxval = 1;
		txval = 8;
	} else {
		rxval = 4;
		txval = 2;
4336
	}
4337 4338 4339 4340
	b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, rxval,
				      core + 1);
	b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, txval,
				      2 - core);
4341
}
4342
#endif
4343

4344 4345
/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalcRxIqComp */
static void b43_nphy_calc_rx_iq_comp(struct b43_wldev *dev, u8 mask)
4346 4347
{
	int i;
4348 4349 4350 4351 4352 4353 4354 4355 4356 4357 4358 4359 4360 4361 4362 4363 4364 4365 4366 4367
	s32 iq;
	u32 ii;
	u32 qq;
	int iq_nbits, qq_nbits;
	int arsh, brsh;
	u16 tmp, a, b;

	struct nphy_iq_est est;
	struct b43_phy_n_iq_comp old;
	struct b43_phy_n_iq_comp new = { };
	bool error = false;

	if (mask == 0)
		return;

	b43_nphy_rx_iq_coeffs(dev, false, &old);
	b43_nphy_rx_iq_coeffs(dev, true, &new);
	b43_nphy_rx_iq_est(dev, &est, 0x4000, 32, false);
	new = old;

4368
	for (i = 0; i < 2; i++) {
4369 4370 4371 4372 4373 4374 4375 4376
		if (i == 0 && (mask & 1)) {
			iq = est.iq0_prod;
			ii = est.i0_pwr;
			qq = est.q0_pwr;
		} else if (i == 1 && (mask & 2)) {
			iq = est.iq1_prod;
			ii = est.i1_pwr;
			qq = est.q1_pwr;
4377
		} else {
4378
			continue;
4379 4380
		}

4381 4382 4383 4384
		if (ii + qq < 2) {
			error = true;
			break;
		}
4385

4386 4387
		iq_nbits = fls(abs(iq));
		qq_nbits = fls(qq);
4388

4389 4390 4391 4392 4393 4394 4395 4396 4397 4398 4399 4400 4401
		arsh = iq_nbits - 20;
		if (arsh >= 0) {
			a = -((iq << (30 - iq_nbits)) + (ii >> (1 + arsh)));
			tmp = ii >> arsh;
		} else {
			a = -((iq << (30 - iq_nbits)) + (ii << (-1 - arsh)));
			tmp = ii << -arsh;
		}
		if (tmp == 0) {
			error = true;
			break;
		}
		a /= tmp;
4402

4403 4404 4405 4406
		brsh = qq_nbits - 11;
		if (brsh >= 0) {
			b = (qq << (31 - qq_nbits));
			tmp = ii >> brsh;
4407
		} else {
4408 4409 4410 4411 4412 4413
			b = (qq << (31 - qq_nbits));
			tmp = ii << -brsh;
		}
		if (tmp == 0) {
			error = true;
			break;
4414
		}
4415
		b = int_sqrt(b / tmp - a * a) - (1 << 10);
4416

4417 4418 4419 4420 4421 4422 4423 4424 4425 4426 4427 4428 4429 4430 4431 4432 4433
		if (i == 0 && (mask & 0x1)) {
			if (dev->phy.rev >= 3) {
				new.a0 = a & 0x3FF;
				new.b0 = b & 0x3FF;
			} else {
				new.a0 = b & 0x3FF;
				new.b0 = a & 0x3FF;
			}
		} else if (i == 1 && (mask & 0x2)) {
			if (dev->phy.rev >= 3) {
				new.a1 = a & 0x3FF;
				new.b1 = b & 0x3FF;
			} else {
				new.a1 = b & 0x3FF;
				new.b1 = a & 0x3FF;
			}
		}
4434 4435
	}

4436 4437
	if (error)
		new = old;
4438

4439 4440
	b43_nphy_rx_iq_coeffs(dev, true, &new);
}
4441

4442 4443 4444 4445
/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxIqWar */
static void b43_nphy_tx_iq_workaround(struct b43_wldev *dev)
{
	u16 array[4];
4446
	b43_ntab_read_bulk(dev, B43_NTAB16(0xF, 0x50), 4, array);
4447 4448 4449 4450 4451

	b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW0, array[0]);
	b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW1, array[1]);
	b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW2, array[2]);
	b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW3, array[3]);
4452 4453
}

4454 4455 4456 4457
/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SpurWar */
static void b43_nphy_spur_workaround(struct b43_wldev *dev)
{
	struct b43_phy_n *nphy = dev->phy.n;
4458

4459
	u8 channel = dev->phy.channel;
4460 4461
	int tone[2] = { 57, 58 };
	u32 noise[2] = { 0x3FF, 0x3FF };
4462

4463
	B43_WARN_ON(dev->phy.rev < 3);
4464

4465 4466
	if (nphy->hang_avoid)
		b43_nphy_stay_in_carrier_search(dev, 1);
4467

4468 4469
	if (nphy->gband_spurwar_en) {
		/* TODO: N PHY Adjust Analog Pfbw (7) */
4470
		if (channel == 11 && b43_is_40mhz(dev))
4471 4472 4473 4474
			; /* TODO: N PHY Adjust Min Noise Var(2, tone, noise)*/
		else
			; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
		/* TODO: N PHY Adjust CRS Min Power (0x1E) */
4475 4476
	}

4477 4478 4479 4480 4481 4482 4483 4484 4485 4486 4487
	if (nphy->aband_spurwar_en) {
		if (channel == 54) {
			tone[0] = 0x20;
			noise[0] = 0x25F;
		} else if (channel == 38 || channel == 102 || channel == 118) {
			if (0 /* FIXME */) {
				tone[0] = 0x20;
				noise[0] = 0x21F;
			} else {
				tone[0] = 0;
				noise[0] = 0;
4488
			}
4489 4490 4491 4492 4493 4494 4495 4496 4497 4498 4499 4500
		} else if (channel == 134) {
			tone[0] = 0x20;
			noise[0] = 0x21F;
		} else if (channel == 151) {
			tone[0] = 0x10;
			noise[0] = 0x23F;
		} else if (channel == 153 || channel == 161) {
			tone[0] = 0x30;
			noise[0] = 0x23F;
		} else {
			tone[0] = 0;
			noise[0] = 0;
4501 4502
		}

4503 4504
		if (!tone[0] && !noise[0])
			; /* TODO: N PHY Adjust Min Noise Var(1, tone, noise)*/
4505
		else
4506 4507
			; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
	}
4508

4509 4510 4511
	if (nphy->hang_avoid)
		b43_nphy_stay_in_carrier_search(dev, 0);
}
4512

4513 4514 4515 4516 4517 4518 4519
/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlCoefSetup */
static void b43_nphy_tx_pwr_ctrl_coef_setup(struct b43_wldev *dev)
{
	struct b43_phy_n *nphy = dev->phy.n;
	int i, j;
	u32 tmp;
	u32 cur_real, cur_imag, real_part, imag_part;
4520

4521
	u16 buffer[7];
4522

4523 4524
	if (nphy->hang_avoid)
		b43_nphy_stay_in_carrier_search(dev, true);
4525

4526
	b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
4527

4528 4529 4530 4531 4532 4533 4534 4535 4536 4537
	for (i = 0; i < 2; i++) {
		tmp = ((buffer[i * 2] & 0x3FF) << 10) |
			(buffer[i * 2 + 1] & 0x3FF);
		b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
				(((i + 26) << 10) | 320));
		for (j = 0; j < 128; j++) {
			b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
					((tmp >> 16) & 0xFFFF));
			b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
					(tmp & 0xFFFF));
4538 4539 4540
		}
	}

4541 4542 4543 4544 4545 4546
	for (i = 0; i < 2; i++) {
		tmp = buffer[5 + i];
		real_part = (tmp >> 8) & 0xFF;
		imag_part = (tmp & 0xFF);
		b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
				(((i + 26) << 10) | 448));
4547

4548 4549 4550 4551 4552
		if (dev->phy.rev >= 3) {
			cur_real = real_part;
			cur_imag = imag_part;
			tmp = ((cur_real & 0xFF) << 8) | (cur_imag & 0xFF);
		}
4553

4554 4555 4556 4557 4558 4559 4560 4561 4562 4563 4564 4565
		for (j = 0; j < 128; j++) {
			if (dev->phy.rev < 3) {
				cur_real = (real_part * loscale[j] + 128) >> 8;
				cur_imag = (imag_part * loscale[j] + 128) >> 8;
				tmp = ((cur_real & 0xFF) << 8) |
					(cur_imag & 0xFF);
			}
			b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
					((tmp >> 16) & 0xFFFF));
			b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
					(tmp & 0xFFFF));
		}
4566
	}
4567 4568

	if (dev->phy.rev >= 3) {
4569 4570 4571 4572
		b43_shm_write16(dev, B43_SHM_SHARED,
				B43_SHM_SH_NPHY_TXPWR_INDX0, 0xFFFF);
		b43_shm_write16(dev, B43_SHM_SHARED,
				B43_SHM_SH_NPHY_TXPWR_INDX1, 0xFFFF);
4573
	}
4574

4575 4576
	if (nphy->hang_avoid)
		b43_nphy_stay_in_carrier_search(dev, false);
4577 4578
}

4579 4580 4581 4582 4583 4584 4585 4586 4587 4588 4589 4590
/*
 * Restore RSSI Calibration
 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreRssiCal
 */
static void b43_nphy_restore_rssi_cal(struct b43_wldev *dev)
{
	struct b43_phy_n *nphy = dev->phy.n;

	u16 *rssical_radio_regs = NULL;
	u16 *rssical_phy_regs = NULL;

	if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
4591
		if (!nphy->rssical_chanspec_2G.center_freq)
4592 4593 4594 4595
			return;
		rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G;
		rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G;
	} else {
4596
		if (!nphy->rssical_chanspec_5G.center_freq)
4597 4598 4599 4600 4601
			return;
		rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G;
		rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G;
	}

4602 4603 4604
	if (dev->phy.rev >= 19) {
		/* TODO */
	} else if (dev->phy.rev >= 7) {
4605 4606 4607 4608
		b43_radio_maskset(dev, R2057_NB_MASTER_CORE0, ~R2057_VCM_MASK,
				  rssical_radio_regs[0]);
		b43_radio_maskset(dev, R2057_NB_MASTER_CORE1, ~R2057_VCM_MASK,
				  rssical_radio_regs[1]);
4609 4610 4611 4612 4613 4614
	} else {
		b43_radio_maskset(dev, B2056_RX0 | B2056_RX_RSSI_MISC, 0xE3,
				  rssical_radio_regs[0]);
		b43_radio_maskset(dev, B2056_RX1 | B2056_RX_RSSI_MISC, 0xE3,
				  rssical_radio_regs[1]);
	}
4615 4616 4617 4618 4619 4620 4621 4622 4623 4624 4625 4626 4627 4628 4629 4630 4631

	b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, rssical_phy_regs[0]);
	b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, rssical_phy_regs[1]);
	b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, rssical_phy_regs[2]);
	b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, rssical_phy_regs[3]);

	b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, rssical_phy_regs[4]);
	b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, rssical_phy_regs[5]);
	b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, rssical_phy_regs[6]);
	b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, rssical_phy_regs[7]);

	b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, rssical_phy_regs[8]);
	b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, rssical_phy_regs[9]);
	b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, rssical_phy_regs[10]);
	b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, rssical_phy_regs[11]);
}

4632 4633 4634 4635 4636 4637 4638
static void b43_nphy_tx_cal_radio_setup_rev19(struct b43_wldev *dev)
{
	/* TODO */
}

static void b43_nphy_tx_cal_radio_setup_rev7(struct b43_wldev *dev)
{
4639 4640 4641 4642 4643 4644 4645 4646 4647 4648 4649 4650 4651 4652 4653 4654 4655 4656 4657 4658 4659 4660 4661 4662 4663 4664 4665 4666 4667 4668 4669 4670 4671 4672 4673 4674 4675 4676 4677 4678 4679 4680 4681 4682 4683 4684 4685 4686 4687
	struct b43_phy *phy = &dev->phy;
	struct b43_phy_n *nphy = dev->phy.n;
	u16 *save = nphy->tx_rx_cal_radio_saveregs;
	int core, off;
	u16 r, tmp;

	for (core = 0; core < 2; core++) {
		r = core ? 0x20 : 0;
		off = core * 11;

		save[off + 0] = b43_radio_read(dev, r + R2057_TX0_TX_SSI_MASTER);
		save[off + 1] = b43_radio_read(dev, r + R2057_TX0_IQCAL_VCM_HG);
		save[off + 2] = b43_radio_read(dev, r + R2057_TX0_IQCAL_IDAC);
		save[off + 3] = b43_radio_read(dev, r + R2057_TX0_TSSI_VCM);
		save[off + 4] = 0;
		save[off + 5] = b43_radio_read(dev, r + R2057_TX0_TX_SSI_MUX);
		if (phy->radio_rev != 5)
			save[off + 6] = b43_radio_read(dev, r + R2057_TX0_TSSIA);
		save[off + 7] = b43_radio_read(dev, r + R2057_TX0_TSSIG);
		save[off + 8] = b43_radio_read(dev, r + R2057_TX0_TSSI_MISC1);

		if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
			b43_radio_write(dev, r + R2057_TX0_TX_SSI_MASTER, 0xA);
			b43_radio_write(dev, r + R2057_TX0_IQCAL_VCM_HG, 0x43);
			b43_radio_write(dev, r + R2057_TX0_IQCAL_IDAC, 0x55);
			b43_radio_write(dev, r + R2057_TX0_TSSI_VCM, 0);
			b43_radio_write(dev, r + R2057_TX0_TSSIG, 0);
			if (nphy->use_int_tx_iq_lo_cal) {
				b43_radio_write(dev, r + R2057_TX0_TX_SSI_MUX, 0x4);
				tmp = true ? 0x31 : 0x21; /* TODO */
				b43_radio_write(dev, r + R2057_TX0_TSSIA, tmp);
			}
			b43_radio_write(dev, r + R2057_TX0_TSSI_MISC1, 0x00);
		} else {
			b43_radio_write(dev, r + R2057_TX0_TX_SSI_MASTER, 0x6);
			b43_radio_write(dev, r + R2057_TX0_IQCAL_VCM_HG, 0x43);
			b43_radio_write(dev, r + R2057_TX0_IQCAL_IDAC, 0x55);
			b43_radio_write(dev, r + R2057_TX0_TSSI_VCM, 0);

			if (phy->radio_rev != 5)
				b43_radio_write(dev, r + R2057_TX0_TSSIA, 0);
			if (nphy->use_int_tx_iq_lo_cal) {
				b43_radio_write(dev, r + R2057_TX0_TX_SSI_MUX, 0x6);
				tmp = true ? 0x31 : 0x21; /* TODO */
				b43_radio_write(dev, r + R2057_TX0_TSSIG, tmp);
			}
			b43_radio_write(dev, r + R2057_TX0_TSSI_MISC1, 0);
		}
	}
4688 4689
}

4690 4691 4692
/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalRadioSetup */
static void b43_nphy_tx_cal_radio_setup(struct b43_wldev *dev)
{
4693
	struct b43_phy *phy = &dev->phy;
4694 4695
	struct b43_phy_n *nphy = dev->phy.n;
	u16 *save = nphy->tx_rx_cal_radio_saveregs;
4696 4697
	u16 tmp;
	u8 offset, i;
4698

4699 4700 4701 4702 4703
	if (phy->rev >= 19) {
		b43_nphy_tx_cal_radio_setup_rev19(dev);
	} else if (phy->rev >= 7) {
		b43_nphy_tx_cal_radio_setup_rev7(dev);
	} else if (phy->rev >= 3) {
4704 4705 4706 4707
	    for (i = 0; i < 2; i++) {
		tmp = (i == 0) ? 0x2000 : 0x3000;
		offset = i * 11;

4708 4709 4710 4711 4712 4713 4714 4715 4716 4717 4718
		save[offset + 0] = b43_radio_read(dev, B2055_CAL_RVARCTL);
		save[offset + 1] = b43_radio_read(dev, B2055_CAL_LPOCTL);
		save[offset + 2] = b43_radio_read(dev, B2055_CAL_TS);
		save[offset + 3] = b43_radio_read(dev, B2055_CAL_RCCALRTS);
		save[offset + 4] = b43_radio_read(dev, B2055_CAL_RCALRTS);
		save[offset + 5] = b43_radio_read(dev, B2055_PADDRV);
		save[offset + 6] = b43_radio_read(dev, B2055_XOCTL1);
		save[offset + 7] = b43_radio_read(dev, B2055_XOCTL2);
		save[offset + 8] = b43_radio_read(dev, B2055_XOREGUL);
		save[offset + 9] = b43_radio_read(dev, B2055_XOMISC);
		save[offset + 10] = b43_radio_read(dev, B2055_PLL_LFC1);
4719 4720

		if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
4721 4722 4723 4724 4725
			b43_radio_write(dev, tmp | B2055_CAL_RVARCTL, 0x0A);
			b43_radio_write(dev, tmp | B2055_CAL_LPOCTL, 0x40);
			b43_radio_write(dev, tmp | B2055_CAL_TS, 0x55);
			b43_radio_write(dev, tmp | B2055_CAL_RCCALRTS, 0);
			b43_radio_write(dev, tmp | B2055_CAL_RCALRTS, 0);
4726
			if (nphy->ipa5g_on) {
4727 4728
				b43_radio_write(dev, tmp | B2055_PADDRV, 4);
				b43_radio_write(dev, tmp | B2055_XOCTL1, 1);
4729
			} else {
4730 4731
				b43_radio_write(dev, tmp | B2055_PADDRV, 0);
				b43_radio_write(dev, tmp | B2055_XOCTL1, 0x2F);
4732
			}
4733
			b43_radio_write(dev, tmp | B2055_XOCTL2, 0);
4734
		} else {
4735 4736 4737 4738 4739 4740
			b43_radio_write(dev, tmp | B2055_CAL_RVARCTL, 0x06);
			b43_radio_write(dev, tmp | B2055_CAL_LPOCTL, 0x40);
			b43_radio_write(dev, tmp | B2055_CAL_TS, 0x55);
			b43_radio_write(dev, tmp | B2055_CAL_RCCALRTS, 0);
			b43_radio_write(dev, tmp | B2055_CAL_RCALRTS, 0);
			b43_radio_write(dev, tmp | B2055_XOCTL1, 0);
4741
			if (nphy->ipa2g_on) {
4742 4743
				b43_radio_write(dev, tmp | B2055_PADDRV, 6);
				b43_radio_write(dev, tmp | B2055_XOCTL2,
4744 4745
					(dev->phy.rev < 5) ? 0x11 : 0x01);
			} else {
4746 4747
				b43_radio_write(dev, tmp | B2055_PADDRV, 0);
				b43_radio_write(dev, tmp | B2055_XOCTL2, 0);
4748 4749
			}
		}
4750 4751 4752
		b43_radio_write(dev, tmp | B2055_XOREGUL, 0);
		b43_radio_write(dev, tmp | B2055_XOMISC, 0);
		b43_radio_write(dev, tmp | B2055_PLL_LFC1, 0);
4753
	    }
4754
	} else {
4755 4756
		save[0] = b43_radio_read(dev, B2055_C1_TX_RF_IQCAL1);
		b43_radio_write(dev, B2055_C1_TX_RF_IQCAL1, 0x29);
4757

4758 4759
		save[1] = b43_radio_read(dev, B2055_C1_TX_RF_IQCAL2);
		b43_radio_write(dev, B2055_C1_TX_RF_IQCAL2, 0x54);
4760

4761 4762
		save[2] = b43_radio_read(dev, B2055_C2_TX_RF_IQCAL1);
		b43_radio_write(dev, B2055_C2_TX_RF_IQCAL1, 0x29);
4763

4764 4765
		save[3] = b43_radio_read(dev, B2055_C2_TX_RF_IQCAL2);
		b43_radio_write(dev, B2055_C2_TX_RF_IQCAL2, 0x54);
4766

4767 4768
		save[3] = b43_radio_read(dev, B2055_C1_PWRDET_RXTX);
		save[4] = b43_radio_read(dev, B2055_C2_PWRDET_RXTX);
4769 4770 4771

		if (!(b43_phy_read(dev, B43_NPHY_BANDCTL) &
		    B43_NPHY_BANDCTL_5GHZ)) {
4772 4773
			b43_radio_write(dev, B2055_C1_PWRDET_RXTX, 0x04);
			b43_radio_write(dev, B2055_C2_PWRDET_RXTX, 0x04);
4774
		} else {
4775 4776
			b43_radio_write(dev, B2055_C1_PWRDET_RXTX, 0x20);
			b43_radio_write(dev, B2055_C2_PWRDET_RXTX, 0x20);
4777 4778 4779 4780 4781 4782 4783 4784 4785 4786 4787 4788
		}

		if (dev->phy.rev < 2) {
			b43_radio_set(dev, B2055_C1_TX_BB_MXGM, 0x20);
			b43_radio_set(dev, B2055_C2_TX_BB_MXGM, 0x20);
		} else {
			b43_radio_mask(dev, B2055_C1_TX_BB_MXGM, ~0x20);
			b43_radio_mask(dev, B2055_C2_TX_BB_MXGM, ~0x20);
		}
	}
}

4789 4790 4791 4792 4793 4794 4795 4796 4797 4798 4799 4800 4801 4802 4803
/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/UpdateTxCalLadder */
static void b43_nphy_update_tx_cal_ladder(struct b43_wldev *dev, u16 core)
{
	struct b43_phy_n *nphy = dev->phy.n;
	int i;
	u16 scale, entry;

	u16 tmp = nphy->txcal_bbmult;
	if (core == 0)
		tmp >>= 8;
	tmp &= 0xff;

	for (i = 0; i < 18; i++) {
		scale = (ladder_lo[i].percent * tmp) / 100;
		entry = ((scale & 0xFF) << 8) | ladder_lo[i].g_env;
4804
		b43_ntab_write(dev, B43_NTAB16(15, i), entry);
4805 4806 4807

		scale = (ladder_iq[i].percent * tmp) / 100;
		entry = ((scale & 0xFF) << 8) | ladder_iq[i].g_env;
4808
		b43_ntab_write(dev, B43_NTAB16(15, i + 32), entry);
4809 4810 4811
	}
}

4812 4813 4814 4815 4816 4817 4818 4819 4820 4821 4822 4823 4824 4825
/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ExtPaSetTxDigiFilts */
static void b43_nphy_ext_pa_set_tx_dig_filters(struct b43_wldev *dev)
{
	int i;
	for (i = 0; i < 15; i++)
		b43_phy_write(dev, B43_PHY_N(0x2C5 + i),
				tbl_tx_filter_coef_rev4[2][i]);
}

/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IpaSetTxDigiFilts */
static void b43_nphy_int_pa_set_tx_dig_filters(struct b43_wldev *dev)
{
	int i, j;
	/* B43_NPHY_TXF_20CO_S0A1, B43_NPHY_TXF_40CO_S0A1, unknown */
Joe Perches's avatar
Joe Perches committed
4826
	static const u16 offset[] = { 0x186, 0x195, 0x2C5 };
4827 4828 4829 4830 4831 4832

	for (i = 0; i < 3; i++)
		for (j = 0; j < 15; j++)
			b43_phy_write(dev, B43_PHY_N(offset[i] + j),
					tbl_tx_filter_coef_rev4[i][j]);

4833
	if (b43_is_40mhz(dev)) {
4834 4835 4836 4837 4838 4839 4840 4841 4842 4843 4844 4845 4846 4847 4848
		for (j = 0; j < 15; j++)
			b43_phy_write(dev, B43_PHY_N(offset[0] + j),
					tbl_tx_filter_coef_rev4[3][j]);
	} else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
		for (j = 0; j < 15; j++)
			b43_phy_write(dev, B43_PHY_N(offset[0] + j),
					tbl_tx_filter_coef_rev4[5][j]);
	}

	if (dev->phy.channel == 14)
		for (j = 0; j < 15; j++)
			b43_phy_write(dev, B43_PHY_N(offset[0] + j),
					tbl_tx_filter_coef_rev4[6][j]);
}

4849 4850 4851 4852 4853 4854 4855 4856 4857
/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetTxGain */
static struct nphy_txgains b43_nphy_get_tx_gains(struct b43_wldev *dev)
{
	struct b43_phy_n *nphy = dev->phy.n;

	u16 curr_gain[2];
	struct nphy_txgains target;
	const u32 *table = NULL;

4858
	if (!nphy->txpwrctrl) {
4859 4860 4861 4862
		int i;

		if (nphy->hang_avoid)
			b43_nphy_stay_in_carrier_search(dev, true);
4863
		b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, curr_gain);
4864 4865 4866 4867
		if (nphy->hang_avoid)
			b43_nphy_stay_in_carrier_search(dev, false);

		for (i = 0; i < 2; ++i) {
4868 4869 4870 4871 4872 4873 4874
			if (dev->phy.rev >= 7) {
				target.ipa[i] = curr_gain[i] & 0x0007;
				target.pad[i] = (curr_gain[i] & 0x00F8) >> 3;
				target.pga[i] = (curr_gain[i] & 0x0F00) >> 8;
				target.txgm[i] = (curr_gain[i] & 0x7000) >> 12;
				target.tx_lpf[i] = (curr_gain[i] & 0x8000) >> 15;
			} else if (dev->phy.rev >= 3) {
4875 4876 4877 4878 4879 4880 4881 4882 4883 4884 4885 4886 4887 4888 4889 4890 4891 4892 4893 4894 4895 4896
				target.ipa[i] = curr_gain[i] & 0x000F;
				target.pad[i] = (curr_gain[i] & 0x00F0) >> 4;
				target.pga[i] = (curr_gain[i] & 0x0F00) >> 8;
				target.txgm[i] = (curr_gain[i] & 0x7000) >> 12;
			} else {
				target.ipa[i] = curr_gain[i] & 0x0003;
				target.pad[i] = (curr_gain[i] & 0x000C) >> 2;
				target.pga[i] = (curr_gain[i] & 0x0070) >> 4;
				target.txgm[i] = (curr_gain[i] & 0x0380) >> 7;
			}
		}
	} else {
		int i;
		u16 index[2];
		index[0] = (b43_phy_read(dev, B43_NPHY_C1_TXPCTL_STAT) &
			B43_NPHY_TXPCTL_STAT_BIDX) >>
			B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
		index[1] = (b43_phy_read(dev, B43_NPHY_C2_TXPCTL_STAT) &
			B43_NPHY_TXPCTL_STAT_BIDX) >>
			B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;

		for (i = 0; i < 2; ++i) {
4897
			table = b43_nphy_get_tx_gain_table(dev);
4898 4899 4900
			if (!table)
				break;

4901 4902 4903 4904 4905 4906 4907
			if (dev->phy.rev >= 7) {
				target.ipa[i] = (table[index[i]] >> 16) & 0x7;
				target.pad[i] = (table[index[i]] >> 19) & 0x1F;
				target.pga[i] = (table[index[i]] >> 24) & 0xF;
				target.txgm[i] = (table[index[i]] >> 28) & 0x7;
				target.tx_lpf[i] = (table[index[i]] >> 31) & 0x1;
			} else if (dev->phy.rev >= 3) {
4908 4909 4910 4911 4912 4913 4914 4915 4916 4917 4918 4919 4920 4921 4922 4923
				target.ipa[i] = (table[index[i]] >> 16) & 0xF;
				target.pad[i] = (table[index[i]] >> 20) & 0xF;
				target.pga[i] = (table[index[i]] >> 24) & 0xF;
				target.txgm[i] = (table[index[i]] >> 28) & 0xF;
			} else {
				target.ipa[i] = (table[index[i]] >> 16) & 0x3;
				target.pad[i] = (table[index[i]] >> 18) & 0x3;
				target.pga[i] = (table[index[i]] >> 20) & 0x7;
				target.txgm[i] = (table[index[i]] >> 23) & 0x7;
			}
		}
	}

	return target;
}

4924 4925 4926 4927 4928 4929 4930 4931 4932 4933 4934
/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhyCleanup */
static void b43_nphy_tx_cal_phy_cleanup(struct b43_wldev *dev)
{
	u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;

	if (dev->phy.rev >= 3) {
		b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[0]);
		b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
		b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
		b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[3]);
		b43_phy_write(dev, B43_NPHY_BBCFG, regs[4]);
4935 4936
		b43_ntab_write(dev, B43_NTAB16(8, 3), regs[5]);
		b43_ntab_write(dev, B43_NTAB16(8, 19), regs[6]);
4937 4938 4939 4940 4941 4942 4943 4944 4945
		b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[7]);
		b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[8]);
		b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
		b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
		b43_nphy_reset_cca(dev);
	} else {
		b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, regs[0]);
		b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, regs[1]);
		b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
4946 4947
		b43_ntab_write(dev, B43_NTAB16(8, 2), regs[3]);
		b43_ntab_write(dev, B43_NTAB16(8, 18), regs[4]);
4948 4949 4950 4951 4952 4953 4954 4955
		b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[5]);
		b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[6]);
	}
}

/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhySetup */
static void b43_nphy_tx_cal_phy_setup(struct b43_wldev *dev)
{
4956
	struct b43_phy *phy = &dev->phy;
4957
	struct b43_phy_n *nphy = dev->phy.n;
4958 4959 4960 4961 4962 4963 4964 4965 4966 4967 4968 4969 4970 4971 4972 4973 4974 4975
	u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
	u16 tmp;

	regs[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
	regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
	if (dev->phy.rev >= 3) {
		b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0xF0FF, 0x0A00);
		b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0xF0FF, 0x0A00);

		tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
		regs[2] = tmp;
		b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, tmp | 0x0600);

		tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
		regs[3] = tmp;
		b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x0600);

		regs[4] = b43_phy_read(dev, B43_NPHY_BBCFG);
4976 4977
		b43_phy_mask(dev, B43_NPHY_BBCFG,
			     ~B43_NPHY_BBCFG_RSTRX & 0xFFFF);
4978

4979
		tmp = b43_ntab_read(dev, B43_NTAB16(8, 3));
4980
		regs[5] = tmp;
4981
		b43_ntab_write(dev, B43_NTAB16(8, 3), 0);
4982 4983

		tmp = b43_ntab_read(dev, B43_NTAB16(8, 19));
4984
		regs[6] = tmp;
4985
		b43_ntab_write(dev, B43_NTAB16(8, 19), 0);
4986 4987 4988
		regs[7] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
		regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);

4989 4990 4991 4992 4993 4994
		if (!nphy->use_int_tx_iq_lo_cal)
			b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_PA,
						      1, 3);
		else
			b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_PA,
						      0, 3);
4995 4996
		b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, 2, 1);
		b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, 8, 2);
4997 4998 4999 5000 5001

		regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
		regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
		b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
		b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
5002

5003
		tmp = b43_nphy_read_lpf_ctl(dev, 0);
5004
		if (phy->rev >= 19)
5005 5006
			b43_nphy_rf_ctl_override_rev19(dev, 0x80, tmp, 0, false,
						       1);
5007
		else if (phy->rev >= 7)
5008 5009
			b43_nphy_rf_ctl_override_rev7(dev, 0x80, tmp, 0, false,
						      1);
5010

5011
		if (nphy->use_int_tx_iq_lo_cal && true /* FIXME */) {
5012
			if (phy->rev >= 19) {
5013 5014
				b43_nphy_rf_ctl_override_rev19(dev, 0x8, 0, 0x3,
							       false, 0);
5015
			} else if (phy->rev >= 8) {
5016 5017
				b43_nphy_rf_ctl_override_rev7(dev, 0x8, 0, 0x3,
							      false, 0);
5018
			} else if (phy->rev == 7) {
5019 5020 5021 5022 5023 5024 5025 5026
				b43_radio_maskset(dev, R2057_OVR_REG0, 1 << 4, 1 << 4);
				if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
					b43_radio_maskset(dev, R2057_PAD2G_TUNE_PUS_CORE0, ~1, 0);
					b43_radio_maskset(dev, R2057_PAD2G_TUNE_PUS_CORE1, ~1, 0);
				} else {
					b43_radio_maskset(dev, R2057_IPA5G_CASCOFFV_PU_CORE0, ~1, 0);
					b43_radio_maskset(dev, R2057_IPA5G_CASCOFFV_PU_CORE1, ~1, 0);
				}
5027 5028
			}
		}
5029 5030 5031 5032 5033 5034
	} else {
		b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, 0xA000);
		b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, 0xA000);
		tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
		regs[2] = tmp;
		b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x3000);
5035
		tmp = b43_ntab_read(dev, B43_NTAB16(8, 2));
5036 5037
		regs[3] = tmp;
		tmp |= 0x2000;
5038
		b43_ntab_write(dev, B43_NTAB16(8, 2), tmp);
5039
		tmp = b43_ntab_read(dev, B43_NTAB16(8, 18));
5040 5041
		regs[4] = tmp;
		tmp |= 0x2000;
5042
		b43_ntab_write(dev, B43_NTAB16(8, 18), tmp);
5043 5044 5045 5046 5047 5048 5049 5050 5051 5052 5053
		regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
		regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
		if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
			tmp = 0x0180;
		else
			tmp = 0x0120;
		b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
		b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
	}
}

5054 5055 5056
/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SaveCal */
static void b43_nphy_save_cal(struct b43_wldev *dev)
{
5057
	struct b43_phy *phy = &dev->phy;
5058 5059 5060 5061
	struct b43_phy_n *nphy = dev->phy.n;

	struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
	u16 *txcal_radio_regs = NULL;
5062
	struct b43_chanspec *iqcal_chanspec;
5063 5064 5065 5066 5067 5068 5069 5070 5071 5072 5073 5074 5075 5076 5077 5078 5079 5080 5081
	u16 *table = NULL;

	if (nphy->hang_avoid)
		b43_nphy_stay_in_carrier_search(dev, 1);

	if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
		rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
		txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
		iqcal_chanspec = &nphy->iqcal_chanspec_2G;
		table = nphy->cal_cache.txcal_coeffs_2G;
	} else {
		rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
		txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
		iqcal_chanspec = &nphy->iqcal_chanspec_5G;
		table = nphy->cal_cache.txcal_coeffs_5G;
	}

	b43_nphy_rx_iq_coeffs(dev, false, rxcal_coeffs);
	/* TODO use some definitions */
5082 5083 5084
	if (phy->rev >= 19) {
		/* TODO */
	} else if (phy->rev >= 7) {
5085 5086 5087 5088 5089 5090 5091 5092 5093 5094 5095 5096 5097 5098 5099 5100
		txcal_radio_regs[0] = b43_radio_read(dev,
						     R2057_TX0_LOFT_FINE_I);
		txcal_radio_regs[1] = b43_radio_read(dev,
						     R2057_TX0_LOFT_FINE_Q);
		txcal_radio_regs[4] = b43_radio_read(dev,
						     R2057_TX0_LOFT_COARSE_I);
		txcal_radio_regs[5] = b43_radio_read(dev,
						     R2057_TX0_LOFT_COARSE_Q);
		txcal_radio_regs[2] = b43_radio_read(dev,
						     R2057_TX1_LOFT_FINE_I);
		txcal_radio_regs[3] = b43_radio_read(dev,
						     R2057_TX1_LOFT_FINE_Q);
		txcal_radio_regs[6] = b43_radio_read(dev,
						     R2057_TX1_LOFT_COARSE_I);
		txcal_radio_regs[7] = b43_radio_read(dev,
						     R2057_TX1_LOFT_COARSE_Q);
5101
	} else if (phy->rev >= 3) {
5102 5103 5104 5105 5106 5107 5108 5109 5110 5111 5112 5113 5114 5115
		txcal_radio_regs[0] = b43_radio_read(dev, 0x2021);
		txcal_radio_regs[1] = b43_radio_read(dev, 0x2022);
		txcal_radio_regs[2] = b43_radio_read(dev, 0x3021);
		txcal_radio_regs[3] = b43_radio_read(dev, 0x3022);
		txcal_radio_regs[4] = b43_radio_read(dev, 0x2023);
		txcal_radio_regs[5] = b43_radio_read(dev, 0x2024);
		txcal_radio_regs[6] = b43_radio_read(dev, 0x3023);
		txcal_radio_regs[7] = b43_radio_read(dev, 0x3024);
	} else {
		txcal_radio_regs[0] = b43_radio_read(dev, 0x8B);
		txcal_radio_regs[1] = b43_radio_read(dev, 0xBA);
		txcal_radio_regs[2] = b43_radio_read(dev, 0x8D);
		txcal_radio_regs[3] = b43_radio_read(dev, 0xBC);
	}
5116
	iqcal_chanspec->center_freq = dev->phy.chandef->chan->center_freq;
5117 5118
	iqcal_chanspec->channel_type =
				cfg80211_get_chandef_type(dev->phy.chandef);
5119
	b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 8, table);
5120 5121 5122 5123 5124

	if (nphy->hang_avoid)
		b43_nphy_stay_in_carrier_search(dev, 0);
}

5125 5126 5127
/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreCal */
static void b43_nphy_restore_cal(struct b43_wldev *dev)
{
5128
	struct b43_phy *phy = &dev->phy;
5129 5130 5131 5132 5133 5134 5135 5136 5137 5138 5139
	struct b43_phy_n *nphy = dev->phy.n;

	u16 coef[4];
	u16 *loft = NULL;
	u16 *table = NULL;

	int i;
	u16 *txcal_radio_regs = NULL;
	struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;

	if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
5140
		if (!nphy->iqcal_chanspec_2G.center_freq)
5141 5142 5143 5144
			return;
		table = nphy->cal_cache.txcal_coeffs_2G;
		loft = &nphy->cal_cache.txcal_coeffs_2G[5];
	} else {
5145
		if (!nphy->iqcal_chanspec_5G.center_freq)
5146 5147 5148 5149 5150
			return;
		table = nphy->cal_cache.txcal_coeffs_5G;
		loft = &nphy->cal_cache.txcal_coeffs_5G[5];
	}

5151
	b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4, table);
5152 5153 5154 5155 5156 5157 5158 5159

	for (i = 0; i < 4; i++) {
		if (dev->phy.rev >= 3)
			table[i] = coef[i];
		else
			coef[i] = 0;
	}

5160 5161 5162
	b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4, coef);
	b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2, loft);
	b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2, loft);
5163 5164 5165 5166 5167 5168 5169 5170 5171 5172 5173 5174 5175

	if (dev->phy.rev < 2)
		b43_nphy_tx_iq_workaround(dev);

	if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
		txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
		rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
	} else {
		txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
		rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
	}

	/* TODO use some definitions */
5176 5177 5178
	if (phy->rev >= 19) {
		/* TODO */
	} else if (phy->rev >= 7) {
5179 5180 5181 5182 5183 5184 5185 5186 5187 5188 5189 5190 5191 5192 5193 5194
		b43_radio_write(dev, R2057_TX0_LOFT_FINE_I,
				txcal_radio_regs[0]);
		b43_radio_write(dev, R2057_TX0_LOFT_FINE_Q,
				txcal_radio_regs[1]);
		b43_radio_write(dev, R2057_TX0_LOFT_COARSE_I,
				txcal_radio_regs[4]);
		b43_radio_write(dev, R2057_TX0_LOFT_COARSE_Q,
				txcal_radio_regs[5]);
		b43_radio_write(dev, R2057_TX1_LOFT_FINE_I,
				txcal_radio_regs[2]);
		b43_radio_write(dev, R2057_TX1_LOFT_FINE_Q,
				txcal_radio_regs[3]);
		b43_radio_write(dev, R2057_TX1_LOFT_COARSE_I,
				txcal_radio_regs[6]);
		b43_radio_write(dev, R2057_TX1_LOFT_COARSE_Q,
				txcal_radio_regs[7]);
5195
	} else if (phy->rev >= 3) {
5196 5197 5198 5199 5200 5201 5202 5203 5204 5205 5206 5207 5208 5209 5210 5211 5212
		b43_radio_write(dev, 0x2021, txcal_radio_regs[0]);
		b43_radio_write(dev, 0x2022, txcal_radio_regs[1]);
		b43_radio_write(dev, 0x3021, txcal_radio_regs[2]);
		b43_radio_write(dev, 0x3022, txcal_radio_regs[3]);
		b43_radio_write(dev, 0x2023, txcal_radio_regs[4]);
		b43_radio_write(dev, 0x2024, txcal_radio_regs[5]);
		b43_radio_write(dev, 0x3023, txcal_radio_regs[6]);
		b43_radio_write(dev, 0x3024, txcal_radio_regs[7]);
	} else {
		b43_radio_write(dev, 0x8B, txcal_radio_regs[0]);
		b43_radio_write(dev, 0xBA, txcal_radio_regs[1]);
		b43_radio_write(dev, 0x8D, txcal_radio_regs[2]);
		b43_radio_write(dev, 0xBC, txcal_radio_regs[3]);
	}
	b43_nphy_rx_iq_coeffs(dev, true, rxcal_coeffs);
}

5213 5214 5215 5216 5217
/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalTxIqlo */
static int b43_nphy_cal_tx_iq_lo(struct b43_wldev *dev,
				struct nphy_txgains target,
				bool full, bool mphase)
{
5218
	struct b43_phy *phy = &dev->phy;
5219 5220 5221 5222 5223 5224
	struct b43_phy_n *nphy = dev->phy.n;
	int i;
	int error = 0;
	int freq;
	bool avoid = false;
	u8 length;
5225
	u16 tmp, core, type, count, max, numb, last = 0, cmd;
5226 5227 5228 5229 5230 5231 5232 5233 5234 5235 5236 5237 5238 5239
	const u16 *table;
	bool phy6or5x;

	u16 buffer[11];
	u16 diq_start = 0;
	u16 save[2];
	u16 gain[2];
	struct nphy_iqcal_params params[2];
	bool updated[2] = { };

	b43_nphy_stay_in_carrier_search(dev, true);

	if (dev->phy.rev >= 4) {
		avoid = nphy->hang_avoid;
5240
		nphy->hang_avoid = false;
5241 5242
	}

5243
	b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
5244 5245 5246 5247 5248

	for (i = 0; i < 2; i++) {
		b43_nphy_iq_cal_gain_params(dev, i, target, &params[i]);
		gain[i] = params[i].cal_gain;
	}
5249 5250

	b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain);
5251 5252

	b43_nphy_tx_cal_radio_setup(dev);
5253
	b43_nphy_tx_cal_phy_setup(dev);
5254 5255 5256 5257 5258

	phy6or5x = dev->phy.rev >= 6 ||
		(dev->phy.rev == 5 && nphy->ipa2g_on &&
		b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ);
	if (phy6or5x) {
5259
		if (b43_is_40mhz(dev)) {
5260 5261 5262 5263 5264 5265 5266 5267 5268 5269
			b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
					tbl_tx_iqlo_cal_loft_ladder_40);
			b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
					tbl_tx_iqlo_cal_iqimb_ladder_40);
		} else {
			b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
					tbl_tx_iqlo_cal_loft_ladder_20);
			b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
					tbl_tx_iqlo_cal_iqimb_ladder_20);
		}
5270 5271
	}

5272 5273 5274
	if (phy->rev >= 19) {
		/* TODO */
	} else if (phy->rev >= 7) {
5275
		b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8AD9);
5276 5277 5278
	} else {
		b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8AA9);
	}
5279

5280
	if (!b43_is_40mhz(dev))
5281 5282 5283 5284 5285
		freq = 2500;
	else
		freq = 5000;

	if (nphy->mphase_cal_phase_id > 2)
5286
		b43_nphy_run_samples(dev, (b43_is_40mhz(dev) ? 40 : 20) * 8,
5287
				     0xFFFF, 0, true, false, false);
5288
	else
5289
		error = b43_nphy_tx_tone(dev, freq, 250, true, false, false);
5290 5291 5292 5293 5294 5295 5296 5297 5298 5299 5300 5301 5302 5303 5304 5305 5306 5307 5308 5309 5310 5311 5312 5313 5314

	if (error == 0) {
		if (nphy->mphase_cal_phase_id > 2) {
			table = nphy->mphase_txcal_bestcoeffs;
			length = 11;
			if (dev->phy.rev < 3)
				length -= 2;
		} else {
			if (!full && nphy->txiqlocal_coeffsvalid) {
				table = nphy->txiqlocal_bestc;
				length = 11;
				if (dev->phy.rev < 3)
					length -= 2;
			} else {
				full = true;
				if (dev->phy.rev >= 3) {
					table = tbl_tx_iqlo_cal_startcoefs_nphyrev3;
					length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS_REV3;
				} else {
					table = tbl_tx_iqlo_cal_startcoefs;
					length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS;
				}
			}
		}

5315
		b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length, table);
5316 5317 5318 5319 5320 5321 5322 5323 5324 5325 5326 5327 5328 5329 5330 5331 5332 5333 5334 5335 5336 5337 5338 5339 5340 5341 5342 5343 5344 5345 5346 5347 5348 5349 5350 5351 5352 5353 5354 5355

		if (full) {
			if (dev->phy.rev >= 3)
				max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL_REV3;
			else
				max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL;
		} else {
			if (dev->phy.rev >= 3)
				max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL_REV3;
			else
				max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL;
		}

		if (mphase) {
			count = nphy->mphase_txcal_cmdidx;
			numb = min(max,
				(u16)(count + nphy->mphase_txcal_numcmds));
		} else {
			count = 0;
			numb = max;
		}

		for (; count < numb; count++) {
			if (full) {
				if (dev->phy.rev >= 3)
					cmd = tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[count];
				else
					cmd = tbl_tx_iqlo_cal_cmds_fullcal[count];
			} else {
				if (dev->phy.rev >= 3)
					cmd = tbl_tx_iqlo_cal_cmds_recal_nphyrev3[count];
				else
					cmd = tbl_tx_iqlo_cal_cmds_recal[count];
			}

			core = (cmd & 0x3000) >> 12;
			type = (cmd & 0x0F00) >> 8;

			if (phy6or5x && updated[core] == 0) {
				b43_nphy_update_tx_cal_ladder(dev, core);
5356
				updated[core] = true;
5357 5358 5359 5360 5361 5362
			}

			tmp = (params[core].ncorr[type] << 8) | 0x66;
			b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDNNUM, tmp);

			if (type == 1 || type == 3 || type == 4) {
5363 5364
				buffer[0] = b43_ntab_read(dev,
						B43_NTAB16(15, 69 + core));
5365 5366
				diq_start = buffer[0];
				buffer[0] = 0;
5367 5368
				b43_ntab_write(dev, B43_NTAB16(15, 69 + core),
						0);
5369 5370 5371 5372 5373 5374 5375 5376 5377 5378
			}

			b43_phy_write(dev, B43_NPHY_IQLOCAL_CMD, cmd);
			for (i = 0; i < 2000; i++) {
				tmp = b43_phy_read(dev, B43_NPHY_IQLOCAL_CMD);
				if (tmp & 0xC000)
					break;
				udelay(10);
			}

5379 5380
			b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
						buffer);
5381 5382
			b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length,
						buffer);
5383 5384 5385 5386 5387 5388 5389 5390 5391 5392 5393

			if (type == 1 || type == 3 || type == 4)
				buffer[0] = diq_start;
		}

		if (mphase)
			nphy->mphase_txcal_cmdidx = (numb >= max) ? 0 : numb;

		last = (dev->phy.rev < 3) ? 6 : 7;

		if (!mphase || nphy->mphase_cal_phase_id == last) {
5394
			b43_ntab_write_bulk(dev, B43_NTAB16(15, 96), 4, buffer);
5395
			b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 4, buffer);
5396 5397 5398 5399 5400 5401
			if (dev->phy.rev < 3) {
				buffer[0] = 0;
				buffer[1] = 0;
				buffer[2] = 0;
				buffer[3] = 0;
			}
5402 5403
			b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
						buffer);
5404
			b43_ntab_read_bulk(dev, B43_NTAB16(15, 101), 2,
5405 5406 5407 5408 5409
						buffer);
			b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
						buffer);
			b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
						buffer);
5410 5411 5412
			length = 11;
			if (dev->phy.rev < 3)
				length -= 2;
5413 5414
			b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
						nphy->txiqlocal_bestc);
5415
			nphy->txiqlocal_coeffsvalid = true;
5416
			nphy->txiqlocal_chanspec.center_freq =
5417
						phy->chandef->chan->center_freq;
5418
			nphy->txiqlocal_chanspec.channel_type =
5419
					cfg80211_get_chandef_type(phy->chandef);
5420 5421 5422 5423
		} else {
			length = 11;
			if (dev->phy.rev < 3)
				length -= 2;
5424 5425
			b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
						nphy->mphase_txcal_bestcoeffs);
5426 5427
		}

5428
		b43_nphy_stop_playback(dev);
5429 5430 5431
		b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0);
	}

5432
	b43_nphy_tx_cal_phy_cleanup(dev);
5433
	b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
5434 5435 5436 5437 5438 5439 5440 5441 5442 5443 5444 5445

	if (dev->phy.rev < 2 && (!mphase || nphy->mphase_cal_phase_id == last))
		b43_nphy_tx_iq_workaround(dev);

	if (dev->phy.rev >= 4)
		nphy->hang_avoid = avoid;

	b43_nphy_stay_in_carrier_search(dev, false);

	return error;
}

5446 5447 5448 5449 5450 5451 5452 5453
/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ReapplyTxCalCoeffs */
static void b43_nphy_reapply_tx_cal_coeffs(struct b43_wldev *dev)
{
	struct b43_phy_n *nphy = dev->phy.n;
	u8 i;
	u16 buffer[7];
	bool equal = true;

5454
	if (!nphy->txiqlocal_coeffsvalid ||
5455
	    nphy->txiqlocal_chanspec.center_freq != dev->phy.chandef->chan->center_freq ||
5456
	    nphy->txiqlocal_chanspec.channel_type != cfg80211_get_chandef_type(dev->phy.chandef))
5457 5458 5459 5460 5461 5462 5463 5464 5465 5466 5467 5468 5469 5470 5471 5472 5473 5474 5475 5476 5477 5478 5479 5480
		return;

	b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
	for (i = 0; i < 4; i++) {
		if (buffer[i] != nphy->txiqlocal_bestc[i]) {
			equal = false;
			break;
		}
	}

	if (!equal) {
		b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4,
					nphy->txiqlocal_bestc);
		for (i = 0; i < 4; i++)
			buffer[i] = 0;
		b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
					buffer);
		b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
					&nphy->txiqlocal_bestc[5]);
		b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
					&nphy->txiqlocal_bestc[5]);
	}
}

5481 5482 5483 5484 5485 5486 5487 5488 5489
/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIqRev2 */
static int b43_nphy_rev2_cal_rx_iq(struct b43_wldev *dev,
			struct nphy_txgains target, u8 type, bool debug)
{
	struct b43_phy_n *nphy = dev->phy.n;
	int i, j, index;
	u8 rfctl[2];
	u8 afectl_core;
	u16 tmp[6];
5490
	u16 uninitialized_var(cur_hpf1), uninitialized_var(cur_hpf2), cur_lna;
5491 5492 5493 5494 5495 5496 5497 5498
	u32 real, imag;
	enum ieee80211_band band;

	u8 use;
	u16 cur_hpf;
	u16 lna[3] = { 3, 3, 1 };
	u16 hpf1[3] = { 7, 2, 0 };
	u16 hpf2[3] = { 2, 0, 0 };
5499
	u32 power[3] = { };
5500 5501 5502 5503 5504 5505 5506 5507 5508 5509 5510
	u16 gain_save[2];
	u16 cal_gain[2];
	struct nphy_iqcal_params cal_params[2];
	struct nphy_iq_est est;
	int ret = 0;
	bool playtone = true;
	int desired = 13;

	b43_nphy_stay_in_carrier_search(dev, 1);

	if (dev->phy.rev < 2)
5511
		b43_nphy_reapply_tx_cal_coeffs(dev);
5512
	b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
5513 5514 5515 5516
	for (i = 0; i < 2; i++) {
		b43_nphy_iq_cal_gain_params(dev, i, target, &cal_params[i]);
		cal_gain[i] = cal_params[i].cal_gain;
	}
5517
	b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, cal_gain);
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	for (i = 0; i < 2; i++) {
		if (i == 0) {
			rfctl[0] = B43_NPHY_RFCTL_INTC1;
			rfctl[1] = B43_NPHY_RFCTL_INTC2;
			afectl_core = B43_NPHY_AFECTL_C1;
		} else {
			rfctl[0] = B43_NPHY_RFCTL_INTC2;
			rfctl[1] = B43_NPHY_RFCTL_INTC1;
			afectl_core = B43_NPHY_AFECTL_C2;
		}

		tmp[1] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
		tmp[2] = b43_phy_read(dev, afectl_core);
		tmp[3] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
		tmp[4] = b43_phy_read(dev, rfctl[0]);
		tmp[5] = b43_phy_read(dev, rfctl[1]);

		b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
5537
				~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF,
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				((1 - i) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
		b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
				(1 - i));
		b43_phy_set(dev, afectl_core, 0x0006);
		b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0006);

		band = b43_current_band(dev->wl);

		if (nphy->rxcalparams & 0xFF000000) {
			if (band == IEEE80211_BAND_5GHZ)
				b43_phy_write(dev, rfctl[0], 0x140);
			else
				b43_phy_write(dev, rfctl[0], 0x110);
		} else {
			if (band == IEEE80211_BAND_5GHZ)
				b43_phy_write(dev, rfctl[0], 0x180);
			else
				b43_phy_write(dev, rfctl[0], 0x120);
		}

		if (band == IEEE80211_BAND_5GHZ)
			b43_phy_write(dev, rfctl[1], 0x148);
		else
			b43_phy_write(dev, rfctl[1], 0x114);

		if (nphy->rxcalparams & 0x10000) {
			b43_radio_maskset(dev, B2055_C1_GENSPARE2, 0xFC,
					(i + 1));
			b43_radio_maskset(dev, B2055_C2_GENSPARE2, 0xFC,
					(2 - i));
		}

5570
		for (j = 0; j < 4; j++) {
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			if (j < 3) {
				cur_lna = lna[j];
				cur_hpf1 = hpf1[j];
				cur_hpf2 = hpf2[j];
			} else {
				if (power[1] > 10000) {
					use = 1;
					cur_hpf = cur_hpf1;
					index = 2;
				} else {
					if (power[0] > 10000) {
						use = 1;
						cur_hpf = cur_hpf1;
						index = 1;
					} else {
						index = 0;
						use = 2;
						cur_hpf = cur_hpf2;
					}
				}
				cur_lna = lna[index];
				cur_hpf1 = hpf1[index];
				cur_hpf2 = hpf2[index];
				cur_hpf += desired - hweight32(power[index]);
				cur_hpf = clamp_val(cur_hpf, 0, 10);
				if (use == 1)
					cur_hpf1 = cur_hpf;
				else
					cur_hpf2 = cur_hpf;
			}

			tmp[0] = ((cur_hpf2 << 8) | (cur_hpf1 << 4) |
					(cur_lna << 2));
5604
			b43_nphy_rf_ctl_override(dev, 0x400, tmp[0], 3,
5605
									false);
5606
			b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
5607
			b43_nphy_stop_playback(dev);
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			if (playtone) {
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				ret = b43_nphy_tx_tone(dev, 4000,
						(nphy->rxcalparams & 0xFFFF),
5612
						false, false, true);
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				playtone = false;
			} else {
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				b43_nphy_run_samples(dev, 160, 0xFFFF, 0, false,
						     false, true);
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			}

			if (ret == 0) {
				if (j < 3) {
					b43_nphy_rx_iq_est(dev, &est, 1024, 32,
									false);
					if (i == 0) {
						real = est.i0_pwr;
						imag = est.q0_pwr;
					} else {
						real = est.i1_pwr;
						imag = est.q1_pwr;
					}
					power[i] = ((real + imag) / 1024) + 1;
				} else {
					b43_nphy_calc_rx_iq_comp(dev, 1 << i);
				}
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				b43_nphy_stop_playback(dev);
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			}

			if (ret != 0)
				break;
		}

		b43_radio_mask(dev, B2055_C1_GENSPARE2, 0xFC);
		b43_radio_mask(dev, B2055_C2_GENSPARE2, 0xFC);
		b43_phy_write(dev, rfctl[1], tmp[5]);
		b43_phy_write(dev, rfctl[0], tmp[4]);
		b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp[3]);
		b43_phy_write(dev, afectl_core, tmp[2]);
		b43_phy_write(dev, B43_NPHY_RFSEQCA, tmp[1]);

		if (ret != 0)
			break;
	}

5653
	b43_nphy_rf_ctl_override(dev, 0x400, 0, 3, true);
5654
	b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
5655
	b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
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	b43_nphy_stay_in_carrier_search(dev, 0);

	return ret;
}

static int b43_nphy_rev3_cal_rx_iq(struct b43_wldev *dev,
			struct nphy_txgains target, u8 type, bool debug)
{
	return -1;
}

/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIq */
static int b43_nphy_cal_rx_iq(struct b43_wldev *dev,
			struct nphy_txgains target, u8 type, bool debug)
{
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	if (dev->phy.rev >= 7)
		type = 0;

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	if (dev->phy.rev >= 3)
		return b43_nphy_rev3_cal_rx_iq(dev, target, type, debug);
	else
		return b43_nphy_rev2_cal_rx_iq(dev, target, type, debug);
}

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/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCoreSetState */
static void b43_nphy_set_rx_core_state(struct b43_wldev *dev, u8 mask)
{
	struct b43_phy *phy = &dev->phy;
	struct b43_phy_n *nphy = phy->n;
5686
	/* u16 buf[16]; it's rev3+ */
5687

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	nphy->phyrxchain = mask;

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	if (0 /* FIXME clk */)
		return;

	b43_mac_suspend(dev);

	if (nphy->hang_avoid)
		b43_nphy_stay_in_carrier_search(dev, true);

	b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
			(mask & 0x3) << B43_NPHY_RFSEQCA_RXEN_SHIFT);

5701
	if ((mask & 0x3) != 0x3) {
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		b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 1);
		if (dev->phy.rev >= 3) {
			/* TODO */
		}
	} else {
		b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 0x1E);
		if (dev->phy.rev >= 3) {
			/* TODO */
		}
	}

	b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);

	if (nphy->hang_avoid)
		b43_nphy_stay_in_carrier_search(dev, false);

	b43_mac_enable(dev);
}

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/**************************************************
 * N-PHY init
 **************************************************/

/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MIMOConfig */
static void b43_nphy_update_mimo_config(struct b43_wldev *dev, s32 preamble)
{
	u16 mimocfg = b43_phy_read(dev, B43_NPHY_MIMOCFG);

	mimocfg |= B43_NPHY_MIMOCFG_AUTO;
	if (preamble == 1)
		mimocfg |= B43_NPHY_MIMOCFG_GFMIX;
	else
		mimocfg &= ~B43_NPHY_MIMOCFG_GFMIX;

	b43_phy_write(dev, B43_NPHY_MIMOCFG, mimocfg);
}

/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BPHYInit */
static void b43_nphy_bphy_init(struct b43_wldev *dev)
{
	unsigned int i;
	u16 val;

	val = 0x1E1F;
	for (i = 0; i < 16; i++) {
		b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val);
		val -= 0x202;
	}
	val = 0x3E3F;
	for (i = 0; i < 16; i++) {
		b43_phy_write(dev, B43_PHY_N_BMODE(0x98 + i), val);
		val -= 0x202;
	}
	b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
}

/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SuperSwitchInit */
static void b43_nphy_superswitch_init(struct b43_wldev *dev, bool init)
{
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	if (dev->phy.rev >= 7)
		return;

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	if (dev->phy.rev >= 3) {
		if (!init)
			return;
		if (0 /* FIXME */) {
			b43_ntab_write(dev, B43_NTAB16(9, 2), 0x211);
			b43_ntab_write(dev, B43_NTAB16(9, 3), 0x222);
			b43_ntab_write(dev, B43_NTAB16(9, 8), 0x144);
			b43_ntab_write(dev, B43_NTAB16(9, 12), 0x188);
		}
	} else {
		b43_phy_write(dev, B43_NPHY_GPIO_LOOEN, 0);
		b43_phy_write(dev, B43_NPHY_GPIO_HIOEN, 0);

		switch (dev->dev->bus_type) {
#ifdef CONFIG_B43_BCMA
		case B43_BUS_BCMA:
			bcma_chipco_gpio_control(&dev->dev->bdev->bus->drv_cc,
						 0xFC00, 0xFC00);
			break;
#endif
#ifdef CONFIG_B43_SSB
		case B43_BUS_SSB:
			ssb_chipco_gpio_control(&dev->dev->sdev->bus->chipco,
						0xFC00, 0xFC00);
			break;
#endif
		}

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		b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_GPOUTSMSK, 0);
		b43_maskset16(dev, B43_MMIO_GPIO_MASK, ~0, 0xFC00);
		b43_maskset16(dev, B43_MMIO_GPIO_CONTROL, (~0xFC00 & 0xFFFF),
			      0);
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		if (init) {
			b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
			b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
			b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
			b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
		}
	}
}

/* http://bcm-v4.sipsolutions.net/802.11/PHY/Init/N */
5807
static int b43_phy_initn(struct b43_wldev *dev)
5808
{
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5809
	struct ssb_sprom *sprom = dev->dev->bus_sprom;
5810
	struct b43_phy *phy = &dev->phy;
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	struct b43_phy_n *nphy = phy->n;
	u8 tx_pwr_state;
	struct nphy_txgains target;
5814
	u16 tmp;
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	enum ieee80211_band tmp2;
	bool do_rssi_cal;

	u16 clip[2];
	bool do_cal = false;
5820

5821
	if ((dev->phy.rev >= 3) &&
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5822
	   (sprom->boardflags_lo & B43_BFL_EXTLNA) &&
5823
	   (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)) {
5824
		switch (dev->dev->bus_type) {
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#ifdef CONFIG_B43_BCMA
		case B43_BUS_BCMA:
			bcma_cc_set32(&dev->dev->bdev->bus->drv_cc,
				      BCMA_CC_CHIPCTL, 0x40);
			break;
#endif
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#ifdef CONFIG_B43_SSB
		case B43_BUS_SSB:
			chipco_set32(&dev->dev->sdev->bus->chipco,
				     SSB_CHIPCO_CHIPCTL, 0x40);
			break;
#endif
		}
5838
	}
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	nphy->use_int_tx_iq_lo_cal = b43_nphy_ipa(dev) ||
		phy->rev >= 7 ||
		(phy->rev >= 5 &&
		 sprom->boardflags2_hi & B43_BFH2_INTERNDET_TXIQCAL);
5843
	nphy->deaf_count = 0;
5844
	b43_nphy_tables_init(dev);
5845 5846
	nphy->crsminpwr_adjusted = false;
	nphy->noisevars_adjusted = false;
5847 5848

	/* Clear all overrides */
5849 5850 5851
	if (dev->phy.rev >= 3) {
		b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, 0);
		b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
5852
		if (phy->rev >= 7) {
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			b43_phy_write(dev, B43_NPHY_REV7_RF_CTL_OVER3, 0);
			b43_phy_write(dev, B43_NPHY_REV7_RF_CTL_OVER4, 0);
			b43_phy_write(dev, B43_NPHY_REV7_RF_CTL_OVER5, 0);
			b43_phy_write(dev, B43_NPHY_REV7_RF_CTL_OVER6, 0);
5857 5858 5859 5860 5861
		}
		if (phy->rev >= 19) {
			/* TODO */
		}

5862 5863 5864 5865 5866
		b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, 0);
		b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, 0);
	} else {
		b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
	}
5867 5868
	b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 0);
	b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 0);
5869 5870 5871 5872
	if (dev->phy.rev < 6) {
		b43_phy_write(dev, B43_NPHY_RFCTL_INTC3, 0);
		b43_phy_write(dev, B43_NPHY_RFCTL_INTC4, 0);
	}
5873 5874 5875
	b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
		     ~(B43_NPHY_RFSEQMODE_CAOVER |
		       B43_NPHY_RFSEQMODE_TROVER));
5876 5877
	if (dev->phy.rev >= 3)
		b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, 0);
5878 5879
	b43_phy_write(dev, B43_NPHY_AFECTL_OVER, 0);

5880 5881 5882 5883 5884 5885
	if (dev->phy.rev <= 2) {
		tmp = (dev->phy.rev == 2) ? 0x3B : 0x40;
		b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
				~B43_NPHY_BPHY_CTL3_SCALE,
				tmp << B43_NPHY_BPHY_CTL3_SCALE_SHIFT);
	}
5886 5887 5888
	b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20);
	b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20);

5889
	if (sprom->boardflags2_lo & B43_BFL2_SKWRKFEM_BRD ||
5890
	    (dev->dev->board_vendor == PCI_VENDOR_ID_APPLE &&
5891
	     dev->dev->board_type == BCMA_BOARD_TYPE_BCM943224M93))
5892 5893 5894 5895 5896 5897
		b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0);
	else
		b43_phy_write(dev, B43_NPHY_TXREALFD, 0xB8);
	b43_phy_write(dev, B43_NPHY_MIMO_CRSTXEXT, 0xC8);
	b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x50);
	b43_phy_write(dev, B43_NPHY_TXRIFS_FRDEL, 0x30);
5898

5899 5900 5901
	if (phy->rev < 8)
		b43_nphy_update_mimo_config(dev, nphy->preamble_override);

5902
	b43_nphy_update_txrx_chain(dev);
5903 5904 5905 5906 5907

	if (phy->rev < 2) {
		b43_phy_write(dev, B43_NPHY_DUP40_GFBL, 0xAA8);
		b43_phy_write(dev, B43_NPHY_DUP40_BL, 0x9A4);
	}
5908 5909

	tmp2 = b43_current_band(dev->wl);
5910
	if (b43_nphy_ipa(dev)) {
5911 5912 5913 5914 5915 5916
		b43_phy_set(dev, B43_NPHY_PAPD_EN0, 0x1);
		b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ0, 0x007F,
				nphy->papd_epsilon_offset[0] << 7);
		b43_phy_set(dev, B43_NPHY_PAPD_EN1, 0x1);
		b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ1, 0x007F,
				nphy->papd_epsilon_offset[1] << 7);
5917
		b43_nphy_int_pa_set_tx_dig_filters(dev);
5918
	} else if (phy->rev >= 5) {
5919
		b43_nphy_ext_pa_set_tx_dig_filters(dev);
5920 5921
	}

5922 5923
	b43_nphy_workarounds(dev);

5924
	/* Reset CCA, in init code it differs a little from standard way */
5925
	b43_phy_force_clock(dev, 1);
5926 5927 5928
	tmp = b43_phy_read(dev, B43_NPHY_BBCFG);
	b43_phy_write(dev, B43_NPHY_BBCFG, tmp | B43_NPHY_BBCFG_RSTCCA);
	b43_phy_write(dev, B43_NPHY_BBCFG, tmp & ~B43_NPHY_BBCFG_RSTCCA);
5929
	b43_phy_force_clock(dev, 0);
5930

5931
	b43_mac_phy_clock_set(dev, true);
5932

5933 5934 5935 5936 5937 5938
	if (phy->rev < 7) {
		b43_nphy_pa_override(dev, false);
		b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
		b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
		b43_nphy_pa_override(dev, true);
	}
5939

5940 5941
	b43_nphy_classifier(dev, 0, 0);
	b43_nphy_read_clip_detection(dev, clip);
5942 5943 5944
	if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
		b43_nphy_bphy_init(dev);

5945
	tx_pwr_state = nphy->txpwrctrl;
5946 5947
	b43_nphy_tx_power_ctrl(dev, false);
	b43_nphy_tx_power_fix(dev);
5948
	b43_nphy_tx_power_ctl_idle_tssi(dev);
5949
	b43_nphy_tx_power_ctl_setup(dev);
5950
	b43_nphy_tx_gain_table_upload(dev);
5951

5952
	if (nphy->phyrxchain != 3)
5953
		b43_nphy_set_rx_core_state(dev, nphy->phyrxchain);
5954 5955 5956 5957 5958 5959
	if (nphy->mphase_cal_phase_id > 0)
		;/* TODO PHY Periodic Calibration Multi-Phase Restart */

	do_rssi_cal = false;
	if (phy->rev >= 3) {
		if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
5960
			do_rssi_cal = !nphy->rssical_chanspec_2G.center_freq;
5961
		else
5962
			do_rssi_cal = !nphy->rssical_chanspec_5G.center_freq;
5963 5964

		if (do_rssi_cal)
5965
			b43_nphy_rssi_cal(dev);
5966
		else
5967
			b43_nphy_restore_rssi_cal(dev);
5968
	} else {
5969
		b43_nphy_rssi_cal(dev);
5970 5971 5972 5973
	}

	if (!((nphy->measure_hold & 0x6) != 0)) {
		if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
5974
			do_cal = !nphy->iqcal_chanspec_2G.center_freq;
5975
		else
5976
			do_cal = !nphy->iqcal_chanspec_5G.center_freq;
5977 5978 5979 5980 5981

		if (nphy->mute)
			do_cal = false;

		if (do_cal) {
5982
			target = b43_nphy_get_tx_gains(dev);
5983 5984

			if (nphy->antsel_type == 2)
5985
				b43_nphy_superswitch_init(dev, true);
5986
			if (nphy->perical != 2) {
5987
				b43_nphy_rssi_cal(dev);
5988 5989 5990 5991 5992 5993
				if (phy->rev >= 3) {
					nphy->cal_orig_pwr_idx[0] =
					    nphy->txpwrindex[0].index_internal;
					nphy->cal_orig_pwr_idx[1] =
					    nphy->txpwrindex[1].index_internal;
					/* TODO N PHY Pre Calibrate TX Gain */
5994
					target = b43_nphy_get_tx_gains(dev);
5995
				}
5996 5997 5998 5999 6000 6001 6002
				if (!b43_nphy_cal_tx_iq_lo(dev, target, true, false))
					if (b43_nphy_cal_rx_iq(dev, target, 2, 0) == 0)
						b43_nphy_save_cal(dev);
			} else if (nphy->mphase_cal_phase_id == 0)
				;/* N PHY Periodic Calibration with arg 3 */
		} else {
			b43_nphy_restore_cal(dev);
6003 6004 6005
		}
	}

6006
	b43_nphy_tx_pwr_ctrl_coef_setup(dev);
6007
	b43_nphy_tx_power_ctrl(dev, tx_pwr_state);
6008 6009 6010
	b43_phy_write(dev, B43_NPHY_TXMACIF_HOLDOFF, 0x0015);
	b43_phy_write(dev, B43_NPHY_TXMACDELAY, 0x0320);
	if (phy->rev >= 3 && phy->rev <= 6)
6011
		b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x0032);
6012
	b43_nphy_tx_lpf_bw(dev);
6013 6014
	if (phy->rev >= 3)
		b43_nphy_spur_workaround(dev);
6015

6016
	return 0;
6017
}
6018

6019 6020 6021 6022 6023 6024 6025 6026 6027 6028 6029 6030 6031 6032 6033
/**************************************************
 * Channel switching ops.
 **************************************************/

static void b43_chantab_phy_upload(struct b43_wldev *dev,
				   const struct b43_phy_n_sfo_cfg *e)
{
	b43_phy_write(dev, B43_NPHY_BW1A, e->phy_bw1a);
	b43_phy_write(dev, B43_NPHY_BW2, e->phy_bw2);
	b43_phy_write(dev, B43_NPHY_BW3, e->phy_bw3);
	b43_phy_write(dev, B43_NPHY_BW4, e->phy_bw4);
	b43_phy_write(dev, B43_NPHY_BW5, e->phy_bw5);
	b43_phy_write(dev, B43_NPHY_BW6, e->phy_bw6);
}

6034 6035 6036
/* http://bcm-v4.sipsolutions.net/802.11/PmuSpurAvoid */
static void b43_nphy_pmu_spur_avoid(struct b43_wldev *dev, bool avoid)
{
6037 6038 6039
	switch (dev->dev->bus_type) {
#ifdef CONFIG_B43_BCMA
	case B43_BUS_BCMA:
6040 6041
		bcma_pmu_spuravoid_pllupdate(&dev->dev->bdev->bus->drv_cc,
					     avoid);
6042
		break;
6043
#endif
6044 6045
#ifdef CONFIG_B43_SSB
	case B43_BUS_SSB:
6046 6047
		ssb_pmu_spuravoid_pllupdate(&dev->dev->sdev->bus->chipco,
					    avoid);
6048 6049 6050
		break;
#endif
	}
6051 6052
}

6053
/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ChanspecSetup */
6054
static void b43_nphy_channel_setup(struct b43_wldev *dev,
6055
				const struct b43_phy_n_sfo_cfg *e,
6056
				struct ieee80211_channel *new_channel)
6057 6058 6059
{
	struct b43_phy *phy = &dev->phy;
	struct b43_phy_n *nphy = dev->phy.n;
6060
	int ch = new_channel->hw_value;
6061
	u16 tmp16;
6062

6063
	if (new_channel->band == IEEE80211_BAND_5GHZ) {
6064 6065
		tmp16 = b43_read16(dev, B43_MMIO_PSM_PHY_HDR);
		b43_write16(dev, B43_MMIO_PSM_PHY_HDR, tmp16 | 4);
6066 6067 6068
		/* Put BPHY in the reset */
		b43_phy_set(dev, B43_PHY_B_BBCFG,
			    B43_PHY_B_BBCFG_RSTCCA | B43_PHY_B_BBCFG_RSTRX);
6069
		b43_write16(dev, B43_MMIO_PSM_PHY_HDR, tmp16);
6070
		b43_phy_set(dev, B43_NPHY_BANDCTL, B43_NPHY_BANDCTL_5GHZ);
6071
	} else if (new_channel->band == IEEE80211_BAND_2GHZ) {
6072
		b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ);
6073 6074
		tmp16 = b43_read16(dev, B43_MMIO_PSM_PHY_HDR);
		b43_write16(dev, B43_MMIO_PSM_PHY_HDR, tmp16 | 4);
6075 6076 6077
		/* Take BPHY out of the reset */
		b43_phy_mask(dev, B43_PHY_B_BBCFG,
			     (u16)~(B43_PHY_B_BBCFG_RSTCCA | B43_PHY_B_BBCFG_RSTRX));
6078
		b43_write16(dev, B43_MMIO_PSM_PHY_HDR, tmp16);
6079 6080 6081 6082
	}

	b43_chantab_phy_upload(dev, e);

6083
	if (new_channel->hw_value == 14) {
6084 6085 6086 6087
		b43_nphy_classifier(dev, 2, 0);
		b43_phy_set(dev, B43_PHY_B_TEST, 0x0800);
	} else {
		b43_nphy_classifier(dev, 2, 2);
6088
		if (new_channel->band == IEEE80211_BAND_2GHZ)
6089 6090 6091
			b43_phy_mask(dev, B43_PHY_B_TEST, ~0x840);
	}

6092
	if (!nphy->txpwrctrl)
6093 6094 6095 6096 6097
		b43_nphy_tx_power_fix(dev);

	if (dev->phy.rev < 3)
		b43_nphy_adjust_lna_gain_table(dev);

6098
	b43_nphy_tx_lpf_bw(dev);
6099

6100 6101
	if (dev->phy.rev >= 3 &&
	    dev->phy.n->spur_avoid != B43_SPUR_AVOID_DISABLE) {
6102 6103
		u8 spuravoid = 0;

6104
		if (dev->phy.n->spur_avoid == B43_SPUR_AVOID_FORCE) {
6105 6106 6107 6108 6109 6110 6111 6112 6113 6114 6115 6116 6117 6118 6119 6120 6121 6122 6123 6124 6125 6126 6127 6128 6129 6130
			spuravoid = 1;
		} else if (phy->rev >= 19) {
			/* TODO */
		} else if (phy->rev >= 18) {
			/* TODO */
		} else if (phy->rev >= 17) {
			/* TODO: Off for channels 1-11, but check 12-14! */
		} else if (phy->rev >= 16) {
			/* TODO: Off for 2 GHz, but check 5 GHz! */
		} else if (phy->rev >= 7) {
			if (!b43_is_40mhz(dev)) { /* 20MHz */
				if (ch == 13 || ch == 14 || ch == 153)
					spuravoid = 1;
			} else { /* 40 MHz */
				if (ch == 54)
					spuravoid = 1;
			}
		} else {
			if (!b43_is_40mhz(dev)) { /* 20MHz */
				if ((ch >= 5 && ch <= 8) || ch == 13 || ch == 14)
					spuravoid = 1;
			} else { /* 40MHz */
				if (nphy->aband_spurwar_en &&
				    (ch == 38 || ch == 102 || ch == 118))
					spuravoid = dev->dev->chip_id == 0x4716;
			}
6131 6132
		}

6133
		b43_nphy_pmu_spur_avoid(dev, spuravoid);
6134

6135
		b43_mac_switch_freq(dev, spuravoid);
6136 6137 6138 6139

		if (dev->phy.rev == 3 || dev->phy.rev == 4)
			; /* TODO: reset PLL */

6140
		if (spuravoid)
6141 6142 6143 6144 6145 6146 6147 6148
			b43_phy_set(dev, B43_NPHY_BBCFG, B43_NPHY_BBCFG_RSTRX);
		else
			b43_phy_mask(dev, B43_NPHY_BBCFG,
				     ~B43_NPHY_BBCFG_RSTRX & 0xFFFF);

		b43_nphy_reset_cca(dev);

		/* wl sets useless phy_isspuravoid here */
6149 6150 6151 6152 6153 6154 6155 6156
	}

	b43_phy_write(dev, B43_NPHY_NDATAT_DUP40, 0x3830);

	if (phy->rev >= 3)
		b43_nphy_spur_workaround(dev);
}

6157
/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetChanspec */
6158 6159 6160
static int b43_nphy_set_channel(struct b43_wldev *dev,
				struct ieee80211_channel *channel,
				enum nl80211_channel_type channel_type)
6161
{
6162
	struct b43_phy *phy = &dev->phy;
6163

6164 6165
	const struct b43_nphy_channeltab_entry_rev2 *tabent_r2 = NULL;
	const struct b43_nphy_channeltab_entry_rev3 *tabent_r3 = NULL;
6166 6167
	const struct b43_nphy_chantabent_rev7 *tabent_r7 = NULL;
	const struct b43_nphy_chantabent_rev7_2g *tabent_r7_2g = NULL;
6168 6169 6170

	u8 tmp;

6171 6172 6173 6174
	if (phy->rev >= 19) {
		return -ESRCH;
		/* TODO */
	} else if (phy->rev >= 7) {
6175 6176 6177 6178 6179
		r2057_get_chantabent_rev7(dev, channel->center_freq,
					  &tabent_r7, &tabent_r7_2g);
		if (!tabent_r7 && !tabent_r7_2g)
			return -ESRCH;
	} else if (phy->rev >= 3) {
6180 6181
		tabent_r3 = b43_nphy_get_chantabent_rev3(dev,
							channel->center_freq);
6182 6183
		if (!tabent_r3)
			return -ESRCH;
6184
	} else {
6185 6186
		tabent_r2 = b43_nphy_get_chantabent_rev2(dev,
							channel->hw_value);
6187
		if (!tabent_r2)
6188
			return -ESRCH;
6189 6190
	}

6191 6192 6193
	/* Channel is set later in common code, but we need to set it on our
	   own to let this function's subcalls work properly. */
	phy->channel = channel->hw_value;
6194

6195
#if 0
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	if (b43_channel_type_is_40mhz(phy->channel_type) !=
		b43_channel_type_is_40mhz(channel_type))
		; /* TODO: BMAC BW Set (channel_type) */
6199
#endif
6200

6201 6202 6203 6204 6205 6206 6207 6208 6209
	if (channel_type == NL80211_CHAN_HT40PLUS) {
		b43_phy_set(dev, B43_NPHY_RXCTL, B43_NPHY_RXCTL_BSELU20);
		if (phy->rev >= 7)
			b43_phy_set(dev, 0x310, 0x8000);
	} else if (channel_type == NL80211_CHAN_HT40MINUS) {
		b43_phy_mask(dev, B43_NPHY_RXCTL, ~B43_NPHY_RXCTL_BSELU20);
		if (phy->rev >= 7)
			b43_phy_mask(dev, 0x310, (u16)~0x8000);
	}
6210

6211 6212 6213
	if (phy->rev >= 19) {
		/* TODO */
	} else if (phy->rev >= 7) {
6214 6215 6216 6217 6218 6219 6220 6221 6222 6223 6224 6225
		const struct b43_phy_n_sfo_cfg *phy_regs = tabent_r7 ?
			&(tabent_r7->phy_regs) : &(tabent_r7_2g->phy_regs);

		if (phy->radio_rev <= 4 || phy->radio_rev == 6) {
			tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 2 : 0;
			b43_radio_maskset(dev, R2057_TIA_CONFIG_CORE0, ~2, tmp);
			b43_radio_maskset(dev, R2057_TIA_CONFIG_CORE1, ~2, tmp);
		}

		b43_radio_2057_setup(dev, tabent_r7, tabent_r7_2g);
		b43_nphy_channel_setup(dev, phy_regs, channel);
	} else if (phy->rev >= 3) {
6226
		tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 4 : 0;
6227
		b43_radio_maskset(dev, 0x08, 0xFFFB, tmp);
6228
		b43_radio_2056_setup(dev, tabent_r3);
6229
		b43_nphy_channel_setup(dev, &(tabent_r3->phy_regs), channel);
6230
	} else {
6231
		tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 0x0020 : 0x0050;
6232
		b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, tmp);
6233
		b43_radio_2055_setup(dev, tabent_r2);
6234
		b43_nphy_channel_setup(dev, &(tabent_r2->phy_regs), channel);
6235 6236 6237 6238 6239
	}

	return 0;
}

6240 6241 6242 6243
/**************************************************
 * Basic PHY ops.
 **************************************************/

6244 6245 6246 6247 6248 6249 6250 6251 6252 6253 6254 6255
static int b43_nphy_op_allocate(struct b43_wldev *dev)
{
	struct b43_phy_n *nphy;

	nphy = kzalloc(sizeof(*nphy), GFP_KERNEL);
	if (!nphy)
		return -ENOMEM;
	dev->phy.n = nphy;

	return 0;
}

6256
static void b43_nphy_op_prepare_structs(struct b43_wldev *dev)
6257
{
6258 6259
	struct b43_phy *phy = &dev->phy;
	struct b43_phy_n *nphy = phy->n;
6260
	struct ssb_sprom *sprom = dev->dev->bus_sprom;
6261

6262
	memset(nphy, 0, sizeof(*nphy));
6263

6264
	nphy->hang_avoid = (phy->rev == 3 || phy->rev == 4);
6265 6266
	nphy->spur_avoid = (phy->rev >= 3) ?
				B43_SPUR_AVOID_AUTO : B43_SPUR_AVOID_DISABLE;
6267 6268 6269
	nphy->gain_boost = true; /* this way we follow wl, assume it is true */
	nphy->txrx_chain = 2; /* sth different than 0 and 1 for now */
	nphy->phyrxchain = 3; /* to avoid b43_nphy_set_rx_core_state like wl */
6270
	nphy->perical = 2; /* avoid additional rssi cal on init (like wl) */
6271 6272 6273 6274
	/* 128 can mean disabled-by-default state of TX pwr ctl. Max value is
	 * 0x7f == 127 and we check for 128 when restoring TX pwr ctl. */
	nphy->tx_pwr_idx[0] = 128;
	nphy->tx_pwr_idx[1] = 128;
6275 6276 6277 6278 6279 6280 6281 6282 6283 6284 6285 6286 6287 6288 6289 6290 6291 6292 6293 6294 6295 6296 6297 6298 6299 6300 6301 6302 6303 6304 6305 6306

	/* Hardware TX power control and 5GHz power gain */
	nphy->txpwrctrl = false;
	nphy->pwg_gain_5ghz = false;
	if (dev->phy.rev >= 3 ||
	    (dev->dev->board_vendor == PCI_VENDOR_ID_APPLE &&
	     (dev->dev->core_rev == 11 || dev->dev->core_rev == 12))) {
		nphy->txpwrctrl = true;
		nphy->pwg_gain_5ghz = true;
	} else if (sprom->revision >= 4) {
		if (dev->phy.rev >= 2 &&
		    (sprom->boardflags2_lo & B43_BFL2_TXPWRCTRL_EN)) {
			nphy->txpwrctrl = true;
#ifdef CONFIG_B43_SSB
			if (dev->dev->bus_type == B43_BUS_SSB &&
			    dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI) {
				struct pci_dev *pdev =
					dev->dev->sdev->bus->host_pci;
				if (pdev->device == 0x4328 ||
				    pdev->device == 0x432a)
					nphy->pwg_gain_5ghz = true;
			}
#endif
		} else if (sprom->boardflags2_lo & B43_BFL2_5G_PWRGAIN) {
			nphy->pwg_gain_5ghz = true;
		}
	}

	if (dev->phy.rev >= 3) {
		nphy->ipa2g_on = sprom->fem.ghz2.extpa_gain == 2;
		nphy->ipa5g_on = sprom->fem.ghz5.extpa_gain == 2;
	}
6307 6308
}

6309
static void b43_nphy_op_free(struct b43_wldev *dev)
6310
{
6311 6312
	struct b43_phy *phy = &dev->phy;
	struct b43_phy_n *nphy = phy->n;
6313 6314

	kfree(nphy);
6315 6316 6317 6318 6319 6320
	phy->n = NULL;
}

static int b43_nphy_op_init(struct b43_wldev *dev)
{
	return b43_phy_initn(dev);
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}

static inline void check_phyreg(struct b43_wldev *dev, u16 offset)
{
#if B43_DEBUG
	if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) {
		/* OFDM registers are onnly available on A/G-PHYs */
		b43err(dev->wl, "Invalid OFDM PHY access at "
		       "0x%04X on N-PHY\n", offset);
		dump_stack();
	}
	if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) {
		/* Ext-G registers are only available on G-PHYs */
		b43err(dev->wl, "Invalid EXT-G PHY access at "
		       "0x%04X on N-PHY\n", offset);
		dump_stack();
	}
#endif /* B43_DEBUG */
}

static u16 b43_nphy_op_read(struct b43_wldev *dev, u16 reg)
{
	check_phyreg(dev, reg);
	b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
	return b43_read16(dev, B43_MMIO_PHY_DATA);
}

static void b43_nphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
{
	check_phyreg(dev, reg);
	b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
	b43_write16(dev, B43_MMIO_PHY_DATA, value);
}

6355 6356 6357 6358 6359
static void b43_nphy_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask,
				 u16 set)
{
	check_phyreg(dev, reg);
	b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
Rafał Miłecki's avatar
Rafał Miłecki committed
6360
	b43_maskset16(dev, B43_MMIO_PHY_DATA, mask, set);
6361 6362
}

6363 6364 6365
static u16 b43_nphy_op_radio_read(struct b43_wldev *dev, u16 reg)
{
	/* Register 1 is a 32-bit register. */
6366
	B43_WARN_ON(dev->phy.rev < 7 && reg == 1);
6367 6368 6369 6370 6371

	if (dev->phy.rev >= 7)
		reg |= 0x200; /* Radio 0x2057 */
	else
		reg |= 0x100;
6372 6373 6374 6375 6376 6377 6378 6379

	b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
	return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
}

static void b43_nphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
{
	/* Register 1 is a 32-bit register. */
6380
	B43_WARN_ON(dev->phy.rev < 7 && reg == 1);
6381 6382 6383 6384 6385

	b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
	b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
}

6386
/* http://bcm-v4.sipsolutions.net/802.11/Radio/Switch%20Radio */
6387
static void b43_nphy_op_software_rfkill(struct b43_wldev *dev,
Johannes Berg's avatar
Johannes Berg committed
6388
					bool blocked)
6389
{
6390 6391
	struct b43_phy *phy = &dev->phy;

6392 6393 6394 6395
	if (b43_read32(dev, B43_MMIO_MACCTL) & B43_MACCTL_ENABLED)
		b43err(dev->wl, "MAC not suspended\n");

	if (blocked) {
6396
		if (phy->rev >= 19) {
6397
			/* TODO */
6398 6399 6400
		} else if (phy->rev >= 8) {
			b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
				     ~B43_NPHY_RFCTL_CMD_CHIP0PU);
6401
		} else if (phy->rev >= 7) {
6402
			/* Nothing needed */
6403
		} else if (phy->rev >= 3) {
6404 6405 6406
			b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
				     ~B43_NPHY_RFCTL_CMD_CHIP0PU);

6407 6408 6409 6410 6411 6412 6413 6414 6415 6416 6417 6418 6419 6420 6421 6422 6423
			b43_radio_mask(dev, 0x09, ~0x2);

			b43_radio_write(dev, 0x204D, 0);
			b43_radio_write(dev, 0x2053, 0);
			b43_radio_write(dev, 0x2058, 0);
			b43_radio_write(dev, 0x205E, 0);
			b43_radio_mask(dev, 0x2062, ~0xF0);
			b43_radio_write(dev, 0x2064, 0);

			b43_radio_write(dev, 0x304D, 0);
			b43_radio_write(dev, 0x3053, 0);
			b43_radio_write(dev, 0x3058, 0);
			b43_radio_write(dev, 0x305E, 0);
			b43_radio_mask(dev, 0x3062, ~0xF0);
			b43_radio_write(dev, 0x3064, 0);
		}
	} else {
6424 6425 6426
		if (phy->rev >= 19) {
			/* TODO */
		} else if (phy->rev >= 7) {
6427 6428
			if (!dev->phy.radio_on)
				b43_radio_2057_init(dev);
6429
			b43_switch_channel(dev, dev->phy.channel);
6430
		} else if (phy->rev >= 3) {
6431 6432
			if (!dev->phy.radio_on)
				b43_radio_init2056(dev);
6433
			b43_switch_channel(dev, dev->phy.channel);
6434 6435 6436 6437
		} else {
			b43_radio_init2055(dev);
		}
	}
6438 6439
}

6440
/* http://bcm-v4.sipsolutions.net/802.11/PHY/Anacore */
6441 6442
static void b43_nphy_op_switch_analog(struct b43_wldev *dev, bool on)
{
6443
	struct b43_phy *phy = &dev->phy;
6444 6445
	u16 override = on ? 0x0 : 0x7FFF;
	u16 core = on ? 0xD : 0x00FD;
6446

6447 6448 6449
	if (phy->rev >= 19) {
		/* TODO */
	} else if (phy->rev >= 3) {
6450 6451 6452 6453 6454 6455 6456 6457 6458 6459 6460 6461 6462 6463
		if (on) {
			b43_phy_write(dev, B43_NPHY_AFECTL_C1, core);
			b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, override);
			b43_phy_write(dev, B43_NPHY_AFECTL_C2, core);
			b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
		} else {
			b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, override);
			b43_phy_write(dev, B43_NPHY_AFECTL_C1, core);
			b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
			b43_phy_write(dev, B43_NPHY_AFECTL_C2, core);
		}
	} else {
		b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
	}
6464 6465
}

6466 6467 6468
static int b43_nphy_op_switch_channel(struct b43_wldev *dev,
				      unsigned int new_channel)
{
6469 6470 6471
	struct ieee80211_channel *channel = dev->wl->hw->conf.chandef.chan;
	enum nl80211_channel_type channel_type =
		cfg80211_get_chandef_type(&dev->wl->hw->conf.chandef);
6472

6473 6474 6475 6476 6477 6478 6479 6480
	if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
		if ((new_channel < 1) || (new_channel > 14))
			return -EINVAL;
	} else {
		if (new_channel > 200)
			return -EINVAL;
	}

6481
	return b43_nphy_set_channel(dev, channel, channel_type);
6482 6483 6484 6485 6486 6487 6488 6489 6490 6491 6492
}

static unsigned int b43_nphy_op_get_default_chan(struct b43_wldev *dev)
{
	if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
		return 1;
	return 36;
}

const struct b43_phy_operations b43_phyops_n = {
	.allocate		= b43_nphy_op_allocate,
6493 6494
	.free			= b43_nphy_op_free,
	.prepare_structs	= b43_nphy_op_prepare_structs,
6495 6496 6497
	.init			= b43_nphy_op_init,
	.phy_read		= b43_nphy_op_read,
	.phy_write		= b43_nphy_op_write,
6498
	.phy_maskset		= b43_nphy_op_maskset,
6499 6500 6501
	.radio_read		= b43_nphy_op_radio_read,
	.radio_write		= b43_nphy_op_radio_write,
	.software_rfkill	= b43_nphy_op_software_rfkill,
6502
	.switch_analog		= b43_nphy_op_switch_analog,
6503 6504
	.switch_channel		= b43_nphy_op_switch_channel,
	.get_default_chan	= b43_nphy_op_get_default_chan,
6505 6506
	.recalc_txpower		= b43_nphy_op_recalc_txpower,
	.adjust_txpower		= b43_nphy_op_adjust_txpower,
6507
};