omap-mcbsp.c 21.9 KB
Newer Older
1 2 3 4 5
/*
 * omap-mcbsp.c  --  OMAP ALSA SoC DAI driver using McBSP port
 *
 * Copyright (C) 2008 Nokia Corporation
 *
6
 * Contact: Jarkko Nikula <jarkko.nikula@bitmer.com>
7
 *          Peter Ujfalusi <peter.ujfalusi@ti.com>
8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
 * 02110-1301 USA
 *
 */

#include <linux/init.h>
#include <linux/module.h>
#include <linux/device.h>
28
#include <linux/pm_runtime.h>
29 30
#include <linux/of.h>
#include <linux/of_device.h>
31 32 33 34 35
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/initval.h>
#include <sound/soc.h>
36
#include <sound/dmaengine_pcm.h>
37

38
#include <linux/platform_data/asoc-ti-mcbsp.h>
39
#include "mcbsp.h"
40 41
#include "omap-mcbsp.h"

42
#define OMAP_MCBSP_RATES	(SNDRV_PCM_RATE_8000_96000)
43

44 45 46 47 48 49 50 51
#define OMAP_MCBSP_SOC_SINGLE_S16_EXT(xname, xmin, xmax, \
	xhandler_get, xhandler_put) \
{	.iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
	.info = omap_mcbsp_st_info_volsw, \
	.get = xhandler_get, .put = xhandler_put, \
	.private_value = (unsigned long) &(struct soc_mixer_control) \
	{.min = xmin, .max = xmax} }

52 53 54 55 56 57 58 59 60
enum {
	OMAP_MCBSP_WORD_8 = 0,
	OMAP_MCBSP_WORD_12,
	OMAP_MCBSP_WORD_16,
	OMAP_MCBSP_WORD_20,
	OMAP_MCBSP_WORD_24,
	OMAP_MCBSP_WORD_32,
};

61 62 63 64
/*
 * Stream DMA parameters. DMA request line and port address are set runtime
 * since they are different between OMAP1 and later OMAPs
 */
65 66
static void omap_mcbsp_set_threshold(struct snd_pcm_substream *substream,
		unsigned int packet_size)
67 68
{
	struct snd_soc_pcm_runtime *rtd = substream->private_data;
69
	struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
70
	struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
71
	int words;
72

73 74 75 76 77 78
	/*
	 * Configure McBSP threshold based on either:
	 * packet_size, when the sDMA is in packet mode, or based on the
	 * period size in THRESHOLD mode, otherwise use McBSP threshold = 1
	 * for mono streams.
	 */
79 80
	if (packet_size)
		words = packet_size;
81
	else
82
		words = 1;
83 84 85

	/* Configure McBSP internal buffer usage */
	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
86
		omap_mcbsp_set_tx_threshold(mcbsp, words);
87
	else
88
		omap_mcbsp_set_rx_threshold(mcbsp, words);
89 90
}

91 92 93 94 95 96 97
static int omap_mcbsp_hwrule_min_buffersize(struct snd_pcm_hw_params *params,
				    struct snd_pcm_hw_rule *rule)
{
	struct snd_interval *buffer_size = hw_param_interval(params,
					SNDRV_PCM_HW_PARAM_BUFFER_SIZE);
	struct snd_interval *channels = hw_param_interval(params,
					SNDRV_PCM_HW_PARAM_CHANNELS);
98
	struct omap_mcbsp *mcbsp = rule->private;
99 100 101 102
	struct snd_interval frames;
	int size;

	snd_interval_any(&frames);
103
	size = mcbsp->pdata->buffer_size;
104 105 106 107 108 109

	frames.min = size / channels->min;
	frames.integer = 1;
	return snd_interval_refine(buffer_size, &frames);
}

110
static int omap_mcbsp_dai_startup(struct snd_pcm_substream *substream,
111
				  struct snd_soc_dai *cpu_dai)
112
{
113
	struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
114 115
	int err = 0;

116
	if (!cpu_dai->active)
117
		err = omap_mcbsp_request(mcbsp);
118

119 120 121 122 123 124 125 126 127 128 129 130 131 132 133
	/*
	 * OMAP3 McBSP FIFO is word structured.
	 * McBSP2 has 1024 + 256 = 1280 word long buffer,
	 * McBSP1,3,4,5 has 128 word long buffer
	 * This means that the size of the FIFO depends on the sample format.
	 * For example on McBSP3:
	 * 16bit samples: size is 128 * 2 = 256 bytes
	 * 32bit samples: size is 128 * 4 = 512 bytes
	 * It is simpler to place constraint for buffer and period based on
	 * channels.
	 * McBSP3 as example again (16 or 32 bit samples):
	 * 1 channel (mono): size is 128 frames (128 words)
	 * 2 channels (stereo): size is 128 / 2 = 64 frames (2 * 64 words)
	 * 4 channels: size is 128 / 4 = 32 frames (4 * 32 words)
	 */
134
	if (mcbsp->pdata->buffer_size) {
135
		/*
136
		* Rule for the buffer size. We should not allow
137 138
		* smaller buffer than the FIFO size to avoid underruns.
		* This applies only for the playback stream.
139
		*/
140 141 142 143 144 145
		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
			snd_pcm_hw_rule_add(substream->runtime, 0,
					    SNDRV_PCM_HW_PARAM_BUFFER_SIZE,
					    omap_mcbsp_hwrule_min_buffersize,
					    mcbsp,
					    SNDRV_PCM_HW_PARAM_CHANNELS, -1);
146

147 148 149
		/* Make sure, that the period size is always even */
		snd_pcm_hw_constraint_step(substream->runtime, 0,
					   SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 2);
150 151
	}

152 153 154
	snd_soc_dai_set_dma_data(cpu_dai, substream,
				 &mcbsp->dma_data[substream->stream]);

155 156 157
	return err;
}

158
static void omap_mcbsp_dai_shutdown(struct snd_pcm_substream *substream,
159
				    struct snd_soc_dai *cpu_dai)
160
{
161
	struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
162 163

	if (!cpu_dai->active) {
164
		omap_mcbsp_free(mcbsp);
165
		mcbsp->configured = 0;
166 167 168
	}
}

169
static int omap_mcbsp_dai_trigger(struct snd_pcm_substream *substream, int cmd,
170
				  struct snd_soc_dai *cpu_dai)
171
{
172
	struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
173
	int err = 0, play = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
174 175 176 177 178

	switch (cmd) {
	case SNDRV_PCM_TRIGGER_START:
	case SNDRV_PCM_TRIGGER_RESUME:
	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
179
		mcbsp->active++;
180
		omap_mcbsp_start(mcbsp, play, !play);
181 182 183 184 185
		break;

	case SNDRV_PCM_TRIGGER_STOP:
	case SNDRV_PCM_TRIGGER_SUSPEND:
	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
186
		omap_mcbsp_stop(mcbsp, play, !play);
187
		mcbsp->active--;
188 189 190 191 192 193 194 195
		break;
	default:
		err = -EINVAL;
	}

	return err;
}

196 197 198 199 200
static snd_pcm_sframes_t omap_mcbsp_dai_delay(
			struct snd_pcm_substream *substream,
			struct snd_soc_dai *dai)
{
	struct snd_soc_pcm_runtime *rtd = substream->private_data;
201
	struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
202
	struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
203 204 205 206
	u16 fifo_use;
	snd_pcm_sframes_t delay;

	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
207
		fifo_use = omap_mcbsp_get_tx_delay(mcbsp);
208
	else
209
		fifo_use = omap_mcbsp_get_rx_delay(mcbsp);
210 211 212 213 214 215 216 217 218 219 220

	/*
	 * Divide the used locations with the channel count to get the
	 * FIFO usage in samples (don't care about partial samples in the
	 * buffer).
	 */
	delay = fifo_use / substream->runtime->channels;

	return delay;
}

221
static int omap_mcbsp_dai_hw_params(struct snd_pcm_substream *substream,
222
				    struct snd_pcm_hw_params *params,
223
				    struct snd_soc_dai *cpu_dai)
224
{
225
	struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
226
	struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs;
227
	struct snd_dmaengine_dai_dma_data *dma_data;
228
	int wlen, channels, wpf;
229
	int pkt_size = 0;
230
	unsigned int format, div, framesize, master;
231

232
	dma_data = snd_soc_dai_get_dma_data(cpu_dai, substream);
233
	channels = params_channels(params);
234

235 236
	switch (params_format(params)) {
	case SNDRV_PCM_FORMAT_S16_LE:
237
		wlen = 16;
238 239
		break;
	case SNDRV_PCM_FORMAT_S32_LE:
240
		wlen = 32;
241 242 243 244
		break;
	default:
		return -EINVAL;
	}
245
	if (mcbsp->pdata->buffer_size) {
246
		if (mcbsp->dma_op_mode == MCBSP_DMA_MODE_THRESHOLD) {
247
			int period_words, max_thrsh;
248
			int divider = 0;
249 250 251

			period_words = params_period_bytes(params) / (wlen / 8);
			if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
252
				max_thrsh = mcbsp->max_tx_thres;
253
			else
254
				max_thrsh = mcbsp->max_rx_thres;
255
			/*
256 257 258 259 260
			 * Use sDMA packet mode if McBSP is in threshold mode:
			 * If period words less than the FIFO size the packet
			 * size is set to the number of period words, otherwise
			 * Look for the biggest threshold value which divides
			 * the period size evenly.
261
			 */
262 263 264 265 266 267 268 269 270 271
			divider = period_words / max_thrsh;
			if (period_words % max_thrsh)
				divider++;
			while (period_words % divider &&
				divider < period_words)
				divider++;
			if (divider == period_words)
				return -EINVAL;

			pkt_size = period_words / divider;
272 273 274
		} else if (channels > 1) {
			/* Use packet mode for non mono streams */
			pkt_size = channels;
275
		}
276
		omap_mcbsp_set_threshold(substream, pkt_size);
277 278
	}

279
	dma_data->maxburst = pkt_size;
280

281
	if (mcbsp->configured) {
282 283 284 285
		/* McBSP already configured by another stream */
		return 0;
	}

286 287 288 289
	regs->rcr2	&= ~(RPHASE | RFRLEN2(0x7f) | RWDLEN2(7));
	regs->xcr2	&= ~(RPHASE | XFRLEN2(0x7f) | XWDLEN2(7));
	regs->rcr1	&= ~(RFRLEN1(0x7f) | RWDLEN1(7));
	regs->xcr1	&= ~(XFRLEN1(0x7f) | XWDLEN1(7));
290
	format = mcbsp->fmt & SND_SOC_DAIFMT_FORMAT_MASK;
291
	wpf = channels;
292 293
	if (channels == 2 && (format == SND_SOC_DAIFMT_I2S ||
			      format == SND_SOC_DAIFMT_LEFT_J)) {
294 295 296 297 298 299 300
		/* Use dual-phase frames */
		regs->rcr2	|= RPHASE;
		regs->xcr2	|= XPHASE;
		/* Set 1 word per (McBSP) frame for phase1 and phase2 */
		wpf--;
		regs->rcr2	|= RFRLEN2(wpf - 1);
		regs->xcr2	|= XFRLEN2(wpf - 1);
301 302
	}

303 304 305
	regs->rcr1	|= RFRLEN1(wpf - 1);
	regs->xcr1	|= XFRLEN1(wpf - 1);

306 307 308 309 310 311 312 313
	switch (params_format(params)) {
	case SNDRV_PCM_FORMAT_S16_LE:
		/* Set word lengths */
		regs->rcr2	|= RWDLEN2(OMAP_MCBSP_WORD_16);
		regs->rcr1	|= RWDLEN1(OMAP_MCBSP_WORD_16);
		regs->xcr2	|= XWDLEN2(OMAP_MCBSP_WORD_16);
		regs->xcr1	|= XWDLEN1(OMAP_MCBSP_WORD_16);
		break;
314 315 316 317 318 319 320
	case SNDRV_PCM_FORMAT_S32_LE:
		/* Set word lengths */
		regs->rcr2	|= RWDLEN2(OMAP_MCBSP_WORD_32);
		regs->rcr1	|= RWDLEN1(OMAP_MCBSP_WORD_32);
		regs->xcr2	|= XWDLEN2(OMAP_MCBSP_WORD_32);
		regs->xcr1	|= XWDLEN1(OMAP_MCBSP_WORD_32);
		break;
321 322 323 324 325
	default:
		/* Unsupported PCM format */
		return -EINVAL;
	}

326 327
	/* In McBSP master modes, FRAME (i.e. sample rate) is generated
	 * by _counting_ BCLKs. Calculate frame size in BCLKs */
328
	master = mcbsp->fmt & SND_SOC_DAIFMT_MASTER_MASK;
329
	if (master ==	SND_SOC_DAIFMT_CBS_CFS) {
330 331
		div = mcbsp->clk_div ? mcbsp->clk_div : 1;
		framesize = (mcbsp->in_freq / div) / params_rate(params);
332 333 334 335 336 337 338 339 340

		if (framesize < wlen * channels) {
			printk(KERN_ERR "%s: not enough bandwidth for desired rate and "
					"channels\n", __func__);
			return -EINVAL;
		}
	} else
		framesize = wlen * channels;

341
	/* Set FS period and length in terms of bit clock periods */
342 343
	regs->srgr2	&= ~FPER(0xfff);
	regs->srgr1	&= ~FWID(0xff);
344
	switch (format) {
345
	case SND_SOC_DAIFMT_I2S:
346
	case SND_SOC_DAIFMT_LEFT_J:
347 348
		regs->srgr2	|= FPER(framesize - 1);
		regs->srgr1	|= FWID((framesize >> 1) - 1);
349
		break;
350
	case SND_SOC_DAIFMT_DSP_A:
351
	case SND_SOC_DAIFMT_DSP_B:
352
		regs->srgr2	|= FPER(framesize - 1);
353
		regs->srgr1	|= FWID(0);
354 355 356
		break;
	}

357 358 359
	omap_mcbsp_config(mcbsp, &mcbsp->cfg_regs);
	mcbsp->wlen = wlen;
	mcbsp->configured = 1;
360 361 362 363 364 365 366 367

	return 0;
}

/*
 * This must be called before _set_clkdiv and _set_sysclk since McBSP register
 * cache is initialized here
 */
368
static int omap_mcbsp_dai_set_dai_fmt(struct snd_soc_dai *cpu_dai,
369 370
				      unsigned int fmt)
{
371
	struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
372
	struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs;
373
	bool inv_fs = false;
374

375
	if (mcbsp->configured)
376 377
		return 0;

378
	mcbsp->fmt = fmt;
379 380 381 382
	memset(regs, 0, sizeof(*regs));
	/* Generic McBSP register settings */
	regs->spcr2	|= XINTM(3) | FREE;
	regs->spcr1	|= RINTM(3);
383 384
	/* RFIG and XFIG are not defined in 2430 and on OMAP3+ */
	if (!mcbsp->pdata->has_ccr) {
385 386 387
		regs->rcr2	|= RFIG;
		regs->xcr2	|= XFIG;
	}
388 389 390

	/* Configure XCCR/RCCR only for revisions which have ccr registers */
	if (mcbsp->pdata->has_ccr) {
391 392
		regs->xccr = DXENDLY(1) | XDMAEN | XDISABLE;
		regs->rccr = RFULL_CYCLE | RDMAEN | RDISABLE;
393
	}
394 395 396 397 398 399 400

	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	case SND_SOC_DAIFMT_I2S:
		/* 1-bit data delay */
		regs->rcr2	|= RDATDLY(1);
		regs->xcr2	|= XDATDLY(1);
		break;
401 402 403 404 405 406
	case SND_SOC_DAIFMT_LEFT_J:
		/* 0-bit data delay */
		regs->rcr2	|= RDATDLY(0);
		regs->xcr2	|= XDATDLY(0);
		regs->spcr1	|= RJUST(2);
		/* Invert FS polarity configuration */
407
		inv_fs = true;
408
		break;
409 410 411 412 413
	case SND_SOC_DAIFMT_DSP_A:
		/* 1-bit data delay */
		regs->rcr2      |= RDATDLY(1);
		regs->xcr2      |= XDATDLY(1);
		/* Invert FS polarity configuration */
414
		inv_fs = true;
415
		break;
416
	case SND_SOC_DAIFMT_DSP_B:
417 418 419
		/* 0-bit data delay */
		regs->rcr2      |= RDATDLY(0);
		regs->xcr2      |= XDATDLY(0);
420
		/* Invert FS polarity configuration */
421
		inv_fs = true;
422
		break;
423 424 425 426 427 428 429 430 431 432 433 434 435
	default:
		/* Unsupported data format */
		return -EINVAL;
	}

	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
	case SND_SOC_DAIFMT_CBS_CFS:
		/* McBSP master. Set FS and bit clocks as outputs */
		regs->pcr0	|= FSXM | FSRM |
				   CLKXM | CLKRM;
		/* Sample rate generator drives the FS */
		regs->srgr2	|= FSGM;
		break;
436 437 438 439 440
	case SND_SOC_DAIFMT_CBM_CFS:
		/* McBSP slave. FS clock as output */
		regs->srgr2	|= FSGM;
		regs->pcr0	|= FSXM;
		break;
441 442 443 444 445 446 447 448 449
	case SND_SOC_DAIFMT_CBM_CFM:
		/* McBSP slave */
		break;
	default:
		/* Unsupported master/slave configuration */
		return -EINVAL;
	}

	/* Set bit clock (CLKX/CLKR) and FS polarities */
450
	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470
	case SND_SOC_DAIFMT_NB_NF:
		/*
		 * Normal BCLK + FS.
		 * FS active low. TX data driven on falling edge of bit clock
		 * and RX data sampled on rising edge of bit clock.
		 */
		regs->pcr0	|= FSXP | FSRP |
				   CLKXP | CLKRP;
		break;
	case SND_SOC_DAIFMT_NB_IF:
		regs->pcr0	|= CLKXP | CLKRP;
		break;
	case SND_SOC_DAIFMT_IB_NF:
		regs->pcr0	|= FSXP | FSRP;
		break;
	case SND_SOC_DAIFMT_IB_IF:
		break;
	default:
		return -EINVAL;
	}
471 472
	if (inv_fs == true)
		regs->pcr0 ^= FSXP | FSRP;
473 474 475 476

	return 0;
}

477
static int omap_mcbsp_dai_set_clkdiv(struct snd_soc_dai *cpu_dai,
478 479
				     int div_id, int div)
{
480
	struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
481
	struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs;
482 483 484 485

	if (div_id != OMAP_MCBSP_CLKGDV)
		return -ENODEV;

486
	mcbsp->clk_div = div;
487
	regs->srgr1	&= ~CLKGDV(0xff);
488 489 490 491 492
	regs->srgr1	|= CLKGDV(div - 1);

	return 0;
}

493
static int omap_mcbsp_dai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
494 495 496
					 int clk_id, unsigned int freq,
					 int dir)
{
497
	struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
498
	struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs;
499 500
	int err = 0;

501 502
	if (mcbsp->active) {
		if (freq == mcbsp->in_freq)
503 504 505
			return 0;
		else
			return -EBUSY;
506
	}
507

508 509 510
	mcbsp->in_freq = freq;
	regs->srgr2 &= ~CLKSM;
	regs->pcr0 &= ~SCLKME;
511

512 513 514 515 516
	switch (clk_id) {
	case OMAP_MCBSP_SYSCLK_CLK:
		regs->srgr2	|= CLKSM;
		break;
	case OMAP_MCBSP_SYSCLK_CLKS_FCLK:
517
		if (mcbsp_omap1()) {
518 519 520
			err = -EINVAL;
			break;
		}
521
		err = omap2_mcbsp_set_clks_src(mcbsp,
522 523
					       MCBSP_CLKS_PRCM_SRC);
		break;
524
	case OMAP_MCBSP_SYSCLK_CLKS_EXT:
525
		if (mcbsp_omap1()) {
526 527 528
			err = 0;
			break;
		}
529
		err = omap2_mcbsp_set_clks_src(mcbsp,
530
					       MCBSP_CLKS_PAD_SRC);
531 532 533 534 535 536 537 538 539 540 541 542 543 544
		break;

	case OMAP_MCBSP_SYSCLK_CLKX_EXT:
		regs->srgr2	|= CLKSM;
	case OMAP_MCBSP_SYSCLK_CLKR_EXT:
		regs->pcr0	|= SCLKME;
		break;
	default:
		err = -ENODEV;
	}

	return err;
}

545
static const struct snd_soc_dai_ops mcbsp_dai_ops = {
546 547 548
	.startup	= omap_mcbsp_dai_startup,
	.shutdown	= omap_mcbsp_dai_shutdown,
	.trigger	= omap_mcbsp_dai_trigger,
549
	.delay		= omap_mcbsp_dai_delay,
550 551 552 553 554 555
	.hw_params	= omap_mcbsp_dai_hw_params,
	.set_fmt	= omap_mcbsp_dai_set_dai_fmt,
	.set_clkdiv	= omap_mcbsp_dai_set_clkdiv,
	.set_sysclk	= omap_mcbsp_dai_set_dai_sysclk,
};

556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573
static int omap_mcbsp_probe(struct snd_soc_dai *dai)
{
	struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(dai);

	pm_runtime_enable(mcbsp->dev);

	return 0;
}

static int omap_mcbsp_remove(struct snd_soc_dai *dai)
{
	struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(dai);

	pm_runtime_disable(mcbsp->dev);

	return 0;
}

574
static struct snd_soc_dai_driver omap_mcbsp_dai = {
575 576
	.probe = omap_mcbsp_probe,
	.remove = omap_mcbsp_remove,
577 578 579 580 581 582 583 584 585 586 587 588 589
	.playback = {
		.channels_min = 1,
		.channels_max = 16,
		.rates = OMAP_MCBSP_RATES,
		.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE,
	},
	.capture = {
		.channels_min = 1,
		.channels_max = 16,
		.rates = OMAP_MCBSP_RATES,
		.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE,
	},
	.ops = &mcbsp_dai_ops,
590
};
591

592 593 594 595
static const struct snd_soc_component_driver omap_mcbsp_component = {
	.name		= "omap-mcbsp",
};

596
static int omap_mcbsp_st_info_volsw(struct snd_kcontrol *kcontrol,
597 598 599 600 601 602 603 604 605 606 607 608 609 610
			struct snd_ctl_elem_info *uinfo)
{
	struct soc_mixer_control *mc =
		(struct soc_mixer_control *)kcontrol->private_value;
	int max = mc->max;
	int min = mc->min;

	uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
	uinfo->count = 1;
	uinfo->value.integer.min = min;
	uinfo->value.integer.max = max;
	return 0;
}

611
#define OMAP_MCBSP_ST_CHANNEL_VOLUME(channel)				\
612
static int								\
613
omap_mcbsp_set_st_ch##channel##_volume(struct snd_kcontrol *kc,		\
614 615
					struct snd_ctl_elem_value *uc)	\
{									\
616 617
	struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kc);		\
	struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);	\
618 619 620 621 622 623 624 625 626 627
	struct soc_mixer_control *mc =					\
		(struct soc_mixer_control *)kc->private_value;		\
	int max = mc->max;						\
	int min = mc->min;						\
	int val = uc->value.integer.value[0];				\
									\
	if (val < min || val > max)					\
		return -EINVAL;						\
									\
	/* OMAP McBSP implementation uses index values 0..4 */		\
628
	return omap_st_set_chgain(mcbsp, channel, val);			\
629 630
}									\
									\
631
static int								\
632
omap_mcbsp_get_st_ch##channel##_volume(struct snd_kcontrol *kc,		\
633 634
					struct snd_ctl_elem_value *uc)	\
{									\
635 636
	struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kc);		\
	struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);	\
637 638
	s16 chgain;							\
									\
639
	if (omap_st_get_chgain(mcbsp, channel, &chgain))		\
640 641 642 643 644 645
		return -EAGAIN;						\
									\
	uc->value.integer.value[0] = chgain;				\
	return 0;							\
}

646 647
OMAP_MCBSP_ST_CHANNEL_VOLUME(0)
OMAP_MCBSP_ST_CHANNEL_VOLUME(1)
648 649 650 651

static int omap_mcbsp_st_put_mode(struct snd_kcontrol *kcontrol,
				struct snd_ctl_elem_value *ucontrol)
{
652 653
	struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
	struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
654 655
	u8 value = ucontrol->value.integer.value[0];

656
	if (value == omap_st_is_enabled(mcbsp))
657 658 659
		return 0;

	if (value)
660
		omap_st_enable(mcbsp);
661
	else
662
		omap_st_disable(mcbsp);
663 664 665 666 667 668 669

	return 1;
}

static int omap_mcbsp_st_get_mode(struct snd_kcontrol *kcontrol,
				struct snd_ctl_elem_value *ucontrol)
{
670 671
	struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
	struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
672

673
	ucontrol->value.integer.value[0] = omap_st_is_enabled(mcbsp);
674 675 676
	return 0;
}

677 678 679 680 681 682 683 684 685 686 687 688 689
#define OMAP_MCBSP_ST_CONTROLS(port)					  \
static const struct snd_kcontrol_new omap_mcbsp##port##_st_controls[] = { \
SOC_SINGLE_EXT("McBSP" #port " Sidetone Switch", 1, 0, 1, 0,		  \
	       omap_mcbsp_st_get_mode, omap_mcbsp_st_put_mode),		  \
OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP" #port " Sidetone Channel 0 Volume", \
			      -32768, 32767,				  \
			      omap_mcbsp_get_st_ch0_volume,		  \
			      omap_mcbsp_set_st_ch0_volume),		  \
OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP" #port " Sidetone Channel 1 Volume", \
			      -32768, 32767,				  \
			      omap_mcbsp_get_st_ch1_volume,		  \
			      omap_mcbsp_set_st_ch1_volume),		  \
}
690

691 692
OMAP_MCBSP_ST_CONTROLS(2);
OMAP_MCBSP_ST_CONTROLS(3);
693

694
int omap_mcbsp_st_add_controls(struct snd_soc_pcm_runtime *rtd)
695
{
696 697 698
	struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
	struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);

699 700 701 702
	if (!mcbsp->st_data) {
		dev_warn(mcbsp->dev, "No sidetone data for port\n");
		return 0;
	}
703

704
	switch (mcbsp->id) {
705 706 707
	case 2: /* McBSP 2 */
		return snd_soc_add_dai_controls(cpu_dai,
					omap_mcbsp2_st_controls,
708
					ARRAY_SIZE(omap_mcbsp2_st_controls));
709 710 711
	case 3: /* McBSP 3 */
		return snd_soc_add_dai_controls(cpu_dai,
					omap_mcbsp3_st_controls,
712 713 714 715 716 717 718 719 720
					ARRAY_SIZE(omap_mcbsp3_st_controls));
	default:
		break;
	}

	return -EINVAL;
}
EXPORT_SYMBOL_GPL(omap_mcbsp_st_add_controls);

721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766
static struct omap_mcbsp_platform_data omap2420_pdata = {
	.reg_step = 4,
	.reg_size = 2,
};

static struct omap_mcbsp_platform_data omap2430_pdata = {
	.reg_step = 4,
	.reg_size = 4,
	.has_ccr = true,
};

static struct omap_mcbsp_platform_data omap3_pdata = {
	.reg_step = 4,
	.reg_size = 4,
	.has_ccr = true,
	.has_wakeup = true,
};

static struct omap_mcbsp_platform_data omap4_pdata = {
	.reg_step = 4,
	.reg_size = 4,
	.has_ccr = true,
	.has_wakeup = true,
};

static const struct of_device_id omap_mcbsp_of_match[] = {
	{
		.compatible = "ti,omap2420-mcbsp",
		.data = &omap2420_pdata,
	},
	{
		.compatible = "ti,omap2430-mcbsp",
		.data = &omap2430_pdata,
	},
	{
		.compatible = "ti,omap3-mcbsp",
		.data = &omap3_pdata,
	},
	{
		.compatible = "ti,omap4-mcbsp",
		.data = &omap4_pdata,
	},
	{ },
};
MODULE_DEVICE_TABLE(of, omap_mcbsp_of_match);

767
static int asoc_mcbsp_probe(struct platform_device *pdev)
768
{
769 770
	struct omap_mcbsp_platform_data *pdata = dev_get_platdata(&pdev->dev);
	struct omap_mcbsp *mcbsp;
771
	const struct of_device_id *match;
772 773
	int ret;

774 775 776 777 778 779 780 781 782 783 784 785 786 787 788
	match = of_match_device(omap_mcbsp_of_match, &pdev->dev);
	if (match) {
		struct device_node *node = pdev->dev.of_node;
		int buffer_size;

		pdata = devm_kzalloc(&pdev->dev,
				     sizeof(struct omap_mcbsp_platform_data),
				     GFP_KERNEL);
		if (!pdata)
			return -ENOMEM;

		memcpy(pdata, match->data, sizeof(*pdata));
		if (!of_property_read_u32(node, "ti,buffer-size", &buffer_size))
			pdata->buffer_size = buffer_size;
	} else if (!pdata) {
789 790 791 792 793 794 795 796 797 798 799 800 801
		dev_err(&pdev->dev, "missing platform data.\n");
		return -EINVAL;
	}
	mcbsp = devm_kzalloc(&pdev->dev, sizeof(struct omap_mcbsp), GFP_KERNEL);
	if (!mcbsp)
		return -ENOMEM;

	mcbsp->id = pdev->id;
	mcbsp->pdata = pdata;
	mcbsp->dev = &pdev->dev;
	platform_set_drvdata(pdev, mcbsp);

	ret = omap_mcbsp_init(pdev);
802
	if (!ret)
803 804
		return snd_soc_register_component(&pdev->dev, &omap_mcbsp_component,
						  &omap_mcbsp_dai, 1);
805 806

	return ret;
807 808
}

809
static int asoc_mcbsp_remove(struct platform_device *pdev)
810
{
811 812
	struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev);

813
	snd_soc_unregister_component(&pdev->dev);
814 815 816 817 818 819 820 821

	if (mcbsp->pdata->ops && mcbsp->pdata->ops->free)
		mcbsp->pdata->ops->free(mcbsp->id);

	omap_mcbsp_sysfs_remove(mcbsp);

	clk_put(mcbsp->fclk);

822 823 824 825 826
	return 0;
}

static struct platform_driver asoc_mcbsp_driver = {
	.driver = {
827
			.name = "omap-mcbsp",
828
			.owner = THIS_MODULE,
829
			.of_match_table = omap_mcbsp_of_match,
830 831 832
	},

	.probe = asoc_mcbsp_probe,
833
	.remove = asoc_mcbsp_remove,
834 835
};

836
module_platform_driver(asoc_mcbsp_driver);
Mark Brown's avatar
Mark Brown committed
837

838
MODULE_AUTHOR("Jarkko Nikula <jarkko.nikula@bitmer.com>");
839 840
MODULE_DESCRIPTION("OMAP I2S SoC Interface");
MODULE_LICENSE("GPL");
841
MODULE_ALIAS("platform:omap-mcbsp");