Let's handle GPIOs by banks, each bank covers up to 32 GPIOs with one set
of registers, and each set of registers start from different offsets.

           GPLR    GPDR    GPSR    GPCR    GRER    GFER    GEDR
 BANK 0 - 0x0000  0x000C  0x0018  0x0024  0x0030  0x003C  0x0048
 BANK 1 - 0x0004  0x0010  0x001C  0x0028  0x0034  0x0040  0x004C
 BANK 2 - 0x0008  0x0014  0x0020  0x002C  0x0038  0x0044  0x0050

 BANK 3 - 0x0100  0x010C  0x0118  0x0124  0x0130  0x013C  0x0148
 BANK 4 - 0x0104  0x0110  0x011C  0x0128  0x0134  0x0140  0x014C
 BANK 5 - 0x0108  0x0114  0x0120  0x012C  0x0138  0x0144  0x0150

 NOTE:
   BANK 3 is only available on PXA27x and later processors.
   BANK 4 and 5 are only available on PXA935

1. introduce GPIO_BANK(n) for the offset base of each bank

2. 'struct pxa_gpio_chip' is expanded to include IRQ edge and mask
   setings, and saved register values as well, and is dynamically
   allocated due to possible bank number ranging from 3 to 6

3. all accesses to GPIO registers are made through 'regbase' within
   'pxa_gpio_chip', and register offset

4. introduce several inline functions to simplify the code a bit

5. change IRQ demux handler to base on gpio chips
Signed-off-by: Mike Rapoport <mike@compulab.co.il>
Signed-off-by: Eric Miao <eric.miao@marvell.com>