• Rich Felker's avatar
    clocksource: Add J-Core timer/clocksource driver · 9995f4f1
    Rich Felker authored
    At the hardware level, the J-Core PIT is integrated with the interrupt
    controller, but it is represented as its own device and has an
    independent programming interface. It provides a 12-bit countdown
    timer, which is not presently used, and a periodic timer. The interval
    length for the latter is programmable via a 32-bit throttle register
    whose units are determined by a bus-period register. The periodic
    timer is used to implement both periodic and oneshot clock event
    modes; in oneshot mode the interrupt handler simply disables the timer
    as soon as it fires.
    
    Despite its device tree node representing an interrupt for the PIT,
    the actual irq generated is programmable, not hard-wired. The driver
    is responsible for programming the PIT to generate the hardware irq
    number that the DT assigns to it.
    
    On SMP configurations, J-Core provides cpu-local instances of the PIT;
    no broadcast timer is needed. This driver supports the creation of the
    necessary per-cpu clock_event_device instances.
    
    A nanosecond-resolution clocksource is provided using the J-Core "RTC"
    registers, which give a 64-bit seconds count and 32-bit nanoseconds
    that wrap every second. The driver converts these to a full-range
    32-bit nanoseconds count.
    Signed-off-by: default avatarRich Felker <dalias@libc.org>
    Cc: Mark Rutland <mark.rutland@arm.com>
    Cc: devicetree@vger.kernel.org
    Cc: linux-sh@vger.kernel.org
    Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
    Cc: Rob Herring <robh+dt@kernel.org>
    Link: http://lkml.kernel.org/r/b591ff12cc5ebf63d1edc98da26046f95a233814.1476393790.git.dalias@libc.orgSigned-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
    9995f4f1
jcore-pit.c 6.54 KB