• Cédric Le Goater's avatar
    KVM: PPC: Book3S HV: XIVE: Add a TIMA mapping · 39e9af3d
    Cédric Le Goater authored
    Each thread has an associated Thread Interrupt Management context
    composed of a set of registers. These registers let the thread handle
    priority management and interrupt acknowledgment. The most important
    are :
    
        - Interrupt Pending Buffer     (IPB)
        - Current Processor Priority   (CPPR)
        - Notification Source Register (NSR)
    
    They are exposed to software in four different pages each proposing a
    view with a different privilege. The first page is for the physical
    thread context and the second for the hypervisor. Only the third
    (operating system) and the fourth (user level) are exposed the guest.
    
    A custom VM fault handler will populate the VMA with the appropriate
    pages, which should only be the OS page for now.
    Signed-off-by: default avatarCédric Le Goater <clg@kaod.org>
    Reviewed-by: default avatarDavid Gibson <david@gibson.dropbear.id.au>
    Signed-off-by: default avatarPaul Mackerras <paulus@ozlabs.org>
    39e9af3d
native.c 19 KB