• Lucas Stach's avatar
    clk: tegra: Fix PLL_U post divider and initial rate on Tegra30 · 79709730
    Lucas Stach authored
    The post divider value in the frequency table is wrong as it would lead
    to the PLL producing an output rate of 960 MHz instead of the desired
    480 MHz. This wasn't a problem as nothing used the table to actually
    initialize the PLL rate, but the bootloader configuration was used
    unaltered.
    
    If the bootloader does not set up the PLL it will fail to come when used
    under Linux. To fix this don't rely on the bootloader, but set the
    correct rate in the clock driver.
    Signed-off-by: default avatarLucas Stach <dev@lynxeye.de>
    Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
    79709730
clk-tegra30.c 55.4 KB