• Benjamin Herrenschmidt's avatar
    powerpc/perf: Fix instruction address sampling on 970 and Power4 · 1ce447b9
    Benjamin Herrenschmidt authored
    970 and Power4 don't support "continuous sampling" which means that
    when we aren't in marked instruction sampling mode (marked events),
    SIAR isn't updated with the last instruction sampled before the
    perf interrupt. On those processors, we must thus use the exception
    SRR0 value as the sampled instruction pointer.
    
    Those processors also don't support the SIPR and SIHV bits in MMCRA
    which means we need some kind of heuristic to decide if SIAR values
    represent kernel or user addresses.
    Signed-off-by: default avatarBenjamin Herrenschmidt <benh@kernel.crashing.org>
    1ce447b9
power4-pmu.c 16.9 KB