• Alexey Brodkin's avatar
    ARCv2: Support IO Coherency and permutations involving L1 and L2 caches · f2b0b25a
    Alexey Brodkin authored
    In case of ARCv2 CPU there're could be following configurations
    that affect cache handling for data exchanged with peripherals
    via DMA:
     [1] Only L1 cache exists
     [2] Both L1 and L2 exist, but no IO coherency unit
     [3] L1, L2 caches and IO coherency unit exist
    
    Current implementation takes care of [1] and [2].
    Moreover support of [2] is implemented with run-time check
    for SLC existence which is not super optimal.
    
    This patch introduces support of [3] and rework of DMA ops
    usage. Instead of doing run-time check every time a particular
    DMA op is executed we'll have 3 different implementations of
    DMA ops and select appropriate one during init.
    
    As for IOC support for it we need:
     [a] Implement empty DMA ops because IOC takes care of cache
         coherency with DMAed data
     [b] Route dma_alloc_coherent() via dma_alloc_noncoherent()
         This is required to make IOC work in first place and also
         serves as optimization as LD/ST to coherent buffers can be
         srviced from caches w/o going all the way to memory
    Signed-off-by: default avatarAlexey Brodkin <abrodkin@synopsys.com>
    [vgupta:
      -Added some comments about IOC gains
      -Marked dma ops as static,
      -Massaged changelog a bit]
    Signed-off-by: default avatarVineet Gupta <vgupta@synopsys.com>
    f2b0b25a
arcregs.h 9.34 KB