• Aneesh Kumar K.V's avatar
    powerpc/mm/hash: Don't add memory coherence if cache inhibited is set · e568006b
    Aneesh Kumar K.V authored
    H_ENTER hcall handling in qemu had assumptions that a cache inhibited
    hpte entry won't have memory conference set. Also older kernel
    mentioned that some version of pHyp required this (the code removed
    by the below commit says:
    
        /* Make pHyp happy */
        if ((rflags & _PAGE_NO_CACHE) && !(rflags & _PAGE_WRITETHRU))
                hpte_r &= ~HPTE_R_M;
    
    But with older kernel we had some inconsistent memory conherence
    mapping. We always enabled memory conherence in the page fault path and
    removed memory conherence is _PAGE_NO_CACHE was set when we mapped the
    page via htab_bolt_mapping. The commit mentioned below tried to
    consolidate that by always enabling memory conherence. But as mentioned
    above that breaks Qemu H_ENTER handling.
    
    This patch update this such that we enable memory conherence only if
    cache inhibited is not set and bring fault handling, lpar and bolt
    mapping in sync.
    
    Fixes: commit 30bda41a("powerpc/mm: Drop WIMG in favour of new constant")
    Reported-by: default avatarDarrick J. Wong <darrick.wong@oracle.com>
    Signed-off-by: default avatarAneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
    Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
    e568006b
hash_utils_64.c 45.6 KB