• Shanker Donthineni's avatar
    arm64: Add software workaround for Falkor erratum 1041 · 3060e9f0
    Shanker Donthineni authored
    The ARM architecture defines the memory locations that are permitted
    to be accessed as the result of a speculative instruction fetch from
    an exception level for which all stages of translation are disabled.
    Specifically, the core is permitted to speculatively fetch from the
    4KB region containing the current program counter 4K and next 4K.
    
    When translation is changed from enabled to disabled for the running
    exception level (SCTLR_ELn[M] changed from a value of 1 to 0), the
    Falkor core may errantly speculatively access memory locations outside
    of the 4KB region permitted by the architecture. The errant memory
    access may lead to one of the following unexpected behaviors.
    
    1) A System Error Interrupt (SEI) being raised by the Falkor core due
       to the errant memory access attempting to access a region of memory
       that is protected by a slave-side memory protection unit.
    2) Unpredictable device behavior due to a speculative read from device
       memory. This behavior may only occur if the instruction cache is
       disabled prior to or coincident with translation being changed from
       enabled to disabled.
    
    The conditions leading to this erratum will not occur when either of the
    following occur:
     1) A higher exception level disables translation of a lower exception level
       (e.g. EL2 changing SCTLR_EL1[M] from a value of 1 to 0).
     2) An exception level disabling its stage-1 translation if its stage-2
        translation is enabled (e.g. EL1 changing SCTLR_EL1[M] from a value of 1
        to 0 when HCR_EL2[VM] has a value of 1).
    
    To avoid the errant behavior, software must execute an ISB immediately
    prior to executing the MSR that will change SCTLR_ELn[M] from 1 to 0.
    Signed-off-by: default avatarShanker Donthineni <shankerd@codeaurora.org>
    Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
    Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
    3060e9f0
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