• Tudor Ambarus's avatar
    mtd: spi-nor: use 16-bit WRR command when QE is set on spansion flashes · 191f5c2e
    Tudor Ambarus authored
    SPI memory devices from different manufacturers have widely
    different configurations for Status, Control and Configuration
    registers. JEDEC 216C defines a new map for these common register
    bits and their functions, and describes how the individual bits may
    be accessed for a specific device. For the JEDEC 216B compliant
    flashes, we can partially deduce Status and Configuration registers
    functions by inspecting the 16th DWORD of BFPT. Older flashes that
    don't declare the SFDP tables (SPANSION FL512SAIFG1 311QQ063 A ©11
    SPANSION) let the software decide how to interact with these registers.
    
    The commit dcb4b22e ("spi-nor: s25fl512s supports region locking")
    uncovered a probe error for s25fl512s, when the Quad Enable bit CR[1]
    was set to one in the bootloader. When this bit is one, only the Write
    Status (01h) command with two data byts may be used, the 01h command with
    one data byte is not recognized and hence the error when trying to clear
    the block protection bits.
    
    Fix the above by using the Write Status (01h) command with two data bytes
    when the Quad Enable bit is one.
    
    Backward compatibility should be fine. The newly introduced
    spi_nor_spansion_clear_sr_bp() is tightly coupled with the
    spansion_quad_enable() function. Both assume that the Write Register
    with 16 bits, together with the Read Configuration Register (35h)
    instructions are supported.
    
    Fixes: dcb4b22e ("spi-nor: s25fl512s supports region locking")
    Reported-by: default avatarGeert Uytterhoeven <geert@linux-m68k.org>
    Signed-off-by: default avatarTudor Ambarus <tudor.ambarus@microchip.com>
    Tested-by: default avatarJonas Bonn <jonas@norrbonn.se>
    Tested-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
    Reviewed-by: default avatarVignesh Raghavendra <vigneshr@ti.com>
    Tested-by: default avatarVignesh Raghavendra <vigneshr@ti.com>
    Signed-off-by: default avatarMiquel Raynal <miquel.raynal@bootlin.com>
    191f5c2e
spi-nor.c 123 KB