• Abhilash Kesavan's avatar
    thermal: exynos: Add TMU support for Exynos7 SoC · 6c247393
    Abhilash Kesavan authored
    Add registers, bit fields and compatible strings for Exynos7 TMU
    (Thermal Management Unit). Following are a few of the differences
    in the Exynos7 TMU from earlier SoCs:
            - 8 trigger levels
            - Different bit offsets and more registers for the rising
            and falling thresholds.
            - New power down detection bit in the TMU_CONTROL register
            which does not update the CURRENT_TEMP0 when tmu power down
            is detected.
            - Change in bit offset for the NEXT_DATA field of EMUL_CON
            register. EMUL_CON register address has also changed.
            - INTSTAT and INTCLEAR registers present in earlier SoCs
            have been combined into one INTPEND register. The register
            address for INTCLEAR and INTPEND is also different.
            - Since there are 8 rising/falling interrupts as against
            at most 4 in earlier SoCs the INTEN bit offsets are different.
            - Multiple probe support which is handled by a TMU_CONTROL1
            register (No support for this in the current patch).
    
    This patch adds special clock support required only for Exynos7. It
    also updates the "code_to_temp" prototype as Exynos7 has 9 bit
    code-temp mapping.
    Acked-by: default avatarLukasz Majewski <l.majewski@samsung.com>
    Tested-by: default avatarLukasz Majewski <l.majewski@samsung.com>
    Signed-off-by: default avatarAbhilash Kesavan <a.kesavan@samsung.com>
    Signed-off-by: default avatarEduardo Valentin <edubezval@gmail.com>
    6c247393
exynos_tmu.c 36.7 KB