pci_dma.c 17.9 KB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700
/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 2000,2002-2003 Silicon Graphics, Inc. All rights reserved.
 *
 * Routines for PCI DMA mapping.  See Documentation/DMA-mapping.txt for
 * a description of how these routines should be used.
 */

#include <linux/config.h>
#include <linux/types.h>
#include <linux/mm.h>
#include <linux/string.h>
#include <linux/pci.h>
#include <linux/slab.h>
#include <linux/module.h>

#include <asm/delay.h>
#include <asm/io.h>
#include <asm/sn/sgi.h>
#include <asm/sn/io.h>
#include <asm/sn/invent.h>
#include <asm/sn/hcl.h>
#include <asm/sn/pci/pcibr.h>
#include <asm/sn/pci/pcibr_private.h>
#include <asm/sn/driver.h>
#include <asm/sn/types.h>
#include <asm/sn/alenlist.h>
#include <asm/sn/pci/pci_bus_cvlink.h>
#include <asm/sn/nag.h>

/*
 * For ATE allocations
 */
pciio_dmamap_t get_free_pciio_dmamap(vertex_hdl_t);
void free_pciio_dmamap(pcibr_dmamap_t);
static struct pcibr_dmamap_s *find_sn_dma_map(dma_addr_t, unsigned char);
void sn_pci_unmap_sg(struct pci_dev *hwdev, struct scatterlist *sg, int nents, int direction);

/*
 * Toplogy stuff
 */
extern vertex_hdl_t busnum_to_pcibr_vhdl[];
extern nasid_t busnum_to_nid[];
extern void * busnum_to_atedmamaps[];

/**
 * get_free_pciio_dmamap - find and allocate an ATE
 * @pci_bus: PCI bus to get an entry for
 *
 * Finds and allocates an ATE on the PCI bus specified
 * by @pci_bus.
 */
pciio_dmamap_t
get_free_pciio_dmamap(vertex_hdl_t pci_bus)
{
	int i;
	struct pcibr_dmamap_s *sn_dma_map = NULL;

	/*
	 * Darn, we need to get the maps allocated for this bus.
	 */
	for (i = 0; i < MAX_PCI_XWIDGET; i++) {
		if (busnum_to_pcibr_vhdl[i] == pci_bus) {
			sn_dma_map = busnum_to_atedmamaps[i];
		}
	}

	/*
	 * Now get a free dmamap entry from this list.
	 */
	for (i = 0; i < MAX_ATE_MAPS; i++, sn_dma_map++) {
		if (!sn_dma_map->bd_dma_addr) {
			sn_dma_map->bd_dma_addr = -1;
			return( (pciio_dmamap_t) sn_dma_map );
		}
	}

	return NULL;
}

/**
 * free_pciio_dmamap - free an ATE
 * @dma_map: ATE to free
 *
 * Frees the ATE specified by @dma_map.
 */
void
free_pciio_dmamap(pcibr_dmamap_t dma_map)
{
	dma_map->bd_dma_addr = 0;
}

/**
 * find_sn_dma_map - find an ATE associated with @dma_addr and @busnum
 * @dma_addr: DMA address to look for
 * @busnum: PCI bus to look on
 *
 * Finds the ATE associated with @dma_addr and @busnum.
 */
static struct pcibr_dmamap_s *
find_sn_dma_map(dma_addr_t dma_addr, unsigned char busnum)
{

	struct pcibr_dmamap_s *sn_dma_map = NULL;
	int i;

	sn_dma_map = busnum_to_atedmamaps[busnum];

	for (i = 0; i < MAX_ATE_MAPS; i++, sn_dma_map++) {
		if (sn_dma_map->bd_dma_addr == dma_addr) {
			return sn_dma_map;
		}
	}

	return NULL;
}

/**
 * sn_pci_alloc_consistent - allocate memory for coherent DMA
 * @hwdev: device to allocate for
 * @size: size of the region
 * @dma_handle: DMA (bus) address
 *
 * pci_alloc_consistent() returns a pointer to a memory region suitable for
 * coherent DMA traffic to/from a PCI device.  On SN platforms, this means
 * that @dma_handle will have the %PCIIO_DMA_CMD flag set.
 *
 * This interface is usually used for "command" streams (e.g. the command
 * queue for a SCSI controller).  See Documentation/DMA-mapping.txt for
 * more information.  Note that this routine will always put a 32 bit
 * DMA address into @dma_handle.  This is because most devices
 * that are capable of 64 bit PCI DMA transactions can't do 64 bit _coherent_
 * DMAs, and unfortunately this interface has to cater to the LCD.  Oh well.
 *
 * Also known as platform_pci_alloc_consistent() by the IA64 machvec code.
 */
void *
sn_pci_alloc_consistent(struct pci_dev *hwdev, size_t size, dma_addr_t *dma_handle)
{
        void *cpuaddr;
	vertex_hdl_t vhdl;
	struct sn_device_sysdata *device_sysdata;
	unsigned long phys_addr;
	pcibr_dmamap_t dma_map = 0;

	*dma_handle = 0;

	if (hwdev->dma_mask < 0xffffffffUL)
		return NULL;

	/*
	 * Get hwgraph vertex for the device
	 */
	device_sysdata = (struct sn_device_sysdata *) hwdev->sysdata;
	vhdl = device_sysdata->vhdl;

	/*
	 * Allocate the memory.  FIXME: if we're allocating for
	 * two devices on the same bus, we should at least try to
	 * allocate memory in the same 2 GB window to avoid using
	 * ATEs for the translation.  See the comment above about the
	 * 32 bit requirement for this function.
	 */
	if(!(cpuaddr = (void *)__get_free_pages(GFP_ATOMIC, get_order(size))))
		return NULL;

	/* physical addr. of the memory we just got */
	phys_addr = __pa(cpuaddr);

	/*
	 * This will try to use a Direct Map register to do the
	 * 32 bit DMA mapping, but it may not succeed if another
	 * device on the same bus is already mapped with different
	 * attributes or to a different memory region.
	 */
	*dma_handle = pcibr_dmatrans_addr(vhdl, NULL, phys_addr, size,
			((IS_PIC_DEVICE(hwdev)) ? 0 : PCIIO_BYTE_STREAM) |
					  PCIIO_DMA_CMD);

        /*
	 * If this device is in PCI-X mode, the system would have
	 * automatically allocated a 64Bits DMA Address.  Error out if the 
	 * device cannot support DAC.
	 */
	if (*dma_handle > hwdev->consistent_dma_mask) {
		free_pages((unsigned long) cpuaddr, get_order(size));
		return NULL;
	}

	/*
	 * It is a 32 bit card and we cannot do direct mapping,
	 * so we try to use an ATE.
	 */
	if (!(*dma_handle)) {
		dma_map = pcibr_dmamap_alloc(vhdl, NULL, size,
				((IS_PIC_DEVICE(hwdev)) ? 0 : PCIIO_BYTE_STREAM) |
					     PCIIO_DMA_CMD);
		if (!dma_map) {
			printk(KERN_ERR "sn_pci_alloc_consistent: Unable to "
			       "allocate anymore 32 bit page map entries.\n");
			return 0;
		}
		*dma_handle = (dma_addr_t) pcibr_dmamap_addr(dma_map,phys_addr,
							     size);
		dma_map->bd_dma_addr = *dma_handle;
	}

        return cpuaddr;
}

/**
 * sn_pci_free_consistent - free memory associated with coherent DMAable region
 * @hwdev: device to free for
 * @size: size to free
 * @vaddr: kernel virtual address to free
 * @dma_handle: DMA address associated with this region
 *
 * Frees the memory allocated by pci_alloc_consistent().  Also known
 * as platform_pci_free_consistent() by the IA64 machvec code.
 */
void
sn_pci_free_consistent(struct pci_dev *hwdev, size_t size, void *vaddr, dma_addr_t dma_handle)
{
	struct pcibr_dmamap_s *dma_map = NULL;

	/*
	 * Get the sn_dma_map entry.
	 */
	if (IS_PCI32_MAPPED(dma_handle))
		dma_map = find_sn_dma_map(dma_handle, hwdev->bus->number);

	/*
	 * and free it if necessary...
	 */
	if (dma_map) {
		pcibr_dmamap_done(dma_map);
		pcibr_dmamap_free(dma_map);
		dma_map->bd_dma_addr = 0;
	}
	free_pages((unsigned long) vaddr, get_order(size));
}

/**
 * sn_pci_map_sg - map a scatter-gather list for DMA
 * @hwdev: device to map for
 * @sg: scatterlist to map
 * @nents: number of entries
 * @direction: direction of the DMA transaction
 *
 * Maps each entry of @sg for DMA.  Also known as platform_pci_map_sg by the
 * IA64 machvec code.
 */
int
sn_pci_map_sg(struct pci_dev *hwdev, struct scatterlist *sg, int nents, int direction)
{

	int i;
	vertex_hdl_t vhdl;
	unsigned long phys_addr;
	struct sn_device_sysdata *device_sysdata;
	pcibr_dmamap_t dma_map;
	struct scatterlist *saved_sg = sg;

	/* can't go anywhere w/o a direction in life */
	if (direction == PCI_DMA_NONE)
		BUG();

	/*
	 * Get the hwgraph vertex for the device
	 */
	device_sysdata = (struct sn_device_sysdata *) hwdev->sysdata;
	vhdl = device_sysdata->vhdl;

	/*
	 * Setup a DMA address for each entry in the
	 * scatterlist.
	 */
	for (i = 0; i < nents; i++, sg++) {
		phys_addr = __pa((unsigned long)page_address(sg->page) + sg->offset);

		/*
		 * Handle the most common case: 64 bit cards.  This
		 * call should always succeed.
		 */
		if (IS_PCIA64(hwdev)) {
			sg->dma_address = pcibr_dmatrans_addr(vhdl, NULL, phys_addr,
						       sg->length,
			       ((IS_PIC_DEVICE(hwdev)) ? 0 : PCIIO_BYTE_STREAM) |
						       PCIIO_DMA_DATA |
						       PCIIO_DMA_A64);
			sg->dma_length = sg->length;
			continue;
		}

		/*
		 * Handle 32-63 bit cards via direct mapping
		 */
		if (IS_PCI32G(hwdev)) {
			sg->dma_address = pcibr_dmatrans_addr(vhdl, NULL, phys_addr,
						       sg->length,
					((IS_PIC_DEVICE(hwdev)) ? 0 : PCIIO_BYTE_STREAM) |
						       PCIIO_DMA_DATA);
			sg->dma_length = sg->length;
			/*
			 * See if we got a direct map entry
			 */
			if (sg->dma_address) {
				continue;
			}

		}

		/*
		 * It is a 32 bit card and we cannot do direct mapping,
		 * so we use an ATE.
		 */
		dma_map = pcibr_dmamap_alloc(vhdl, NULL, sg->length,
				((IS_PIC_DEVICE(hwdev)) ? 0 : PCIIO_BYTE_STREAM) |
					     PCIIO_DMA_DATA);
		if (!dma_map) {
			printk(KERN_ERR "sn_pci_map_sg: Unable to allocate "
			       "anymore 32 bit page map entries.\n");
			/*
			 * We will need to free all previously allocated entries.
			 */
			if (i > 0) {
				sn_pci_unmap_sg(hwdev, saved_sg, i, direction);
			}
			return (0);
		}

		sg->dma_address = pcibr_dmamap_addr(dma_map, phys_addr, sg->length);
		sg->dma_length = sg->length;
		dma_map->bd_dma_addr = sg->dma_address;
	}

	return nents;

}

/**
 * sn_pci_unmap_sg - unmap a scatter-gather list
 * @hwdev: device to unmap
 * @sg: scatterlist to unmap
 * @nents: number of scatterlist entries
 * @direction: DMA direction
 *
 * Unmap a set of streaming mode DMA translations.  Again, cpu read rules
 * concerning calls here are the same as for pci_unmap_single() below.  Also
 * known as sn_pci_unmap_sg() by the IA64 machvec code.
 */
void
sn_pci_unmap_sg(struct pci_dev *hwdev, struct scatterlist *sg, int nents, int direction)
{
	int i;
	struct pcibr_dmamap_s *dma_map;

	/* can't go anywhere w/o a direction in life */
	if (direction == PCI_DMA_NONE)
		BUG();

	for (i = 0; i < nents; i++, sg++){

		if (IS_PCI32_MAPPED(sg->dma_address)) {
                	dma_map = find_sn_dma_map(sg->dma_address, hwdev->bus->number);
        		if (dma_map) {
                		pcibr_dmamap_done(dma_map);
                		pcibr_dmamap_free(dma_map);
                		dma_map->bd_dma_addr = 0;
			}
        	}

		sg->dma_address = (dma_addr_t)NULL;
		sg->dma_length = 0;
	}
}

/**
 * sn_pci_map_single - map a single region for DMA
 * @hwdev: device to map for
 * @ptr: kernel virtual address of the region to map
 * @size: size of the region
 * @direction: DMA direction
 *
 * Map the region pointed to by @ptr for DMA and return the
 * DMA address.   Also known as platform_pci_map_single() by
 * the IA64 machvec code.
 *
 * We map this to the one step pcibr_dmamap_trans interface rather than
 * the two step pciio_dmamap_alloc/pciio_dmamap_addr because we have
 * no way of saving the dmamap handle from the alloc to later free
 * (which is pretty much unacceptable).
 *
 * TODO: simplify our interface;
 *       get rid of dev_desc and vhdl (seems redundant given a pci_dev);
 *       figure out how to save dmamap handle so can use two step.
 */
dma_addr_t
sn_pci_map_single(struct pci_dev *hwdev, void *ptr, size_t size, int direction)
{
	vertex_hdl_t vhdl;
	dma_addr_t dma_addr;
	unsigned long phys_addr;
	struct sn_device_sysdata *device_sysdata;
	pcibr_dmamap_t dma_map = NULL;

	if (direction == PCI_DMA_NONE)
		BUG();

	/* SN cannot support DMA addresses smaller than 32 bits. */
	if (IS_PCI32L(hwdev))
		return 0;

	/*
	 * find vertex for the device
	 */
	device_sysdata = (struct sn_device_sysdata *)hwdev->sysdata;
	vhdl = device_sysdata->vhdl;

	/*
	 * Call our dmamap interface
	 */
	dma_addr = 0;
	phys_addr = __pa(ptr);

	if (IS_PCIA64(hwdev)) {
		/* This device supports 64 bit DMA addresses. */
		dma_addr = pcibr_dmatrans_addr(vhdl, NULL, phys_addr, size,
		       ((IS_PIC_DEVICE(hwdev)) ? 0 : PCIIO_BYTE_STREAM) |
					       PCIIO_DMA_DATA |
					       PCIIO_DMA_A64);
		return dma_addr;
	}

	/*
	 * Devices that support 32 bit to 63 bit DMA addresses get
	 * 32 bit DMA addresses.
	 *
	 * First try to get a 32 bit direct map register.
	 */
	if (IS_PCI32G(hwdev)) {
		dma_addr = pcibr_dmatrans_addr(vhdl, NULL, phys_addr, size,
			((IS_PIC_DEVICE(hwdev)) ? 0 : PCIIO_BYTE_STREAM) |
					       PCIIO_DMA_DATA);
		if (dma_addr)
			return dma_addr;
	}

	/*
	 * It's a 32 bit card and we cannot do direct mapping so
	 * let's use the PMU instead.
	 */
	dma_map = NULL;
	dma_map = pcibr_dmamap_alloc(vhdl, NULL, size, 
			((IS_PIC_DEVICE(hwdev)) ? 0 : PCIIO_BYTE_STREAM) |
			PCIIO_DMA_DATA);

	if (!dma_map) {
		printk(KERN_ERR "pci_map_single: Unable to allocate anymore "
		       "32 bit page map entries.\n");
		return 0;
	}

	dma_addr = (dma_addr_t) pcibr_dmamap_addr(dma_map, phys_addr, size);
	dma_map->bd_dma_addr = dma_addr;

	return ((dma_addr_t)dma_addr);
}

/**
 * sn_pci_unmap_single - unmap a region used for DMA
 * @hwdev: device to unmap
 * @dma_addr: DMA address to unmap
 * @size: size of region
 * @direction: DMA direction
 *
 * Unmaps the region pointed to by @dma_addr.  Also known as
 * platform_pci_unmap_single() by the IA64 machvec code.
 */
void
sn_pci_unmap_single(struct pci_dev *hwdev, dma_addr_t dma_addr, size_t size, int direction)
{
	struct pcibr_dmamap_s *dma_map = NULL;

        if (direction == PCI_DMA_NONE)
		BUG();

	/*
	 * Get the sn_dma_map entry.
	 */
	if (IS_PCI32_MAPPED(dma_addr))
		dma_map = find_sn_dma_map(dma_addr, hwdev->bus->number);

	/*
	 * and free it if necessary...
	 */
	if (dma_map) {
		pcibr_dmamap_done(dma_map);
		pcibr_dmamap_free(dma_map);
		dma_map->bd_dma_addr = 0;
	}
}

/**
 * sn_pci_dma_sync_single - make sure all DMAs have completed
 * @hwdev: device to sync
 * @dma_handle: DMA address to sync
 * @size: size of region
 * @direction: DMA direction
 *
 * This routine is supposed to sync the DMA region specified
 * by @dma_handle into the 'coherence domain'.  We do not need to do 
 * anything on our platform.
 */
void
sn_pci_dma_sync_single(struct pci_dev *hwdev, dma_addr_t dma_handle, size_t size, int direction)
{
	return;

}

/**
 * sn_pci_dma_sync_sg - make sure all DMAs have completed
 * @hwdev: device to sync
 * @sg: scatterlist to sync
 * @nents: number of entries in the scatterlist
 * @direction: DMA direction
 *
 * This routine is supposed to sync the DMA regions specified
 * by @sg into the 'coherence domain'.  We do not need to do anything 
 * on our platform.
 */
void
sn_pci_dma_sync_sg(struct pci_dev *hwdev, struct scatterlist *sg, int nents, int direction)
{
	return;

}

/**
 * sn_dma_supported - test a DMA mask
 * @hwdev: device to test
 * @mask: DMA mask to test
 *
 * Return whether the given PCI device DMA address mask can be supported
 * properly.  For example, if your device can only drive the low 24-bits
 * during PCI bus mastering, then you would pass 0x00ffffff as the mask to
 * this function.  Of course, SN only supports devices that have 32 or more
 * address bits when using the PMU.  We could theoretically support <32 bit
 * cards using direct mapping, but we'll worry about that later--on the off
 * chance that someone actually wants to use such a card.
 */
int
sn_pci_dma_supported(struct pci_dev *hwdev, u64 mask)
{
	if (mask < 0xffffffff)
		return 0;
	return 1;
}

/*
 * New generic DMA routines just wrap sn2 PCI routines until we
 * support other bus types (if ever).
 */

int
sn_dma_supported(struct device *dev, u64 mask)
{
	BUG_ON(dev->bus != &pci_bus_type);

	return sn_pci_dma_supported(to_pci_dev(dev), mask);
}
EXPORT_SYMBOL(sn_dma_supported);

int
sn_dma_set_mask(struct device *dev, u64 dma_mask)
{
	BUG_ON(dev->bus != &pci_bus_type);

	if (!sn_dma_supported(dev, dma_mask))
		return 0;

	*dev->dma_mask = dma_mask;
	return 1;
}
EXPORT_SYMBOL(sn_dma_set_mask);

void *
sn_dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *dma_handle,
		   int flag)
{
	BUG_ON(dev->bus != &pci_bus_type);

	return sn_pci_alloc_consistent(to_pci_dev(dev), size, dma_handle);
}
EXPORT_SYMBOL(sn_dma_alloc_coherent);

void
sn_dma_free_coherent(struct device *dev, size_t size, void *cpu_addr,
		    dma_addr_t dma_handle)
{
	BUG_ON(dev->bus != &pci_bus_type);

	sn_pci_free_consistent(to_pci_dev(dev), size, cpu_addr, dma_handle);
}
EXPORT_SYMBOL(sn_dma_free_coherent);

dma_addr_t
sn_dma_map_single(struct device *dev, void *cpu_addr, size_t size,
	       int direction)
{
	BUG_ON(dev->bus != &pci_bus_type);

	return sn_pci_map_single(to_pci_dev(dev), cpu_addr, size, (int)direction);
}
EXPORT_SYMBOL(sn_dma_map_single);

void
sn_dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size,
		 int direction)
{
	BUG_ON(dev->bus != &pci_bus_type);

	sn_pci_unmap_single(to_pci_dev(dev), dma_addr, size, (int)direction);
}
EXPORT_SYMBOL(sn_dma_unmap_single);

dma_addr_t
sn_dma_map_page(struct device *dev, struct page *page,
	     unsigned long offset, size_t size,
	     int direction)
{
	BUG_ON(dev->bus != &pci_bus_type);

	return pci_map_page(to_pci_dev(dev), page, offset, size, (int)direction);
}
EXPORT_SYMBOL(sn_dma_map_page);

void
sn_dma_unmap_page(struct device *dev, dma_addr_t dma_address, size_t size,
	       int direction)
{
	BUG_ON(dev->bus != &pci_bus_type);

	pci_unmap_page(to_pci_dev(dev), dma_address, size, (int)direction);
}
EXPORT_SYMBOL(sn_dma_unmap_page);

int
sn_dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
	   int direction)
{
	BUG_ON(dev->bus != &pci_bus_type);

	return sn_pci_map_sg(to_pci_dev(dev), sg, nents, (int)direction);
}
EXPORT_SYMBOL(sn_dma_map_sg);

void
sn_dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nhwentries,
	     int direction)
{
	BUG_ON(dev->bus != &pci_bus_type);

	sn_pci_unmap_sg(to_pci_dev(dev), sg, nhwentries, (int)direction);
}
EXPORT_SYMBOL(sn_dma_unmap_sg);

void
sn_dma_sync_single(struct device *dev, dma_addr_t dma_handle, size_t size,
		int direction)
{
	BUG_ON(dev->bus != &pci_bus_type);

	sn_pci_dma_sync_single(to_pci_dev(dev), dma_handle, size, (int)direction);
}
EXPORT_SYMBOL(sn_dma_sync_single);

void
sn_dma_sync_sg(struct device *dev, struct scatterlist *sg, int nelems,
	    int direction)
{
	BUG_ON(dev->bus != &pci_bus_type);

	sn_pci_dma_sync_sg(to_pci_dev(dev), sg, nelems, (int)direction);
}
EXPORT_SYMBOL(sn_dma_sync_sg);

EXPORT_SYMBOL(sn_pci_unmap_single);
EXPORT_SYMBOL(sn_pci_map_single);
EXPORT_SYMBOL(sn_pci_dma_sync_single);
EXPORT_SYMBOL(sn_pci_map_sg);
EXPORT_SYMBOL(sn_pci_unmap_sg);
EXPORT_SYMBOL(sn_pci_alloc_consistent);
EXPORT_SYMBOL(sn_pci_free_consistent);
EXPORT_SYMBOL(sn_pci_dma_supported);