Since not all registers need to be cached and the cache is entirely
optional anyway we shouldn't be checking that a register is in the
cached range. If the register is invalid then the actual I/O code
can determine that and report an error.

Similarly, the step size can and should be enforced by the lower level
code if it's important.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>