• Bartlomiej Zolnierkiewicz's avatar
    pdc202xx_old: rewrite mode programming code (v2) · 4fce3164
    Bartlomiej Zolnierkiewicz authored
    This patch is based on the documentation (I would like to thank Promise
    for it) and also partially on the older vendor driver.
    
    Rewrite mode programming code:
    
    * disable 66MHz clock in pdc202xx_tune_chipset() so it is correctly disabled
      even if both devices on the channel are not DMA capable and after reset
    
    * enable/disable IORDY and PREFETCH bits in pdc202xx_tune_chipset()
      as they need to be setup correctly also for PIO only devices, plus IORDY
      wasn't disabled for non-IORDY devices and PREFETCH wasn't disabled for
      ATAPI devices
    
    * remove dead code for setting SYNC_ERDDY_EN bits from config_chipset_for_dma()
      (driver sets ->autotune to 1 so PIO modes are always programmed => lower
       nibble of register A never equals 4 => "chipset_is_set" is always true)
    
    * enable PIO mode programming for all ATAPI devices
      (it was limited to ->media == ide_cdrom devices)
    
    * remove extra reads of registers A/B/C, don't read register D et all
    
    * do clearing / programming of registers A/B/C in one go
      (gets rid of extra PCI config space read/write cycle)
    
    * set initial values of drive_conf/AP/BP/CP variables to zero
      (paranoia for the case when PCI reads fail)
    
    * remove XFER_UDMA6 to XFER_UDMA5 remapping case - it can't happen
      (ide_rate_filter() takes care of it)
    
    * fix XFER_MW_DMA0 timings (they were overclocked, use the official ones)
    
    * fix bitmasks for clearing bits of register B:
    
      - when programming DMA mode bit 0x10 of register B was cleared which
        resulted in overclocked PIO timing setting (iff PIO0 was used)
    
      - when programming PIO mode bits 0x18 weren't cleared so suboptimal
        timings were used for PIO1-4 if PIO0 was previously set (bit 0x10)
        and for PIO0/3/4 if PIO1/2 was previously set (bit 0x08)
    
    * add FIXME comment about missing locking for 66MHz clock register
    
    Also while at it:
    
    * remove unused defines
    
    * do a few cosmetic / CodingStyle fixes
    
    * bump driver version
    
    v2:
    * in pdc202xx_tune_chipset() the old content of drive configuration
      registers is used only by the debugging code so cover "drive_conf"
      PCI registers read by #if PDC202XX_DEBUG_DRIVE_INFO
      (Noticed by Sergei Shtylyov)
    Signed-off-by: default avatarBartlomiej Zolnierkiewicz <bzolnier@gmail.com>
    4fce3164
pdc202xx_old.c 15.3 KB