• Ralf Baechle's avatar
    [MIPS] Handle R4000/R4400 mfc0 from count register. · 5aa85c9f
    Ralf Baechle authored
    The R4000 and R4400 have an errata where if the cp0 count register is read
    in the exact moment when it matches the compare register no interrupt will
    be generated.
    
    This bug may be triggered if the cp0 count register is being used as
    clocksource and the compare interrupt as clockevent.  So a simple
    workaround is to avoid using the compare for both facilities on the
    affected CPUs.
    
    This is different from the workaround suggested in the old errata documents;
    at some opportunity probably the official version should be implemented
    and tested.  Another thing to find out is which processor versions
    exactly are affected.  I only have errata documents upto R4400 V3.0
    available so for the moment the code treats all R4000 and R4400 as broken.
    
    This is potencially a problem for some machines that have no other decent
    clocksource available; this workaround will cause them to fall back to
    another clocksource, worst case the "jiffies" source.
    5aa85c9f
cevt-r4k.c 6.69 KB