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Angus Clark authored
This patch refactors the fsm_read_status() and fsm_write_status() code to support 1 or 2 byte operations, with a specified command. This allows us to remove device/register specific code, such as the N25Q fsm_wrvcr() function. The 'QE' configuration code is updated accordingly, with minor tweaks to ensure the register values are only written if actually required. One notable change in this area is that the 'W25Q_STATUS_QE' bit-field is now defined with respect to the 'SR2' register, rather than the combined 'SR1+SR2' register which is only used for write operations. Signed-off-by:
Angus Clark <angus.clark@st.com> Signed-off-by:
Lee Jones <lee.jones@linaro.org> Signed-off-by:
Brian Norris <computersforpeace@gmail.com>
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