• Shanker Donthineni's avatar
    irqchip/gic-v3: Add support for Range Selector (RS) feature · eda0d04a
    Shanker Donthineni authored
    A new feature Range Selector (RS) has been added to GIC specification
    in order to support more than 16 CPUs at affinity level 0. New fields
    are introduced in SGI system registers (ICC_SGI0R_EL1, ICC_SGI1R_EL1
    and ICC_ASGI1R_EL1) to relax an artificial limit of 16 at level 0.
    
    - A new RSS field in ICC_CTLR_EL3, ICC_CTLR_EL1 and ICV_CTLR_EL1:
      [18] - Range Selector Support (RSS)
      0b0 = Targeted SGIs with affinity level 0 values of 0-15 are supported.
      0b1 = Targeted SGIs with affinity level 0 values of 0-255 are supported.
    
    - A new RS field in ICC_SGI0R_EL1, ICC_SGI1R_EL1 and ICC_ASGI1R_EL1:
      [47:44] - RangeSelector (RS) which group of 16 TargetList[n] field
                TargetList[n] represents aff0 value ((RS*16)+n)
                When ICC_CTLR_EL3.RSS==0 or ICC_CTLR_EL1.RSS==0, RS is RES0.
    
    - A new RSS field in GICD_TYPER:
      [26] - Range Selector Support (RSS)
      0b0 = Targeted SGIs with affinity level 0 values of 0-15 are supported.
      0b1 = Targeted SGIs with affinity level 0 values of 0-255 are supported.
    Signed-off-by: default avatarShanker Donthineni <shankerd@codeaurora.org>
    Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
    eda0d04a
arch_gicv3.h 3.44 KB