• Jerome Brunet's avatar
    clk: meson: add axg misc bit to the mpll driver · 6c00e7b7
    Jerome Brunet authored
    On axg, the rate of the mpll is stuck as if sdm value was 4 and could not
    change (expect for mpll2 strangely). Looking at the vendor kernel, it
    turns out a new magic bit from the undocumented HHI_PLL_TOP_MISC register
    is required.
    
    Setting this bit solves the problem and the mpll rates are back to normal
    
    Fixes: 78b4af31 ("clk: meson-axg: add clock controller drivers")
    Signed-off-by: default avatarJerome Brunet <jbrunet@baylibre.com>
    6c00e7b7
clkc.h 3.87 KB