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    doc: Add doc for the Ingenic TCU hardware · 97689a1a
    Paul Cercueil authored
    Add documentation about the Timer/Counter Unit (TCU) present in the
    Ingenic JZ47xx SoCs.
    
    The Timer/Counter Unit (TCU) in Ingenic JZ47xx SoCs is a multi-function
    hardware block. It features up to to eight channels, that can be used as
    counters, timers, or PWM.
    
    - JZ4725B, JZ4750, JZ4755 only have six TCU channels. The other SoCs all
      have eight channels.
    
    - JZ4725B introduced a separate channel, called Operating System Timer
      (OST). It is a 32-bit programmable timer. On JZ4770 and above, it is
      64-bit.
    
    - Each one of the TCU channels has its own clock, which can be reparented
      to three different clocks (pclk, ext, rtc), gated, and reclocked, through
      their TCSR register.
      * The watchdog and OST hardware blocks also feature a TCSR register with
        the same format in their register space.
      * The TCU registers used to gate/ungate can also gate/ungate the watchdog
        and OST clocks.
    
    - Each TCU channel works in one of two modes:
      * mode TCU1: channels cannot work in sleep mode, but are easier to
        operate.
      * mode TCU2: channels can work in sleep mode, but the operation is a bit
        more complicated than with TCU1 channels.
    
    - The mode of each TCU channel depends on the SoC used:
      * On the oldest SoCs (up to JZ4740), all of the eight channels operate in
        TCU1 mode.
      * On JZ4725B, channel 5 operates as TCU2, the others operate as TCU1.
      * On newest SoCs (JZ4750 and above), channels 1-2 operate as TCU2, the
        others operate as TCU1.
    
    - Each channel can generate an interrupt. Some channels share an interrupt
      line, some don't, and this changes between SoC versions:
      * on older SoCs (JZ4740 and below), channel 0 and channel 1 have their
        own interrupt line; channels 2-7 share the last interrupt line.
      * On JZ4725B, channel 0 has its own interrupt; channels 1-5 share one
        interrupt line; the OST uses the last interrupt line.
      * on newer SoCs (JZ4750 and above), channel 5 has its own interrupt;
        channels 0-4 and (if eight channels) 6-7 all share one interrupt line;
        the OST uses the last interrupt line.
    Signed-off-by: default avatarPaul Cercueil <paul@crapouillou.net>
    Tested-by: default avatarMathieu Malaterre <malat@debian.org>
    Tested-by: default avatarArtur Rojek <contact@artur-rojek.eu>
    Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
    Cc: Ralf Baechle <ralf@linux-mips.org>
    Cc: James Hogan <jhogan@kernel.org>
    Cc: Jonathan Corbet <corbet@lwn.net>
    Cc: Lee Jones <lee.jones@linaro.org>
    Cc: Arnd Bergmann <arnd@arndb.de>
    Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
    Cc: Thomas Gleixner <tglx@linutronix.de>
    Cc: Michael Turquette <mturquette@baylibre.com>
    Cc: Stephen Boyd <sboyd@kernel.org>
    Cc: Jason Cooper <jason@lakedaemon.net>
    Cc: Marc Zyngier <marc.zyngier@arm.com>
    Cc: Rob Herring <robh+dt@kernel.org>
    Cc: Mark Rutland <mark.rutland@arm.com>
    Cc: devicetree@vger.kernel.org
    Cc: linux-kernel@vger.kernel.org
    Cc: linux-doc@vger.kernel.org
    Cc: linux-mips@vger.kernel.org
    Cc: linux-clk@vger.kernel.org
    Cc: od@zcrc.me
    97689a1a
ingenic-tcu.rst 2.89 KB