• Linus Torvalds's avatar
    Merge branch 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip · 78f86013
    Linus Torvalds authored
    Pull irq updates from Thomas Gleixner:
     "The interrupt departement delivers this time:
    
       - New infrastructure to manage NMIs on platforms which have a sane
         NMI delivery, i.e. identifiable NMI vectors instead of a single
         lump.
    
       - Simplification of the interrupt affinity management so drivers
         don't have to implement ugly loops around the PCI/MSI enablement.
    
       - Speedup for interrupt statistics in /proc/stat
    
       - Provide a function to retrieve the default irq domain
    
       - A new interrupt controller for the Loongson LS1X platform
    
       - Affinity support for the SiFive PLIC
    
       - Better support for the iMX irqsteer driver
    
       - NUMA aware memory allocations for GICv3
    
       - The usual small fixes, improvements and cleanups all over the
         place"
    
    * 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (36 commits)
      irqchip/imx-irqsteer: Add multi output interrupts support
      irqchip/imx-irqsteer: Change to use reg_num instead of irq_group
      dt-bindings: irq: imx-irqsteer: Add multi output interrupts support
      dt-binding: irq: imx-irqsteer: Use irq number instead of group number
      irqchip/brcmstb-l2: Use _irqsave locking variants in non-interrupt code
      irqchip/gicv3-its: Use NUMA aware memory allocation for ITS tables
      irqdomain: Allow the default irq domain to be retrieved
      irqchip/sifive-plic: Implement irq_set_affinity() for SMP host
      irqchip/sifive-plic: Differentiate between PLIC handler and context
      irqchip/sifive-plic: Add warning in plic_init() if handler already present
      irqchip/sifive-plic: Pre-compute context hart base and enable base
      PCI/MSI: Remove obsolete sanity checks for multiple interrupt sets
      genirq/affinity: Remove the leftovers of the original set support
      nvme-pci: Simplify interrupt allocation
      genirq/affinity: Add new callback for (re)calculating interrupt sets
      genirq/affinity: Store interrupt sets size in struct irq_affinity
      genirq/affinity: Code consolidation
      irqchip/irq-sifive-plic: Check and continue in case of an invalid cpuid.
      irqchip/i8259: Fix shutdown order by moving syscore_ops registration
      dt-bindings: interrupt-controller: loongson ls1x intc
      ...
    78f86013
irq-gic-v3-its.c 97.9 KB