• Maciej W. Rozycki's avatar
    MIPS: Tell R4k SC and MC variations apart · 7f177a52
    Maciej W. Rozycki authored
    There is no reliable way to tell R4000/R4400 SC and MC variations apart,
    however simple heuristic should give good results.  Only the MC version
    supports coherent caching so we can rely on such a mode having been set
    for KSEG0 by the power-on firmware to reliably indicate an MC processor.
    SC processors reportedly hang on coherent cached memory accesses and Linux
    is linked to a cached load address so the firmware has to use the correct
    caching mode to download the kernel image in a cached mode successfully.
    
    OTOH if the firmware chooses to use either the non-coherent cached or the
    uncached mode for KSEG0 on an MC processor, then the SC variant will be
    reported, just as we currently do, so no regression here.
    Signed-off-by: default avatarMaciej W. Rozycki <macro@linux-mips.org>
    Cc: Jonas Gorski <jogo@openwrt.org>
    Cc: MIPS Mailing List <linux-mips@linux-mips.org>
    Patchwork: https://patchwork.linux-mips.org/patch/5882/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
    7f177a52
cpu-probe.c 26.2 KB