• Paul Mundt's avatar
    sh: Support for extended ASIDs on PTEAEX-capable SH-X3 cores. · 8263a67e
    Paul Mundt authored
    This adds support for extended ASIDs (up to 16-bits) on newer SH-X3 cores
    that implement the PTAEX register and respective functionality. Presently
    only the 65nm SH7786 (90nm only supports legacy 8-bit ASIDs).
    
    The main change is in how the PTE is written out when loading the entry
    in to the TLB, as well as in how the TLB entry is selectively flushed.
    
    While SH-X2 extended mode splits out the memory-mapped U and I-TLB data
    arrays for extra bits, extended ASID mode splits out the address arrays.
    While we don't use the memory-mapped data array access, the address
    array accesses are necessary for selective TLB flushes, so these are
    implemented newly and replace the generic SH-4 implementation.
    
    With this, TLB flushes in switch_mm() are almost non-existent on newer
    parts.
    Signed-off-by: default avatarPaul Mundt <lethal@linux-sh.org>
    8263a67e
mmu_context.h 4.54 KB