• Bhaskar Upadhaya's avatar
    arm64: dts: Add support for NXP LS1028A SoC · 8897f325
    Bhaskar Upadhaya authored
    LS1028A contains two ARM v8 CortexA72 processor cores
    with 32 KB L1-D cache and 48 KB L1-I cache
    
    Features summary
     Two 32-bit / 64-bit ARM v8 Cortex-A72 CPUs
      - Arranged as single clusters of two cores sharing a 1 MB L2 cache
      - Speed Up to 1.3 GHz
      - Support for cluster power-gating.
     Cache coherent interconnect (CCI-400)
      - Hardware-managed data coherency
      - Up to 400 MHz
     32-bit DDR4 SDRAM memory controller with ECC
     Two PCIe 3.0 controllers
     One serial ATA (SATA 3.0) controller
     Two high-speed USB 3.0 controllers with integrated PHY
    
     Following levels of DTSI/DTS files have been created for the LS1028A
      SoC family:
    
             - fsl-ls1028a.dtsi:
                     DTS-Include file for NXP LS1028A SoC.
    
             - fsl-ls1028a-qds.dts:
                     DTS file for NXP LS1028A QDS board.
    
             - fsl-ls1028a-rdb.dts:
                     DTS file for NXP LS1028A RDB board
    Signed-off-by: default avatarSudhanshu Gupta <sudhanshu.gupta@nxp.com>
    Signed-off-by: default avatarRai Harninder <harninder.rai@nxp.com>
    Signed-off-by: default avatarBhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
    Acked-by: default avatarLi Yang <leoyang.li@nxp.com>
    Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
    8897f325
fsl-ls1028a-rdb.dts 1.01 KB