Update D0 <-> D3 sequence to correctly transition hardware and DSP core
from and to D3. On top of that, set SHIM registers to their recommended
defaults during D0 and D3 proceduces as HW does not reset registers for
us.

Connected to:
[alsa-devel][BUG] bdw-rt5650 DSP boot timeout
https://mailman.alsa-project.org/pipermail/alsa-devel/2019-July/153098.html

Github issue ticket reference:
https://github.com/thesofproject/linux/pull/1842

Tested on:
- BDW-Y RVP with rt286
- SAMUS with rt5677

Proposed solution (both in July 2019 and on github):
'Revert "ASoC: Intel: Work around to fix HW d3 potential crash issue"'
is NAKed as it only covers the problem up and actually brings back the
undefined behavior: some registers (e.g.: APLLSE) are describing LPT
offsets rather than WPT ones. In consequence, during power-transitions
driver issues incorrect writes and leaves the regs of interest alone.

Existing patch - the non-revert - does not resolve the HW D3 issue at
all as it ignores the recommended sequence and does not initialize
hardware registers as expected. And thus, leaving things as are is also
unacceptable.
Signed-off-by: Cezary Rojewski <cezary.rojewski@intel.com>
Tested-by: Ross Zwisler <zwisler@google.com>
Link: https://lore.kernel.org/r/20200330194520.13253-1-cezary.rojewski@intel.comSigned-off-by: Mark Brown <broonie@kernel.org>