• Matt Fleming's avatar
    sh: Definitions for 3-level page table layout · 5d9b4b19
    Matt Fleming authored
    If using 64-bit PTEs and 4K pages then each page table has 512 entries
    (as opposed to 1024 entries with 32-bit PTEs). Unlike MIPS, SH follows
    the convention that all structures in the page table (pgd_t, pmd_t,
    pgprot_t, etc) must be the same size. Therefore, 64-bit PTEs require
    64-bit PGD entries, etc. Using 2-levels of page tables and 64-bit PTEs
    it is only possible to map 1GB of virtual address space.
    
    In order to map all 4GB of virtual address space we need to adopt a
    3-level page table layout. This actually works out better for
    CONFIG_SUPERH32 because we only waste 2 PGD entries on the P1 and P2
    areas (which are untranslated) instead of 256.
    Signed-off-by: default avatarMatt Fleming <matt@console-pimps.org>
    Signed-off-by: default avatarPaul Mundt <lethal@linux-sh.org>
    5d9b4b19
pgalloc_pmd.h 859 Bytes