• Thomas Petazzoni's avatar
    ARM: 8076/1: mm: add support for HW coherent systems in PL310 cache · 98ea2dba
    Thomas Petazzoni authored
    When a PL310 cache is used on a system that provides hardware
    coherency, the outer cache sync operation is useless, and can be
    skipped. Moreover, on some systems, it is harmful as it causes
    deadlocks between the Marvell coherency mechanism, the Marvell PCIe
    controller and the Cortex-A9.
    
    To avoid this, this commit introduces a new Device Tree property
    'arm,io-coherent' for the L2 cache controller node, valid only for the
    PL310 cache. It identifies the usage of the PL310 cache in an I/O
    coherent configuration. Internally, it makes the driver disable the
    outer cache sync operation.
    
    Note that technically speaking, a fully coherent system wouldn't
    require any of the other .outer_cache operations. However, in
    practice, when booting secondary CPUs, these are not yet coherent, and
    therefore a set of cache maintenance operations are necessary at this
    point. This explains why we keep the other .outer_cache operations and
    only ->sync is disabled.
    
    While in theory any write to a PL310 register could cause the
    deadlock, in practice, disabling ->sync is sufficient to workaround
    the deadlock, since the other cache maintenance operations are only
    used in very specific situations.
    
    Contrary to previous versions of this patch, this new version does not
    simply NULL-ify the ->sync member, because the l2c_init_data
    structures are now 'const' and therefore cannot be modified, which is
    a good thing. Therefore, this patch introduces a separate
    l2c_init_data instance, called of_l2c310_coherent_data.
    Signed-off-by: default avatarThomas Petazzoni <thomas.petazzoni@free-electrons.com>
    Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
    98ea2dba
cache-l2x0.c 41.5 KB