• Kan Liang's avatar
    perf/x86/intel/uncore: Add enable_box for client MSR uncore · 95f3be79
    Kan Liang authored
    There are bug reports about miscounting uncore counters on some
    client machines like Sandybridge, Broadwell and Skylake. It is
    very likely to be observed on idle systems.
    
    This issue is caused by a hardware issue. PERF_GLOBAL_CTL could be
    cleared after Package C7, and nothing will be count.
    The related errata (HSD 158) could be found in:
    
      www.intel.com/content/dam/www/public/us/en/documents/specification-updates/4th-gen-core-family-desktop-specification-update.pdf
    
    This patch tries to work around this issue by re-enabling PERF_GLOBAL_CTL
    in ->enable_box(). The workaround does not cover all cases. It helps for new
    events after returning from C7. But it cannot prevent C7, it will still
    miscount if a counter is already active.
    
    There is no drawback in leaving it enabled, so it does not need
    disable_box() here.
    Signed-off-by: default avatarKan Liang <kan.liang@intel.com>
    Cc: <stable@vger.kernel.org>
    Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
    Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
    Cc: Jiri Olsa <jolsa@redhat.com>
    Cc: Linus Torvalds <torvalds@linux-foundation.org>
    Cc: Peter Zijlstra <peterz@infradead.org>
    Cc: Stephane Eranian <eranian@google.com>
    Cc: Thomas Gleixner <tglx@linutronix.de>
    Cc: Vince Weaver <vincent.weaver@maine.edu>
    Link: http://lkml.kernel.org/r/1470925874-59943-1-git-send-email-kan.liang@intel.comSigned-off-by: default avatarIngo Molnar <mingo@kernel.org>
    95f3be79
uncore_snb.c 21.7 KB