• Santosh Shilimkar's avatar
    ARM: OMAP4: Fix errata i688 with MPU interconnect barriers. · 137d105d
    Santosh Shilimkar authored
    On OMAP4 SOC, intecronnects has many write buffers in the async bridges
    and they need to be drained before CPU enters into standby state.
    
    Patch 'OMAP4: PM: Add CPUX OFF mode support' added CPU PM support
    but OMAP errata i688 (Async Bridge Corruption) needs to be taken
    care to avoid issues like system freeze, CPU deadlocks, random
    crashes with register accesses, synchronisation loss on initiators
    operating on both interconnect port simultaneously.
    
    As per the errata, if a data is stalled inside asynchronous bridge
    because of back pressure, it may be accepted multiple times, creating
    pointer misalignment that will corrupt next transfers on that data
    path until next reset of the system (No recovery procedure once
    the issue is hit, the path remains consistently broken).
    Async bridge can be found on path between MPU to EMIF and
    MPU to L3 interconnect. This situation can happen only when the
    idle is initiated by a Master Request Disconnection (which is
    trigged by software when executing WFI on CPU).
    
    The work-around for this errata needs all the initiators
    connected through async bridge must ensure that data path
    is properly drained before issuing WFI. This condition will be
    met if one Strongly ordered access is performed to the
    target right before executing the WFI. In MPU case, L3 T2ASYNC
    FIFO and DDR T2ASYNC FIFO needs to be drained. IO barrier ensure
    that there is no synchronisation loss on initiators operating
    on both interconnect port simultaneously.
    
    Thanks to Russell for a tip to conver assembly function to
    C fuction there by reducing 40 odd lines of code from the patch.
    Signed-off-by: default avatarSantosh Shilimkar <santosh.shilimkar@ti.com>
    Signed-off-by: default avatarRichard Woodruff <r-woodruff2@ti.com>
    Acked-by: default avatarJean Pihet <j-pihet@ti.com>
    Reviewed-by: default avatarKevin Hilman <khilman@ti.com>
    Tested-by: default avatarVishwanath BS <vishwanath.bs@ti.com>
    Signed-off-by: default avatarKevin Hilman <khilman@ti.com>
    137d105d
barriers.h 1.03 KB