• Bjorn Andersson's avatar
    drm/msm: Trigger fence completion from GPU · 79d57bf6
    Bjorn Andersson authored
    Interrupt commands causes the CP to trigger an interrupt as the command
    is processed, regardless of the GPU being done processing previous
    commands. This is seen by the interrupt being delivered before the
    fence is written on 8974 and is likely the cause of the additional
    CP_WAIT_FOR_IDLE workaround found for a306, which would cause the CP to
    wait for the GPU to go idle before triggering the interrupt.
    
    Instead we can set the (undocumented) BIT(31) of the CACHE_FLUSH_TS
    which will cause a special CACHE_FLUSH_TS interrupt to be triggered from
    the GPU as the write event is processed.
    
    Add CACHE_FLUSH_TS to the IRQ masks of A3xx and A4xx and remove the
    workaround for A306.
    Suggested-by: default avatarJordan Crouse <jcrouse@codeaurora.org>
    Signed-off-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
    Signed-off-by: default avatarRob Clark <robdclark@gmail.com>
    79d57bf6
a4xx_gpu.c 19.3 KB