• Voon Weifeng's avatar
    net: stmmac: Enable SERDES power up/down sequence · b9663b7c
    Voon Weifeng authored
    This patch is to enable Intel SERDES power up/down sequence. The SERDES
    converts 8/10 bits data to SGMII signal. Below is an example of
    HW configuration for SGMII mode. The SERDES is located in the PHY IF
    in the diagram below.
    
    <-----------------GBE Controller---------->|<--External PHY chip-->
    +----------+         +----+            +---+           +----------+
    |   EQoS   | <-GMII->| DW | < ------ > |PHY| <-SGMII-> | External |
    |   MAC    |         |xPCS|            |IF |           | PHY      |
    +----------+         +----+            +---+           +----------+
           ^               ^                 ^                ^
           |               |                 |                |
           +---------------------MDIO-------------------------+
    
    PHY IF configuration and status registers are accessible through
    mdio address 0x15 which is defined as mdio_adhoc_addr. During D0,
    The driver will need to power up PHY IF by changing the power state
    to P0. Likewise, for D3, the driver sets PHY IF power state to P3.
    Signed-off-by: default avatarVoon Weifeng <weifeng.voon@intel.com>
    Signed-off-by: default avatarOng Boon Leong <boon.leong.ong@intel.com>
    Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
    b9663b7c
dwmac-intel.c 19.1 KB