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    perf/x86/intel: Limit to half counters when the HT workaround is enabled, to... · c02cdbf6
    Stephane Eranian authored
    perf/x86/intel: Limit to half counters when the HT workaround is enabled, to avoid exclusive mode starvation
    
    This patch limits the number of counters available to each CPU when
    the HT bug workaround is enabled.
    
    This is necessary to avoid situation of counter starvation. Such can
    arise from configuration where one HT thread, HT0, is using all 4 counters
    with corrupting events which require exclusion the the sibling HT, HT1.
    
    In such case, HT1 would not be able to schedule any event until HT0
    is done. To mitigate this problem, this patch artificially limits
    the number of counters to 2.
    
    That way, we can gurantee that at least 2 counters are not in exclusive
    mode and therefore allow the sibling thread to schedule events of the
    same type (system vs. per-thread). The 2 counters are not determined
    in advance. We simply set the limit to two events per HT.
    
    This helps mitigate starvation in case of events with specific counter
    constraints such a PREC_DIST.
    
    Note that this does not elimintate the starvation is all cases. But
    it is better than not having it.
    
    (Solution suggested by Peter Zjilstra.)
    Signed-off-by: default avatarStephane Eranian <eranian@google.com>
    Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
    Cc: bp@alien8.de
    Cc: jolsa@redhat.com
    Cc: kan.liang@intel.com
    Cc: maria.n.dimakopoulou@gmail.com
    Link: http://lkml.kernel.org/r/1416251225-17721-11-git-send-email-eranian@google.comSigned-off-by: default avatarIngo Molnar <mingo@kernel.org>
    c02cdbf6
perf_event.h 24.5 KB