1. All the memory barriers are SMP-only avoiding unnecessary overhead on UP.
2, My forward porting merge of the rt_rcu patch dropped two changes in
   rt_intern_hash() in around 2.5.43 that ordered the writes while
   inserting a dst entry at the start of a hash chain. The dst entry updates
   must be visible to other (weakly ordered) CPUs before it is inserted.
   The necessary smp_wmb()s are added.
3. Comments to go with the write ordering.