• Anup Patel's avatar
    irqchip: RISC-V per-HART local interrupt controller driver · 6b7ce892
    Anup Patel authored
    The RISC-V per-HART local interrupt controller manages software
    interrupts, timer interrupts, external interrupts (which are routed
    via the platform level interrupt controller) and other per-HART
    local interrupts.
    
    We add a driver for the RISC-V local interrupt controller, which
    eventually replaces the RISC-V architecture code, allowing for a
    better split between arch code and drivers.
    
    The driver is compliant with RISC-V Hart-Level Interrupt Controller
    DT bindings located at:
    Documentation/devicetree/bindings/interrupt-controller/riscv,cpu-intc.txt
    Co-developed-by: default avatarPalmer Dabbelt <palmer@dabbelt.com>
    Signed-off-by: default avatarAnup Patel <anup.patel@wdc.com>
    [Palmer: Cleaned up warnings]
    Signed-off-by: default avatarPalmer Dabbelt <palmer@dabbelt.com>
    6b7ce892
irq-sifive-plic.c 10 KB