• Imre Deak's avatar
    drm/i915/tgl: Make sure a semiplanar UV plane is tile row size aligned · d156135e
    Imre Deak authored
    Currently the GGTT offset of a UV plane in a semiplanar YUV FB is tile
    size (4kB) aligned. I noticed, that enforcing only this alignment leads
    oddly to random memory corruptions on TGL while scanning out Y-tiled
    FBs. This issue can be easily reproduced with a UV plane offset that is
    not aligned to the plane's tile row size.
    
    Some experiments showed the correct alignment to be tile row size
    indeed. This also makes sense, since the de-tiling fence created for the
    object - with its own stride and so "left" and "right" edge - applies to
    all the planes in the FB, so each tile row of all planes should be tile
    row aligned.
    
    In fact BSpec requires this alignment since SKL. On SKL we may enforce
    this due to the AUX plane x,y coords check, but on ICL and TGL we don't.
    For now enforce this only on TGL; I can follow up with any necessary
    change for ICL after more tests.
    
    BSpec requires a stricter alignment for linear UV planes too (kind of a
    tile row alignment), but it's unclear whether that's really needed
    (couldn't be explained with the de-tiling fence as above) and enforcing
    that could break existing user space; so avoid that too for now until
    more tests.
    
    v2:
    - Clarify the commit log wrt. the address space the alignment applies to.
      (Chris)
    
    Cc: Chris Wilson <chris@chris-wilson.co.uk>
    Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
    Signed-off-by: default avatarImre Deak <imre.deak@intel.com>
    Acked-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
    Reviewed-by: default avatarMika Kahola <mika.kahola@intel.com>
    Link: https://patchwork.freedesktop.org/patch/msgid/20191231233756.18753-3-imre.deak@intel.com
    d156135e
intel_display.c 525 KB