• Martin K. Petersen's avatar
    nvme: Quirks for PM1725 controllers · d554b5e1
    Martin K. Petersen authored
    PM1725 controllers have a couple of quirks that need to be handled in
    the driver:
    
     - I/O queue depth must be limited to 64 entries on controllers that do
       not report MQES.
    
     - The host interface registers go offline briefly while resetting the
       chip. Thus a delay is needed before checking whether the controller
       is ready.
    
    Note that the admin queue depth is also limited to 64 on older versions
    of this board. Since our NVME_AQ_DEPTH is now 32 that is no longer an
    issue.
    Signed-off-by: default avatarMartin K. Petersen <martin.petersen@oracle.com>
    Signed-off-by: default avatarSagi Grimberg <sagi@grimberg.me>
    d554b5e1
pci.c 63.3 KB