• Remi Pommarel's avatar
    clk: meson: pll: Fix by 0 division in __pll_params_to_rate() · d8488a41
    Remi Pommarel authored
    Some meson pll registers can be initialized with 0 as N value, introducing
    the following division by 0 when computing rate :
    
      UBSAN: Undefined behaviour in drivers/clk/meson/clk-pll.c:75:9
      division by zero
      CPU: 0 PID: 1 Comm: swapper/0 Not tainted 5.4.0-rc3-608075-g86c9af8630e1-dirty #400
      Call trace:
       dump_backtrace+0x0/0x1c0
       show_stack+0x14/0x20
       dump_stack+0xc4/0x100
       ubsan_epilogue+0x14/0x68
       __ubsan_handle_divrem_overflow+0x98/0xb8
       __pll_params_to_rate+0xdc/0x140
       meson_clk_pll_recalc_rate+0x278/0x3a0
       __clk_register+0x7c8/0xbb0
       devm_clk_hw_register+0x54/0xc0
       meson_eeclkc_probe+0xf4/0x1a0
       platform_drv_probe+0x54/0xd8
       really_probe+0x16c/0x438
       driver_probe_device+0xb0/0xf0
       device_driver_attach+0x94/0xa0
       __driver_attach+0x70/0x108
       bus_for_each_dev+0xd8/0x128
       driver_attach+0x30/0x40
       bus_add_driver+0x1b0/0x2d8
       driver_register+0xbc/0x1d0
       __platform_driver_register+0x78/0x88
       axg_driver_init+0x18/0x20
       do_one_initcall+0xc8/0x24c
       kernel_init_freeable+0x2b0/0x344
       kernel_init+0x10/0x128
       ret_from_fork+0x10/0x18
    
    This checks if N is null before doing the division.
    
    Fixes: 7a29a869 ("clk: meson: Add support for Meson clock controller")
    Reviewed-by: default avatarMartin Blumenstingl <martin.blumenstingl@googlemail.com>
    Signed-off-by: default avatarRemi Pommarel <repk@triplefau.lt>
    [jbrunet@baylibre.com: update the comment in above the fix]
    Signed-off-by: default avatarJerome Brunet <jbrunet@baylibre.com>
    d8488a41
clk-pll.c 11 KB