• Maciej W. Rozycki's avatar
    MIPS: DECstation HRT initialization rearrangement · daed1285
    Maciej W. Rozycki authored
    Not all I/O ASIC versions have the free-running counter implemented, an
    early revision used in the 5000/1xx models aka 3MIN and 4MIN did not have
    it.  Therefore we cannot unconditionally use it as a clock source.
    Fortunately if not implemented its register slot has a fixed value so it
    is enough if we check for the value at the end of the calibration period
    being the same as at the beginning.
    
    This also means we need to look for another high-precision clock source on
    the systems affected.  The 5000/1xx can have an R4000SC processor
    installed where the CP0 Count register can be used as a clock source.
    Unfortunately all the R4k DECstations suffer from the missed timer
    interrupt on CP0 Count reads erratum, so we cannot use the CP0 timer as a
    clock source and a clock event both at a time.  However we never need an
    R4k clock event device because all DECstations have a DS1287A RTC chip
    whose periodic interrupt can be used as a clock source.
    
    This gives us the following four configuration possibilities for I/O ASIC
    DECstations:
    
    1. No I/O ASIC counter and no CP0 timer, e.g. R3k 5000/1xx (3MIN).
    
    2. No I/O ASIC counter but the CP0 timer, i.e. R4k 5000/150 (4MIN).
    
    3. The I/O ASIC counter but no CP0 timer, e.g. R3k 5000/240 (3MAX+).
    
    4. The I/O ASIC counter and the CP0 timer, e.g. R4k 5000/260 (4MAX+).
    
    For #1 and #2 this change stops the I/O ASIC free-running counter from
    being installed as a clock source of a 0Hz frequency.  For #2 it also
    arranges for the CP0 timer to be used as a clock source rather than a
    clock event device, because having an accurate wall clock is more
    important than a high-precision interval timer.  For #3 there is no
    change.  For #4 the change makes the I/O ASIC free-running counter
    installed as a clock source so that the CP0 timer can be used as a clock
    event device.
    
    Unfortunately the use of the CP0 timer as a clock event device relies on a
    succesful completion of c0_compare_interrupt.  That never happens, because
    while waiting for a CP0 Compare interrupt to happen the function spins in
    a loop reading the CP0 Count register.  This makes the CP0 Count erratum
    trigger reliably causing the interrupt waited for to be lost in all cases.
    As a result #4 resorts to using the CP0 timer as a clock source as well,
    just as #2.  However we want to keep this separate arrangement in case
    (hope) c0_compare_interrupt is eventually rewritten such that it avoids
    the erratum.
    Signed-off-by: default avatarMaciej W. Rozycki <macro@linux-mips.org>
    Cc: linux-mips@linux-mips.org
    Patchwork: https://patchwork.linux-mips.org/patch/5825/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
    daed1285
ioasic.h 862 Bytes