• Andi Kleen's avatar
    [PATCH] x86_64: Update TSC sync algorithm · dda50e71
    Andi Kleen authored
    The new TSC sync algorithm recently submitted did not work too well.
    
    The result was that some MP machines where the TSC came up of the BIOS very
    unsynchronized and that did not have HPET support were nearly unusable because
    the time would jump forwards and backwards between CPUs.
    
    After a lot of research ;-) and some more prototypes I ended up with just
    using the one from IA64 which looks best.  It has some internal self tuning
    that should adapt to changing interconnect latencies.  It holds up in my tests
    so far.
    
    I believe it was originally written by David Mosberger, I just ported it over
    to x86-64.  See the inline comment for a description.
    
    This cleans up the code because it uses smp_call_function for syncing instead
    of having custom hooks in SMP bootup.
    
    Please note that the cycle numbers it outputs are too optimistic because they
    do not take into account the latency of WRMSR and RDTSC, which can be hundreds
    of cycles.  It seems to be able to sync a dual Opteron to 200-300 cycles,
    which is probably good enough.
    
    There is a timing window during AP bootup where interrupts can see
    inconsistent time before the TSC is synced.  It is hard to avoid unfortunately
    because we can only do the TSC sync after some setup, and we need to enable
    interrupts before that.  I just ignored it for now.
    Signed-off-by: default avatarAndi Kleen <ak@suse.de>
    Signed-off-by: default avatarAndrew Morton <akpm@osdl.org>
    Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
    dda50e71
smpboot.c 24.6 KB