The WM8994 can output a clock derived from its internal SYSCLK, called
OPCLK.  The rate can be selected as a sysclk, with a division from the
SYSCLK rate specified (multiplied by 10 since a division of 5.5 is
supported) and the clock can be disabled by specifying a divisor of
zero.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>