• Imre Deak's avatar
    drm/i915/bxt, glk: Increase PCODE timeouts during CDCLK freq changing · e76019a8
    Imre Deak authored
    Currently we see sporadic timeouts during CDCLK changing both on BXT and
    GLK as reported by the Bugzilla: ticket. It's easy to reproduce this by
    changing the frequency in a tight loop after blanking the display. The
    upper bound for the completion time is 800us based on my tests, so
    increase it from the current 500us to 2ms; with that I couldn't trigger
    the problem either on BXT or GLK.
    
    Note that timeouts happened during both the change notification and the
    voltage level setting PCODE request. (For the latter one BSpec doesn't
    require us to wait for completion before further HW programming.)
    
    This issue is similar to
    commit 2c7d0602 ("drm/i915/gen9: Fix PCODE polling during CDCLK
    change notification")
    but there the PCODE request does complete (as shown by the mbox
    busy flag), only the reply we get from PCODE indicates a failure.
    So there we keep resending the request until a success reply, here we
    just have to increase the timeout for the one PCODE request we send.
    
    v2:
    - s/snb_pcode_request/sandybridge_pcode_write_timeout/ (Ville)
    
    Cc: Chris Wilson <chris@chris-wilson.co.uk>
    Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
    Cc: <stable@vger.kernel.org> # v4.4+
    Acked-by: Chris Wilson <chris@chris-wilson.co.uk> (v1)
    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103326Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
    Signed-off-by: default avatarImre Deak <imre.deak@intel.com>
    Link: https://patchwork.freedesktop.org/patch/msgid/20180130142939.17983-1-imre.deak@intel.com
    e76019a8
intel_cdclk.c 64.2 KB