The latest versions of Motorola erratas for the MPC745x CPUs (and 744x)
adds a couple of nasty ones for which we really want workarounds in the
kernel. One is to disable the BTIC branch target cache on some revs
(too bad for performances...) and the other one is to force cacheable
memory pages to always be marked as SMP coherent even on UP systems (I
didn't measure significant perfs impact with this one).
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>