• Suresh Siddha's avatar
    x86: Handle legacy PIC interrupts on all the cpu's · 36e9e1ea
    Suresh Siddha authored
    Ingo Molnar reported that with the recent changes of not
    statically blocking IRQ0_VECTOR..IRQ15_VECTOR's on all the
    cpu's, broke an AMD platform (with Nvidia chipset) boot when
    "noapic" boot option is used.
    
    On this platform, legacy PIC interrupts are getting delivered to
    all the cpu's instead of just the boot cpu. Thus not
    initializing the vector to irq mapping for the legacy irq's
    resulted in not handling certain interrupts causing boot hang.
    
    Fix this by initializing the vector to irq mapping on all the
    logical cpu's, if the legacy IRQ is handled by the legacy PIC.
    Reported-by: default avatarIngo Molnar <mingo@elte.hu>
    Signed-off-by: default avatarSuresh Siddha <suresh.b.siddha@intel.com>
    [ -v2: io-apic-enabled improvement ]
    Acked-by: default avatarYinghai Lu <yinghai@kernel.org>
    Cc: Eric W. Biederman <ebiederm@xmission.com>
    LKML-Reference: <1268692386.3296.43.camel@sbs-t61.sc.intel.com>
    Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
    36e9e1ea
irqinit.c 7.1 KB